coreboot-gerrit February 2020

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Change in coreboot[master]: superio/nuvoton/nct5104d: add chip config option to reset GPIOs
by Michał Żygowski (Code Review) 25 Mar '20

25 Mar '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38850 ) Change subject: superio/nuvoton/nct5104d: add chip config option to reset GPIOs ...................................................................... superio/nuvoton/nct5104d: add chip config option to reset GPIOs The devicetree interface to invoke the NCT5104d GPIO reset was too complicated and could cause debugging problems. Define a chip option to explicitly soft reset all enabled GPIOs to default state without the need of additional LDN usage. TEST=boot FreeBSD 11.2 on PC Engines apu1, change GPIO configuration using nctgpio module and check whether GPIOs are reset after reboot Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iae4205574800138402cbc95f4948167265a80d15 --- M src/mainboard/pcengines/apu1/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/superio/nuvoton/nct5104d/chip.h M src/superio/nuvoton/nct5104d/superio.c 7 files changed, 20 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38850/1 diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 767b0b0..ece40bb 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -43,6 +43,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -71,7 +72,6 @@ device pnp 2e.107 off end device pnp 2e.607 off end device pnp 2e.e off end - device pnp 2e.f on end end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 443e150..66f3a48 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -45,6 +45,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -73,7 +74,6 @@ device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.e off end - device pnp 2e.f on end end # SIO NCT5104D chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 524f30f..2806fd6 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -45,6 +45,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -73,7 +74,6 @@ device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.e off end - device pnp 2e.f on end end # SIO NCT5104D end # LPC 0x439d diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index 5aa0748..e28422d 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -45,6 +45,7 @@ device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D register "irq_trigger_type" = "0" + register "reset_gpios" = "1" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 @@ -73,7 +74,6 @@ device pnp 2e.107 on end device pnp 2e.607 off end device pnp 2e.e off end - device pnp 2e.f on end end # SIO NCT5104D end # LPC 0x439d diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index c819114..21667eb 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -66,7 +66,6 @@ end device pnp 2e.008 off end device pnp 2e.108 off end - device pnp 2e.f off end device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end diff --git a/src/superio/nuvoton/nct5104d/chip.h b/src/superio/nuvoton/nct5104d/chip.h index 5b79037..ad1c302 100644 --- a/src/superio/nuvoton/nct5104d/chip.h +++ b/src/superio/nuvoton/nct5104d/chip.h @@ -6,6 +6,7 @@ struct superio_nuvoton_nct5104d_config { u8 irq_trigger_type; + u8 reset_gpios; }; #endif diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index e49a7cb..60a879b 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */ +#include <stdlib.h> #include <console/console.h> #include <device/pnp.h> #include <device/device.h> @@ -100,40 +101,22 @@ pnp_set_logical_device(dev); /* Soft reset GPIOs to default state: IN */ - switch (dev->path.pnp.device) { - case NCT5104D_GPIO0: - pnp_write_config(dev, NCT5104D_GPIO0_IO, 0xFF); - break; - case NCT5104D_GPIO1: - pnp_write_config(dev, NCT5104D_GPIO1_IO, 0xFF); - break; - case NCT5104D_GPIO6: - pnp_write_config(dev, NCT5104D_GPIO6_IO, 0xFF); - break; - default: - break; - } + pnp_write_config(dev, NCT5104D_GPIO0_IO +(dev->path.pnp.device >> 8), + 0xFF); } static void reset_gpio_default_od(struct device *dev) { - struct device *gpio0, *gpio1, *gpio6; + struct device *gpio_pp_od = malloc(sizeof(struct device *)); - gpio0 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO0); - gpio1 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO1); - gpio6 = dev_find_slot_pnp(dev->path.pnp.port, NCT5104D_GPIO6); - - pnp_set_logical_device(dev); + gpio_pp_od->path.pnp.port = dev->path.pnp.port; + gpio_pp_od->path.pnp.device = NCT5104D_GPIO_PP_OD; + pnp_set_logical_device(gpio_pp_od); /* Soft reset GPIOs to default state: Open-drain */ - if (gpio0 && gpio0->enabled) - pnp_write_config(dev, NCT5104D_GPIO0_PP_OD, 0xFF); - - if (gpio1 && gpio1->enabled) - pnp_write_config(dev, NCT5104D_GPIO1_PP_OD, 0xFF); - - if (gpio6 && gpio6->enabled) - pnp_write_config(dev, NCT5104D_GPIO6_PP_OD, 0xFF); + pnp_write_config(gpio_pp_od, + (dev->path.pnp.device >> 8) + NCT5104D_GPIO0_PP_OD, + 0xFF); } static void disable_gpio_io_port(struct device *dev) @@ -181,13 +164,12 @@ case NCT5104D_GPIO0: case NCT5104D_GPIO1: route_pins_to_uart(dev, false); - reset_gpio_default_in(dev); - break; + /* FALLTHROUGH */ case NCT5104D_GPIO6: - reset_gpio_default_in(dev); - break; - case NCT5104D_GPIO_PP_OD: - reset_gpio_default_od(dev); + if(conf->reset_gpios) { + reset_gpio_default_in(dev); + reset_gpio_default_od(dev); + } break; case NCT5104D_GPIO_IO: disable_gpio_io_port(dev); @@ -218,7 +200,6 @@ { NULL, NCT5104D_GPIO0}, { NULL, NCT5104D_GPIO1}, { NULL, NCT5104D_GPIO6}, - { NULL, NCT5104D_GPIO_PP_OD}, { NULL, NCT5104D_GPIO_IO, PNP_IO0, 0x07f8, }, { NULL, NCT5104D_PORT80}, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/38850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae4205574800138402cbc95f4948167265a80d15 Gerrit-Change-Number: 38850 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

5 19

Change in ...coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503 Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+ ...................................................................... drivers/intel/gma: Add `new-pch.asl` for Skylake+ This should work as `pch.asl` equivalent for Skylake and later platforms. Untested. Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- A src/drivers/intel/gma/acpi/new-pch.asl 1 file changed, 42 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1 diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl new file mode 100644 index 0000000..b24a350 --- /dev/null +++ b/src/drivers/intel/gma/acpi/new-pch.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0xc8254), + BCLV, 16, + BCLM, 16 + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31503 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Gerrit-Change-Number: 31503 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

7 22

Change in coreboot[master]: mb/intel/jasperlake_rvp: Update FMAP for jslrvp
by Meera Ravindranath (Code Review) 25 Mar '20

25 Mar '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38273 ) Change subject: mb/intel/jasperlake_rvp: Update FMAP for jslrvp ...................................................................... mb/intel/jasperlake_rvp: Update FMAP for jslrvp Remove unused SMM_STORE space and use it for RW_LEGACY area BUG=None TEST=None Change-Id: I5724b860271025e8cb8b320ecbd33352ef779660 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/chromeos.fmd 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/38273/1 diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index f4db8b4..5f4f362 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -28,16 +28,15 @@ RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - SMMSTORE(PRESERVE)@0x5d0000 0x40000 - RW_LEGACY(CBFS)@0x610000 0x1c0000 - WP_RO@0x7d0000 0x430000 { + RW_LEGACY(CBFS)@0x5d0000 0x100000 + WP_RO@0x6d0000 0x330000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x42c000 { + RO_SECTION@0x4000 0x32c000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x33c000 + COREBOOT(CBFS)@0xf0000 0x23c000 } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/38273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5724b860271025e8cb8b320ecbd33352ef779660 Gerrit-Change-Number: 38273 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

7 10

Change in coreboot[master]: vendorcode/secunet: Add driver to read DMI info from I2C EEPROM
by Nico Huber (Code Review) 25 Mar '20

25 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36298 ) Change subject: vendorcode/secunet: Add driver to read DMI info from I2C EEPROM ...................................................................... vendorcode/secunet: Add driver to read DMI info from I2C EEPROM Change-Id: Iae5c9138e8404acfc3a43dc2c7b55d47d4147060 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/vendorcode/Makefile.inc A src/vendorcode/secunet/Kconfig A src/vendorcode/secunet/Makefile.inc A src/vendorcode/secunet/dmi/Makefile.inc A src/vendorcode/secunet/dmi/eeprom.h A src/vendorcode/secunet/dmi/smbios.c 6 files changed, 177 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/36298/1 diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 8ccb0d0..55c2bb1 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -4,3 +4,4 @@ subdirs-y += siemens subdirs-y += cavium subdirs-y += eltan +subdirs-y += secunet diff --git a/src/vendorcode/secunet/Kconfig b/src/vendorcode/secunet/Kconfig new file mode 100644 index 0000000..7e83f90 --- /dev/null +++ b/src/vendorcode/secunet/Kconfig @@ -0,0 +1,3 @@ +config SECUNET_DMI + bool + select SMBIOS_PROVIDED_BY_MOBO diff --git a/src/vendorcode/secunet/Makefile.inc b/src/vendorcode/secunet/Makefile.inc new file mode 100644 index 0000000..15d7360 --- /dev/null +++ b/src/vendorcode/secunet/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SECUNET_DMI) += dmi diff --git a/src/vendorcode/secunet/dmi/Makefile.inc b/src/vendorcode/secunet/dmi/Makefile.inc new file mode 100644 index 0000000..90da971 --- /dev/null +++ b/src/vendorcode/secunet/dmi/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += smbios.c diff --git a/src/vendorcode/secunet/dmi/eeprom.h b/src/vendorcode/secunet/dmi/eeprom.h new file mode 100644 index 0000000..c4cdd41 --- /dev/null +++ b/src/vendorcode/secunet/dmi/eeprom.h @@ -0,0 +1,62 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SECUNET_DMI_EEPROM_H +#define _SECUNET_DMI_EEPROM_H + +#include <stdint.h> + +enum bx26_strings { + BOARD_MATNR, + BOARD_SERIAL_NUMBER, + BOARD_VERSION, + BOARD_MCTRL_FW_VERSION, + BOARD_CCR_FW_VERSION, + BOARD_NIC_FW_VERSION, + BOARD_LP_VERSION, + BOARD_VERSION_ID, + + SYSTEM_PRODUCT_NAME, + SYSTEM_VERSION, + SYSTEM_SERIAL_NUMBER, + SYSTEM_UUID, + SYSTEM_MANUFACTURER, + SYSTEM_PRODUCTION_DATE, + SYSTEM_MLFB, + SYSTEM_MATNR, +}; + +struct bx26_location { + uint16_t offset; + uint16_t length; +}; + +static const struct bx26_location bx26_locations[] = { + [BOARD_MATNR] = { 0x0000, 0x20 }, + [BOARD_SERIAL_NUMBER] = { 0x0020, 0x20 }, + [BOARD_VERSION] = { 0x0040, 0x20 }, + [BOARD_MCTRL_FW_VERSION] = { 0x0060, 0x20 }, + [BOARD_CCR_FW_VERSION] = { 0x0080, 0x20 }, + [BOARD_NIC_FW_VERSION] = { 0x00a0, 0x20 }, + [BOARD_LP_VERSION] = { 0x00c0, 0x20 }, + [BOARD_VERSION_ID] = { 0x0100, 0x20 }, + + [SYSTEM_PRODUCT_NAME] = { 0x4000, 0x20 }, + [SYSTEM_VERSION] = { 0x4040, 0x10 }, + [SYSTEM_SERIAL_NUMBER] = { 0x4060, 0x10 }, + [SYSTEM_UUID] = { 0x4080, 0x24 }, + [SYSTEM_MANUFACTURER] = { 0x40c0, 0x20 }, + [SYSTEM_PRODUCTION_DATE] = { 0x4100, 0x20 }, + [SYSTEM_MLFB] = { 0x4140, 0x20 }, + [SYSTEM_MATNR] = { 0x4180, 0x20 }, +}; + +#endif diff --git a/src/vendorcode/secunet/dmi/smbios.c b/src/vendorcode/secunet/dmi/smbios.c new file mode 100644 index 0000000..c299516d --- /dev/null +++ b/src/vendorcode/secunet/dmi/smbios.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <ctype.h> +#include <commonlib/helpers.h> +#include <uuid.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c_bus.h> +#include <smbios.h> + +#include "eeprom.h" + +#define MAX_STRING_LENGTH 256 + +static struct device *eeprom; + +static const char *eeprom_read_string(const enum bx26_strings idx) +{ + static char str[MAX_STRING_LENGTH + 1]; + + if (!eeprom) { + printk(BIOS_WARNING, "DMI: Serial EEPROM not found\n"); + str[0] = '\0'; + return str; + } + + const size_t offset = bx26_locations[idx].offset; + const size_t length = MIN(bx26_locations[idx].length, MAX_STRING_LENGTH); + + if (i2c_dev_read_at16(eeprom, (u8 *)str, length, offset) != length) { + printk(BIOS_WARNING, "DMI: Failed to read serial EEPROM\n"); + str[0] = '\0'; + } else { + unsigned int i; + /* Terminate at first non-printable character. */ + for (i = 0; i < length; ++i) { + if (!isprint(str[i])) + break; + } + str[i] = '\0'; + } + + return str; +} + +const char *smbios_system_manufacturer(void) +{ + return eeprom_read_string(SYSTEM_MANUFACTURER); +} + +const char *smbios_system_product_name(void) +{ + return eeprom_read_string(SYSTEM_PRODUCT_NAME); +} + +const char *smbios_system_serial_number(void) +{ + return eeprom_read_string(SYSTEM_SERIAL_NUMBER); +} + +const char *smbios_system_version(void) +{ + return eeprom_read_string(SYSTEM_VERSION); +} + +void smbios_system_set_uuid(u8 *const uuid) +{ + if (parse_uuid(uuid, eeprom_read_string(SYSTEM_UUID))) { + printk(BIOS_WARNING, "DMI: Cannot parse UUID\n"); + memset(uuid, 0x00, UUID_LEN); + } +} + +const char *smbios_mainboard_serial_number(void) +{ + return eeprom_read_string(BOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + return eeprom_read_string(BOARD_VERSION); +} + +static void enable_dev(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_I2C || (dev->path.i2c.device & 0xf0) != 0x50) + return; + eeprom = dev; +} + +struct chip_operations vendorcode_secunet_dmi_ops = { + CHIP_NAME("secunet DMI") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/36298 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae5c9138e8404acfc3a43dc2c7b55d47d4147060 Gerrit-Change-Number: 36298 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: mb/ocp/tiogapass: Enable IPMI KCS
by Johnny Lin (Code Review) 25 Mar '20

25 Mar '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38995 ) Change subject: mb/ocp/tiogapass: Enable IPMI KCS ...................................................................... mb/ocp/tiogapass: Enable IPMI KCS Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b --- M src/mainboard/ocp/tiogapass/Kconfig M src/mainboard/ocp/tiogapass/devicetree.cb 2 files changed, 10 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38995/1 diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index ab0f789..41abb65 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -26,6 +26,7 @@ select SOC_INTEL_XEON_SP select MAINBOARD_USES_FSP2_0 select FSP_CAR + select IPMI_KCS config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 3ac0f56..decb81b 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -53,6 +53,8 @@ register "coherency_support" = "1" register "ats_support" = "1" + register "gen2_dec" = "0x000c0ca1" # IPMI KCS + device cpu_cluster 0 on device lapic 0 on end end @@ -83,7 +85,13 @@ device pci 17.0 on end # Intel Corporation C620 Series Chipset Family SATA Controller [AHCI mode] device pci 1c.0 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #1 device pci 1c.4 on end # PCI bridge: Intel Corporation C620 Series Chipset Family PCI Express Root Port #5 - device pci 1f.0 on end # Intel Corporation C621 Series Chipset LPC/eSPI Controller + device pci 1f.0 on + chip drivers/ipmi # BMC KCS + device pnp ca2.0 on end + register "bmc_i2c_address" = "0x20" + register "bmc_boot_timeout" = "60" + end + end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller device pci 1f.4 on end # Intel Corporation C620 Series Chipset Family SMBus device pci 1f.5 on end # Intel Corporation C620 Series Chipset Family SPI Controller -- To view, visit https://review.coreboot.org/c/coreboot/+/38995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3678973736a675ed22b5bc9da20a2ca947220f4b Gerrit-Change-Number: 38995 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: soc/intel/xeon_sp: Enable LPC generic IO decode range
by Johnny Lin (Code Review) 25 Mar '20

25 Mar '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38994 ) Change subject: soc/intel/xeon_sp: Enable LPC generic IO decode range ...................................................................... soc/intel/xeon_sp: Enable LPC generic IO decode range To use Intel common block LPC function that enables the IO ranges defined in devicetree.cb. Tested on OCP Tioga Pass with BMC LPC working. Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8 --- M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/bootblock/bootblock.c A src/soc/intel/xeon_sp/bootblock/pch.c M src/soc/intel/xeon_sp/chip.h A src/soc/intel/xeon_sp/include/soc/bootblock.h M src/soc/intel/xeon_sp/lpc.c 6 files changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/38994/1 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index c4db44c..3e7dadb 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -26,6 +26,8 @@ subdirs-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/pch.c +bootblock-y += lpc.c bootblock-y += spi.c postcar-y += soc_util.c diff --git a/src/soc/intel/xeon_sp/bootblock/bootblock.c b/src/soc/intel/xeon_sp/bootblock/bootblock.c index 15435fa..835f03c 100644 --- a/src/soc/intel/xeon_sp/bootblock/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <intelblocks/rtc.h> #include <intelblocks/fast_spi.h> #include <soc/iomap.h> +#include <soc/bootblock.h> #include <spi-generic.h> #include <timestamp.h> #include <console/console.h> @@ -55,6 +56,7 @@ void bootblock_soc_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); + pch_early_iorange_init(); } void bootblock_soc_init(void) diff --git a/src/soc/intel/xeon_sp/bootblock/pch.c b/src/soc/intel/xeon_sp/bootblock/pch.c new file mode 100644 index 0000000..6b7b27d --- /dev/null +++ b/src/soc/intel/xeon_sp/bootblock/pch.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2019 Intel Corporation. + * Copyright (C) 2020 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <intelblocks/lpc_lib.h> +#include <soc/bootblock.h> + +void pch_early_iorange_init(void) +{ + /* Program generic IO Decode Range */ + pch_enable_lpc(); +} diff --git a/src/soc/intel/xeon_sp/chip.h b/src/soc/intel/xeon_sp/chip.h index 046c746..fda6498 100644 --- a/src/soc/intel/xeon_sp/chip.h +++ b/src/soc/intel/xeon_sp/chip.h @@ -82,6 +82,12 @@ uint32_t vtd_support; uint32_t coherency_support; uint32_t ats_support; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; extern struct chip_operations soc_intel_xeon_sp_ops; diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h new file mode 100644 index 0000000..77f3516 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2020 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOOTBLOCK_H_ +#define _SOC_BOOTBLOCK_H_ + +void pch_early_iorange_init(void); + +#endif diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index d4e5d9d..0bd81b4 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -18,8 +18,12 @@ #include <console/console.h> #include <arch/ioapic.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> #include <soc/soc_util.h> #include <soc/iomap.h> +#include <soc/pcr_ids.h> + +#include "chip.h" static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { { 0, 0 } @@ -30,6 +34,25 @@ return xeon_lpc_fixed_mmio_ranges; } +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const config_t *config = config_of(dev); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) +{ + /* Mirror these same settings in DMI PCR */ + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]); + pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]); +} + void lpc_soc_init(struct device *dev) { printk(BIOS_SPEW, "pch: lpc_init\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/38994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I675489d3c66dad259e4101a17300176f6c0e8bd8 Gerrit-Change-Number: 38994 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

5 23

Change in coreboot[master]: mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xe
by Michał Żygowski (Code Review) 25 Mar '20

25 Mar '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38851 ) Change subject: mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xe ...................................................................... mb/pcengines/*/devicetree: remove non-existing NCT5104d LDN 0xe Nuvoton NCT5104d has no LDN 0xe according to its datasheet. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I0d34218d88b779b08c380d2396ff9ab9253597fa --- M src/mainboard/pcengines/apu1/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb 5 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/38851/1 diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index ece40bb..c280c4c 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -71,7 +71,6 @@ device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end - device pnp 2e.e off end end chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 66f3a48..fee5051 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -73,7 +73,6 @@ device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end - device pnp 2e.e off end end # SIO NCT5104D chip drivers/pc80/tpm device pnp 0c31.0 on end diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 2806fd6..66a3b6f 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -73,7 +73,6 @@ device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end - device pnp 2e.e off end end # SIO NCT5104D end # LPC 0x439d diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index e28422d..d19b546 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -73,7 +73,6 @@ device pnp 2e.007 on end device pnp 2e.107 on end device pnp 2e.607 off end - device pnp 2e.e off end end # SIO NCT5104D end # LPC 0x439d diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index 21667eb..c5b20d3 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -69,7 +69,6 @@ device pnp 2e.007 off end device pnp 2e.107 off end device pnp 2e.607 off end - device pnp 2e.e off end end # SIO NCT5104D chip drivers/pc80/tpm device pnp 0c31.0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/38851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d34218d88b779b08c380d2396ff9ab9253597fa Gerrit-Change-Number: 38851 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

6 7

Change in coreboot[master]: soc/intel/skylake: Add Lewisburg PCH GPIOs support
by Maxim Polyakov (Code Review) 23 Mar '20

23 Mar '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35031 ) Change subject: soc/intel/skylake: Add Lewisburg PCH GPIOs support ...................................................................... soc/intel/skylake: Add Lewisburg PCH GPIOs support The pin layout in this patch corresponds to the driver in the linux kernel for Lewisburg PCH GPIO hardware [1] [1] drivers/pinctrl/intel/pinctrl-lewisburg.c These changes are in accordance with the documentation: [*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub (PCH) Datasheet, May 2019. Document Number: 336067-007US Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/gpio_defs.h A src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h M src/soc/intel/skylake/include/soc/pcr_ids.h 5 files changed, 440 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/35031/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 13c1517..34fd97c 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -175,6 +175,12 @@ help Choose this option if you have a PCH-H chipset. +config WELISBURG_SOC_PCH_H + bool + default n + help + Choose this option if you have the Lewisburg C62x PCH chipset. + config NHLT_DMIC_2CH bool default n diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 67edeae..0130936 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -36,6 +36,9 @@ static const struct pad_group skl_community_com0_groups[] = { INTEL_GPP(GPP_A0, GPP_A0, GPP_A23), /* GPP A */ INTEL_GPP(GPP_A0, GPP_B0, GPP_B23), /* GPP B */ +#if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_A0, GPP_F0, GPP_F23), /* GPP F */ +#endif }; static const struct pad_group skl_community_com1_groups[] = { @@ -48,19 +51,38 @@ INTEL_GPP(GPP_C0, GPP_H0, GPP_H23), /* GPP H */ #else INTEL_GPP(GPP_C0, GPP_D0, GPP_D23), /* GPP D */ +# if CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_C0, GPP_E0, GPP_E12), /* GPP E */ +# else INTEL_GPP(GPP_C0, GPP_E0, GPP_E23), /* GPP E */ +# endif #endif }; static const struct pad_group skl_community_com3_groups[] = { #if CONFIG(SKYLAKE_SOC_PCH_H) INTEL_GPP(GPP_I0, GPP_I0, GPP_I10), /* GPP I */ +#elif CONFIG(WELISBURG_SOC_PCH_H) + INTEL_GPP(GPP_I0, GPP_I0, RCOMP_3P3), /* GPP I */ #else INTEL_GPP(GPP_F0, GPP_F0, GPP_F23), /* GPP F */ INTEL_GPP(GPP_F0, GPP_G0, GPP_G7), /* GPP G */ #endif }; +#if CONFIG(WELISBURG_SOC_PCH_H) +static const struct pad_group skl_community_com4_groups[] = { + INTEL_GPP(GPP_J0, GPP_J0, GPP_J23), /* GPP F */ + INTEL_GPP(GPP_J0, GPP_K0, RCOMP_1P8_3P3), /* GPP G */ +}; + +static const struct pad_group skl_community_com5_groups[] = { + INTEL_GPP(GPP_J0, GPP_G0, GPP_G23), /* GPP G */ + INTEL_GPP(GPP_J0, GPP_H0, GPP_H23), /* GPP H */ + INTEL_GPP(GPP_J0, GPP_L2, GPP_L19), /* GPP L */ +}; +#endif + static const struct pad_group skl_community_com2_groups[] = { INTEL_GPP(GPD0, GPD0, GPD11), /* GPP GDP */ }; @@ -69,7 +91,11 @@ { .port = PID_GPIOCOM0, .first_pad = GPP_A0, +#if CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_F23, +#else .last_pad = GPP_B23, +#endif .num_gpi_regs = NUM_GPIO_COM0_GPI_REGS, .pad_cfg_base = PAD_CFG_BASE, .host_own_reg_0 = HOSTSW_OWN_REG_0, @@ -89,6 +115,8 @@ .first_pad = GPP_C0, #if CONFIG(SKYLAKE_SOC_PCH_H) .last_pad = GPP_H23, +#elif CONFIG(WELISBURG_SOC_PCH_H) + .last_pad = GPP_E12, #else .last_pad = GPP_E23, #endif @@ -108,7 +136,7 @@ .num_groups = ARRAY_SIZE(skl_community_com1_groups), }, { .port = PID_GPIOCOM3, -#if CONFIG(SKYLAKE_SOC_PCH_H) +#if CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H) .first_pad = GPP_I0, .last_pad = GPP_I10, #else @@ -130,6 +158,44 @@ .groups = skl_community_com3_groups, .num_groups = ARRAY_SIZE(skl_community_com3_groups), }, { +#if CONFIG(WELISBURG_SOC_PCH_H) + .port = PID_GPIOCOM4, + .first_pad = GPP_J0, + .last_pad = GPP_K10, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com4_groups, + .num_groups = ARRAY_SIZE(skl_community_com4_groups), + }, { + .port = PID_GPIOCOM4, + .first_pad = GPP_G0, + .last_pad = GPP_L19, + .num_gpi_regs = NUM_GPIO_COM4_GPI_REGS, + .pad_cfg_base = PAD_CFG_BASE, + .host_own_reg_0 = HOSTSW_OWN_REG_0, + .gpi_int_sts_reg_0 = GPI_INT_STS_0, + .gpi_int_en_reg_0 = GPI_INT_EN_0, + .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, + .gpi_smi_en_reg_0 = GPI_SMI_EN_0, + .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, + .name = "GPIO_COM4", + .acpi_path = "\\_SB.PCI0.GPIO", + .reset_map = rst_map, + .num_reset_vals = ARRAY_SIZE(rst_map), + .groups = skl_community_com5_groups, + .num_groups = ARRAY_SIZE(skl_community_com5_groups), + }, { +#endif .port = PID_GPIOCOM2, .first_pad = GPD0, .last_pad = GPD11, @@ -161,17 +227,27 @@ static const struct pmc_to_gpio_route routes[] = { { GPP_A, GPP_A}, { GPP_B, GPP_B}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_F, GPP_F}, +#endif { GPP_C, GPP_C}, { GPP_D, GPP_D}, { GPP_E, GPP_E}, +#if CONFIG(WELISBURG_SOC_PCH_H) + { GPP_I, GPP_I}, + { GPP_J, GPP_J}, + { GPP_K, GPP_K}, +#else { GPP_F, GPP_F}, { GPP_G, GPP_G}, -#if CONFIG(SKYLAKE_SOC_PCH_H) +# if CONFIG(SKYLAKE_SOC_PCH_H) { GPP_H, GPP_H}, { GPP_I, GPP_I}, +# endif #endif { GPD, GPD}, }; + *num = ARRAY_SIZE(routes); return routes; } @@ -179,7 +255,7 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg, int dw_reg, uint32_t reg_val) { - if (CONFIG(SKYLAKE_SOC_PCH_H)) + if (CONFIG(SKYLAKE_SOC_PCH_H) || CONFIG(WELISBURG_SOC_PCH_H)) return reg_val; /* * For U/Y series, clear PAD_CFG1_TOL_1V8 in GPP_F4 diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 321d3c2..0285989 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -20,6 +20,8 @@ #endif #if CONFIG(SKYLAKE_SOC_PCH_H) # include <soc/gpio_pch_h_defs.h> +#elif CONFIG(WELISBURG_SOC_PCH_H) +# include <soc/gpio_wlb_pch_defs.h> #else # include <soc/gpio_soc_defs.h> #endif @@ -33,6 +35,22 @@ #define NUM_GPIO_COM1_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM1_PADS) #define NUM_GPIO_COM2_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM2_PADS) #define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM3_PADS) +#if CONFIG(WELISBURG_SOC_PCH_H) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM4_PADS) +# define NUM_GPIO_COM3_GPI_REGS NUM_GPIO_COMx_GPI_REGS(NUM_GPIO_COM5_PADS) +#endif + +#if CONFIG(WELISBURG_SOC_PCH_H) + +#define NUM_GPI_STATUS_REGS \ + ((NUM_GPIO_COM0_GPI_REGS) +\ + (NUM_GPIO_COM1_GPI_REGS) +\ + (NUM_GPIO_COM3_GPI_REGS) +\ + (NUM_GPIO_COM4_GPI_REGS) +\ + (NUM_GPIO_COM5_GPI_REGS) +\ + (NUM_GPIO_COM2_GPI_REGS) +\ + +#else #define NUM_GPI_STATUS_REGS \ ((NUM_GPIO_COM0_GPI_REGS) +\ @@ -218,6 +236,8 @@ #define GPD10_IRQ 0x5a #define GPD11_IRQ 0x5b +#endif + /* Register defines. */ #define GPIO_MISCCFG 0x10 #define GPIO_DRIVER_IRQ_ROUTE_MASK 8 diff --git a/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h new file mode 100644 index 0000000..636837c --- /dev/null +++ b/src/soc/intel/skylake/include/soc/gpio_wlb_pch_defs.h @@ -0,0 +1,333 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_WLB_PCH_DEFS_H_ +#define _SOC_GPIO_WLB_PCH_DEFS_H_ + +/* GPIO Community 0 */ +#define GPP_A 0x0 +#define GPP_B 0x1 +#define GPP_F 0x2 +/* GPIO Community 1 */ +#define GPP_C 0x3 +#define GPP_D 0x4 +#define GPP_E 0x5 +/* GPIO Community 3 */ +#define GPP_I 0x6 +/* GPIO Community 4 */ +#define GPP_J 0x7 +#define GPP_K 0x8 +/* GPIO Community 5 */ +#define GPP_G 0x9 +#define GPP_H 0xA +#define GPP_L 0xB +/* GPIO Community 2 */ +#define GPD 0xC + +#define GPIO_NUM_GROUPS 13 +#define GPIO_MAX_NUM_PER_GROUP 24 + +/* Group A */ +#define GPP_A0 0 +#define GPP_A1 1 +#define GPP_A2 2 +#define GPP_A3 3 +#define GPP_A4 4 +#define GPP_A5 5 +#define GPP_A6 6 +#define GPP_A7 7 +#define GPP_A8 8 +#define GPP_A9 9 +#define GPP_A10 10 +#define GPP_A11 11 +#define GPP_A12 12 +#define GPP_A13 13 +#define GPP_A14 14 +#define GPP_A15 15 +#define GPP_A16 16 +#define GPP_A17 17 +#define GPP_A18 18 +#define GPP_A19 19 +#define GPP_A20 20 +#define GPP_A21 21 +#define GPP_A22 22 +#define GPP_A23 23 +/* Group B */ +#define GPP_B0 24 +#define GPP_B1 25 +#define GPP_B2 26 +#define GPP_B3 27 +#define GPP_B4 28 +#define GPP_B5 29 +#define GPP_B6 30 +#define GPP_B7 31 +#define GPP_B8 32 +#define GPP_B9 33 +#define GPP_B10 34 +#define GPP_B11 35 +#define GPP_B12 36 +#define GPP_B13 37 +#define GPP_B14 38 +#define GPP_B15 39 +#define GPP_B16 40 +#define GPP_B17 41 +#define GPP_B18 42 +#define GPP_B19 43 +#define GPP_B20 44 +#define GPP_B21 45 +#define GPP_B22 46 +#define GPP_B23 47 +/* Group F */ +#define GPP_F0 48 +#define GPP_F1 49 +#define GPP_F2 50 +#define GPP_F3 51 +#define GPP_F4 52 +#define GPP_F5 53 +#define GPP_F6 54 +#define GPP_F7 55 +#define GPP_F8 56 +#define GPP_F9 57 +#define GPP_F10 58 +#define GPP_F11 59 +#define GPP_F12 60 +#define GPP_F13 61 +#define GPP_F14 62 +#define GPP_F15 63 +#define GPP_F16 64 +#define GPP_F17 65 +#define GPP_F18 66 +#define GPP_F19 67 +#define GPP_F20 68 +#define GPP_F21 69 +#define GPP_F22 70 +#define GPP_F23 71 + +#define NUM_GPIO_COM0_PADS (GPP_F23 - GPP_A0 + 1) + +/* Group C */ +#define GPP_C0 72 +#define GPP_C1 73 +#define GPP_C2 74 +#define GPP_C3 75 +#define GPP_C4 76 +#define GPP_C5 77 +#define GPP_C6 78 +#define GPP_C7 79 +#define GPP_C8 80 +#define GPP_C9 81 +#define GPP_C10 82 +#define GPP_C11 83 +#define GPP_C12 84 +#define GPP_C13 85 +#define GPP_C14 86 +#define GPP_C15 87 +#define GPP_C16 88 +#define GPP_C17 89 +#define GPP_C18 90 +#define GPP_C19 91 +#define GPP_C20 92 +#define GPP_C21 93 +#define GPP_C22 94 +#define GPP_C23 95 +/* Group D */ +#define GPP_D0 96 +#define GPP_D1 97 +#define GPP_D2 98 +#define GPP_D3 99 +#define GPP_D4 100 +#define GPP_D5 101 +#define GPP_D6 102 +#define GPP_D7 103 +#define GPP_D8 104 +#define GPP_D9 105 +#define GPP_D10 106 +#define GPP_D11 107 +#define GPP_D12 108 +#define GPP_D13 109 +#define GPP_D14 110 +#define GPP_D15 111 +#define GPP_D16 112 +#define GPP_D17 113 +#define GPP_D18 114 +#define GPP_D19 115 +#define GPP_D20 116 +#define GPP_D21 117 +#define GPP_D22 118 +#define GPP_D23 119 +/* Group E */ +#define GPP_E0 120 +#define GPP_E1 121 +#define GPP_E2 122 +#define GPP_E3 123 +#define GPP_E4 124 +#define GPP_E5 125 +#define GPP_E6 126 +#define GPP_E7 127 +#define GPP_E8 128 +#define GPP_E9 129 +#define GPP_E10 130 +#define GPP_E11 131 +#define GPP_E12 132 + +#define NUM_GPIO_COM1_PADS (GPP_E12 - GPP_C0 + 1) + +/* Group I */ +#define GPP_I0 133 +#define GPP_I1 134 +#define GPP_I2 135 +#define GPP_I3 136 +#define GPP_I4 137 +#define GPP_I5 138 +#define GPP_I6 139 +#define GPP_I7 140 +#define GPP_I8 141 +#define GPP_I9 142 +#define GPP_I10 143 +#define RCOMP_3P3 144 + +#define NUM_GPIO_COM3_PADS (RCOMP_3P3 - GPP_I0 + 1) + +/* Group J */ +#define GPP_J0 145 +#define GPP_J1 146 +#define GPP_J2 147 +#define GPP_J3 148 +#define GPP_J4 149 +#define GPP_J5 150 +#define GPP_J6 151 +#define GPP_J7 152 +#define GPP_J8 153 +#define GPP_J9 154 +#define GPP_J10 155 +#define GPP_J11 156 +#define GPP_J12 157 +#define GPP_J13 158 +#define GPP_J14 159 +#define GPP_J15 160 +#define GPP_J16 161 +#define GPP_J17 162 +#define GPP_J18 163 +#define GPP_J19 164 +#define GPP_J20 165 +#define GPP_J21 166 +#define GPP_J22 167 +#define GPP_J23 168 +/* Group K */ +#define GPP_K0 169 +#define GPP_K1 170 +#define GPP_K2 171 +#define GPP_K3 172 +#define GPP_K4 173 +#define GPP_K5 174 +#define GPP_K6 175 +#define GPP_K7 176 +#define GPP_K8 177 +#define GPP_K9 178 +#define GPP_K10 179 + +#define RCOMP_1P8_3P3 180 + +#define NUM_GPIO_COM4_PADS (RCOMP_1P8_3P3 - GPP_J0 + 1) + +/* Group G */ +#define GPP_G0 181 +#define GPP_G1 182 +#define GPP_G2 183 +#define GPP_G3 184 +#define GPP_G4 185 +#define GPP_G5 186 +#define GPP_G6 187 +#define GPP_G7 188 +#define GPP_G8 189 +#define GPP_G9 190 +#define GPP_G10 191 +#define GPP_G11 192 +#define GPP_G12 193 +#define GPP_G13 194 +#define GPP_G14 195 +#define GPP_G15 196 +#define GPP_G16 197 +#define GPP_G17 198 +#define GPP_G18 199 +#define GPP_G19 200 +#define GPP_G20 201 +#define GPP_G21 202 +#define GPP_G22 203 +#define GPP_G23 204 +/* Group H */ +#define GPP_H0 205 +#define GPP_H1 206 +#define GPP_H2 207 +#define GPP_H3 208 +#define GPP_H4 209 +#define GPP_H5 210 +#define GPP_H6 211 +#define GPP_H7 212 +#define GPP_H8 213 +#define GPP_H9 214 +#define GPP_H10 215 +#define GPP_H11 216 +#define GPP_H12 217 +#define GPP_H13 218 +#define GPP_H14 219 +#define GPP_H15 220 +#define GPP_H16 221 +#define GPP_H17 222 +#define GPP_H18 223 +#define GPP_H19 224 +#define GPP_H20 225 +#define GPP_H21 226 +#define GPP_H22 227 +#define GPP_H23 228 +/* Group L */ +#define GPP_L2 229 +#define GPP_L3 230 +#define GPP_L4 231 +#define GPP_L5 232 +#define GPP_L6 233 +#define GPP_L7 234 +#define GPP_L8 235 +#define GPP_L9 236 +#define GPP_L10 237 +#define GPP_L11 238 +#define GPP_L12 239 +#define GPP_L13 240 +#define GPP_L14 241 +#define GPP_L15 242 +#define GPP_L16 243 +#define GPP_L17 244 +#define GPP_L18 245 +#define GPP_L19 246 + +#define NUM_GPIO_COM5_PADS (GPP_L23 - GPP_G0 + 1) + +/* Group GPD */ +#define GPD0 247 +#define GPD1 248 +#define GPD2 249 +#define GPD3 250 +#define GPD4 251 +#define GPD5 252 +#define GPD6 253 +#define GPD7 254 +#define GPD8 255 +#define GPD9 256 +#define GPD10 257 +#define GPD11 258 + +#define NUM_GPIO_COM2_PADS (GPD11 - GPD0 + 1) + +#endif diff --git a/src/soc/intel/skylake/include/soc/pcr_ids.h b/src/soc/intel/skylake/include/soc/pcr_ids.h index 71affd8..1185e17 100644 --- a/src/soc/intel/skylake/include/soc/pcr_ids.h +++ b/src/soc/intel/skylake/include/soc/pcr_ids.h @@ -20,6 +20,8 @@ * Port ids */ #define PID_PSTH 0x89 +#define PID_GPIOCOM5 0x11 +#define PID_GPIOCOM4 0xAB #define PID_GPIOCOM3 0xAC #define PID_GPIOCOM2 0xAD #define PID_GPIOCOM1 0xAE -- To view, visit https://review.coreboot.org/c/coreboot/+/35031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia72c37121fa9616e4ef0ce4acfb36188363c231e Gerrit-Change-Number: 35031 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

4 24

Change in coreboot[master]: WIP: skylake-sp: Hook up IIO code
by Andrey Petrov (Code Review) 23 Mar '20

23 Mar '20

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39017 ) Change subject: WIP: skylake-sp: Hook up IIO code ...................................................................... WIP: skylake-sp: Hook up IIO code This patch is a piece of CB:38549 TEST=On OCP Tioga Pass board this patchset successfully boots into linux kernel as payload. Change-Id: I6f329de7bd4f18cc2e5c0002983816a4c6c7c5c2 --- M src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c 1 file changed, 4 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/39017/1 diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c index ed68c5f..058cf2c 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c @@ -21,23 +21,12 @@ #include <device/pci_ops.h> #include <fsp/api.h> #include <lib.h> - -static void skxsp_pci_domain_read_resources(struct device *dev) -{ -} - -static void skxsp_pci_domain_set_resources(struct device *dev) -{ -} - -static void skxsp_pci_domain_scan_bus(struct device *dev) -{ -} +#include <soc/iio.h> static struct device_operations pci_domain_ops = { - .read_resources = &skxsp_pci_domain_read_resources, - .set_resources = &skxsp_pci_domain_set_resources, - .scan_bus = &skxsp_pci_domain_scan_bus, + .read_resources = &pci_domain_read_resources, + .set_resources = &xeonsp_pci_domain_set_resources, + .scan_bus = &xeonsp_pci_domain_scan_bus, }; static void init_cpus(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/39017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f329de7bd4f18cc2e5c0002983816a4c6c7c5c2 Gerrit-Change-Number: 39017 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: WIP: IIO work
by Andrey Petrov (Code Review) 23 Mar '20

23 Mar '20

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38986 ) Change subject: WIP: IIO work ...................................................................... WIP: IIO work This is work-in-progress, with the goal to identify common parts of IIO-related housekeeping functionality in different Xeons. Change-Id: I2c459fc5deb885c5f979499b75dc95633bb6c00f Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/xeonsp/Makefile.inc M src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c A src/cpu/intel/xeonsp/iio.c A src/cpu/intel/xeonsp/include/soc/fsp_hobs.h A src/cpu/intel/xeonsp/include/soc/iio.h 5 files changed, 135 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/38986/1 diff --git a/src/cpu/intel/xeonsp/Makefile.inc b/src/cpu/intel/xeonsp/Makefile.inc index e9abf59..c1452f4 100644 --- a/src/cpu/intel/xeonsp/Makefile.inc +++ b/src/cpu/intel/xeonsp/Makefile.inc @@ -21,7 +21,7 @@ bootblock-y += bootblock.c romstage-y += ../../../cpu/intel/car/romstage.c romstage-y += postcar.c romstage.c -ramstage-y += model_xeonsp_init.c lpc.c ramstage.c +ramstage-y += model_xeonsp_init.c lpc.c ramstage.c iio.c CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c index 10a6855..e5685ab 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c @@ -21,6 +21,7 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/pci.h> +#include <soc/iio.h> static void skxsp_pci_domain_read_resources(struct device *dev) { @@ -69,6 +70,7 @@ /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; + attach_iio_stacks(dev); } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; diff --git a/src/cpu/intel/xeonsp/iio.c b/src/cpu/intel/xeonsp/iio.c new file mode 100644 index 0000000..ae721cc --- /dev/null +++ b/src/cpu/intel/xeonsp/iio.c @@ -0,0 +1,93 @@ +#include <assert.h> +#include <soc/hob_mem.h> +#include <soc/hob_iiouds.h> +#include <soc/iio.h> +#include <stdlib.h> + +static void get_iiostack_info(struct iiostack_resource *info) +{ + size_t hob_size; + u8 stack_no; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; + + memset(info, 0, sizeof(struct iiostack_resource)); + + hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, + &hob_size); + assert(hob != NULL && hob_size != 0); + + // find out total number of stacks + info->no_of_stacks = 0; + info->sres = NULL; + for (int s=0; s < hob->PlatformData.numofIIO; ++s) { + for (int x=0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? + ++info->no_of_stacks; + } + } + assert(info->no_of_stacks > 0); + + // allocate and copy stack info from FSP HOB + info->sres = malloc(info->no_of_stacks * sizeof(STACK_RES)); + if (info->sres == 0) + die("build_stack_info(): out of memory.\n"); + memset(info->sres, 0, info->no_of_stacks * sizeof(STACK_RES)); + + stack_no = 0; + for (int s=0; s < hob->PlatformData.numofIIO; ++s) { + for (int x=0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + if (ri->BusBase < ri->BusLimit) // TODO: do we have situation with only bux 0 and one stack? + memcpy(&info->sres[stack_no++], ri, sizeof(STACK_RES)); + } + } +} + + +/* Attach IIO stack bus numbers with dummy device to PCI DOMAIN 0000 device */ +void attach_iio_stacks(struct device *dev) +{ + struct bus *iiostack_bus; + struct device dummy; + struct iiostack_resource stack_info; + + get_iiostack_info(&stack_info); + for (int s=0; s < stack_info.no_of_stacks; ++s) { + printk(BIOS_DEBUG, "Attaching stack 0x%x to device %s\n", stack_info.sres[s].BusBase, dev_path(dev)); + if (stack_info.sres[s].BusBase == 0) /* only non zero bus no. needs to be enumerated */ + continue; + + iiostack_bus = malloc(sizeof(struct bus)); + if (iiostack_bus == 0) + die("attach_iio_stacks(): out of memory.\n"); + memset(iiostack_bus, 0, sizeof(struct bus)); + memcpy(iiostack_bus, dev->bus, sizeof(struct bus)); + iiostack_bus->secondary = stack_info.sres[s].BusBase; + iiostack_bus->subordinate = stack_info.sres[s].BusBase; + iiostack_bus->dev = NULL; + iiostack_bus->children = NULL; + iiostack_bus->next = NULL; + iiostack_bus->link_num = 1; + + dummy.bus = iiostack_bus; + dummy.path.type = DEVICE_PATH_PCI; + dummy.path.pci.devfn = 0; + u32 id = pci_read_config32(&dummy, PCI_VENDOR_ID); + if (id == 0xffffffff) + printk(BIOS_WARNING, "IIO Stack device %s not visible\n", dev_path(&dummy)); + + if (dev->link_list == NULL) { + dev->link_list = iiostack_bus; + } + else { + struct bus *nlink = dev->link_list; + while (nlink->next != NULL) + nlink = nlink->next; + nlink->next = iiostack_bus; + } + } +} + diff --git a/src/cpu/intel/xeonsp/include/soc/fsp_hobs.h b/src/cpu/intel/xeonsp/include/soc/fsp_hobs.h new file mode 100644 index 0000000..fc9edbb --- /dev/null +++ b/src/cpu/intel/xeonsp/include/soc/fsp_hobs.h @@ -0,0 +1,25 @@ +#ifndef _FSP_HOBS_H_ +#define _FSP_HOBS_H_ + +#include <fsp/util.h> +#include <soc/hob_mem.h> +#include <soc/hob_iiouds.h> + +#define MAX_IIO_STACK 6 +#define MAX_KTI_PORTS 3 +#define MAX_SOCKET 2 +#define NUMBER_PORTS_PER_SOCKET 21 +#define MaxIIO MAX_SOCKET +#define CONFIG_TDP_MAX_LEVEL 5 +#define MAX_IMC 2 +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) +#define MAX_TAD_RULES 20 +#define MAX_TAD_WAYS 3 +#define SAD_RULES 24 + +#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \ + 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ + 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ +} + +#endif diff --git a/src/cpu/intel/xeonsp/include/soc/iio.h b/src/cpu/intel/xeonsp/include/soc/iio.h new file mode 100644 index 0000000..12a8dd3 --- /dev/null +++ b/src/cpu/intel/xeonsp/include/soc/iio.h @@ -0,0 +1,14 @@ +#ifndef SOC_IIO_H +#define SOC_IIO_H + +#include <device/pci.h> +#include <soc/fsp_hobs.h> + +struct iiostack_resource { + uint8_t no_of_stacks; + STACK_RES *sres; +}; + +void attach_iio_stacks(struct device *dev); + +#endif \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/38986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c459fc5deb885c5f979499b75dc95633bb6c00f Gerrit-Change-Number: 38986 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020