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Change in coreboot[master]: WIP: Add VTD
by Andrey Petrov (Code Review) 23 Mar '20

23 Mar '20

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38985 ) Change subject: WIP: Add VTD ...................................................................... WIP: Add VTD Change-Id: If3cb271a974f06d24ff17987595b700e7bdadc47 --- M src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc M src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c M src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h A src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h A src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h A src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c 6 files changed, 425 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/38985/1 diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc index 50da224..053f372 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc @@ -13,7 +13,7 @@ ## romstage-y += romstage.c -ramstage-y += chip.c +ramstage-y += chip.c mmapvtd.c CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c index 52488d8..10a6855 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c @@ -18,6 +18,9 @@ #include <device/device.h> #include <fsp/api.h> #include <lib.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/pci.h> static void skxsp_pci_domain_read_resources(struct device *dev) { diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h index fba62a3..b97f4f8 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/pci_devs.h @@ -32,4 +32,22 @@ #define PCH_DEV_LPC _PCH_DEV(LPC, 0) #define PCH_DEV_P2SB _PCH_DEV(LPC, 1) +/* Skylake SP devices, registers */ +#define SKXSP_MMAP_VTD_CFG_REG_DEVID 0x2024 +#define SKXSP_VTD_DEV 5 +#define SKXSP_VTD_FUNC 0 +#define SKXSP_VTD_MMCFG_BASE_CSR 0x90 +#define SKXSP_VTD_MMCFG_LIMIT_CSR 0x98 +#define SKXSP_VTD_TSEG_BASE_CSR 0xa8 +#define SKXSP_VTD_TSEG_LIMIT_CSR 0xac +#define SKXSP_VTD_TOLM_CSR 0xd0 +#define SKXSP_VTD_TOHM_CSR 0xd4 +#define SKXSP_VTD_MMIOL_CSR 0xdc +#define SKXSP_VTD_ME_BASE_CSR 0xf0 +#define SKXSP_VTD_ME_LIMIT_CSR 0xf8 +#define SKXSP_SAD_ALL_DEV 29 +#define SKXSP_SAD_ALL_FUNC 0 +#define SKXSP_SAD_ALL_PAM0123_CSR 0x40 +#define SKXSP_SAD_ALL_PAM456_CSR 0x44 + #endif diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h new file mode 100644 index 0000000..7b994ca --- /dev/null +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_iomap.h @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _SKYLAKESP_IOMAP_H_ +#define _SKYLAKESP_IOMAP_H_ + +#define APEI_ERST_BASE_ADDRESS 0x6a7a9000 +#define APEI_ERST_BASE_SIZE (0x6c8a8fff - APEI_ERST_BASE_ADDRESS + 1) + +#endif diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h new file mode 100644 index 0000000..4b72e231 --- /dev/null +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/include/soc/skx_log_utils.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SKX_LOG_UTILS_H_ +#define _SKX_LOG_UTILS_H_ + +#define LOG_MEM_RESOURCE(type, dev, index, base_kb, size_kb) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size_kb: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, (base_kb << 10), (base_kb << 10) + (size_kb << 10) - 1, size_kb) + +#define LOG_IO_RESOURCE(type, dev, index, base, size) \ + printk(BIOS_SPEW, "%s:%d res: %s, dev: %s, index: 0x%x, base: 0x%llx, end: 0x%llx, size: 0x%llx\n", \ + __func__, __LINE__, type, dev_path(dev), index, base, base + size - 1, size) + +#define ADD_MMIO_RESOURCE(dev, index, base, size) \ + mmio_resource(dev, index, (uint64_t) ((uint64_t)base >> 10), (uint64_t) ((uint64_t)size >> 10)); \ + LOG_MEM_RESOURCE("mmio", dev, index, (uint64_t) ((uint64_t)base >> 10), (uint64_t) ((uint64_t)size >> 10)) + +#endif diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c new file mode 100644 index 0000000..cebf488 --- /dev/null +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/mmapvtd.c @@ -0,0 +1,349 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 - 2019 Intel Corporation. + * Copyright (C) 2019-2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <fsp/memory_init.h> +#include <fsp/util.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/skx_iomap.h> +#include <soc/skx_log_utils.h> + +#define MAP_ENTRY(reg_, is_64_, is_limit_, mask_bits_, desc_) \ + { \ + .reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_, \ + .mask_bits = mask_bits_, .description = desc_, \ + } + +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 1, 1, mask_bits_, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, 0, desc_) +#define MAP_ENTRY_LIMIT_32(reg_, mask_bits_, desc_) MAP_ENTRY(reg_, 0, 1, mask_bits_, desc_) + +struct map_entry { + int reg; + int is_64_bit; + int is_limit; + int mask_bits; + const char *description; +}; + +enum { + TOHM_REG, + MMIOL_REG, + MMCFG_BASE_REG, + MMCFG_LIMIT_REG, + TOLM_REG, + ME_BASE_REG, + ME_LIMIT_REG, + TSEG_BASE_REG, + TSEG_LIMIT_REG, + /* Must be last. */ + NUM_MAP_ENTRIES +}; + +static struct map_entry memory_map[NUM_MAP_ENTRIES] = { + [TOHM_REG] = MAP_ENTRY_LIMIT_64(SKXSP_VTD_TOHM_CSR, 26, "TOHM"), + [MMIOL_REG] = MAP_ENTRY_BASE_32(SKXSP_VTD_MMIOL_CSR, "MMIOL"), + [MMCFG_BASE_REG] = MAP_ENTRY_BASE_64(SKXSP_VTD_MMCFG_BASE_CSR, "MMCFG_BASE"), + [MMCFG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(SKXSP_VTD_MMCFG_LIMIT_CSR, 26, "MMCFG_LIMIT"), + [TOLM_REG] = MAP_ENTRY_LIMIT_32(SKXSP_VTD_TOLM_CSR, 26, "TOLM"), + [ME_BASE_REG] = MAP_ENTRY_BASE_64(SKXSP_VTD_ME_BASE_CSR, "ME_BASE"), + [ME_LIMIT_REG] = MAP_ENTRY_LIMIT_64(SKXSP_VTD_ME_LIMIT_CSR, 19, "ME_LIMIT"), + [TSEG_BASE_REG] = MAP_ENTRY_BASE_32(SKXSP_VTD_TSEG_BASE_CSR, "TSEGMB_BASE"), + [TSEG_LIMIT_REG] = MAP_ENTRY_LIMIT_32(SKXSP_VTD_TSEG_LIMIT_CSR, 20, "TSEGMB_LIMIT"), +}; + +static void read_map_entry(struct device *dev, struct map_entry *entry, + uint64_t *result) +{ + uint64_t value; + uint64_t mask; + + /* All registers are on a 1MiB granularity. */ + mask = ((1ULL << entry->mask_bits) - 1); + mask = ~mask; + + value = 0; + + if (entry->is_64_bit) { + value = pci_read_config32(dev, entry->reg + 4); + value <<= 32; + } + + value |= (uint64_t)pci_read_config32(dev, entry->reg); + value &= mask; + + if (entry->is_limit) + value |= ~mask; + + *result = value; +} + +static void mc_read_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) + read_map_entry(dev, &memory_map[i], &values[i]); +} + +static void mc_report_map_entries(struct device *dev, uint64_t *values) +{ + int i; + for (i = 0; i < NUM_MAP_ENTRIES; i++) { + printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", + memory_map[i].description, values[i]); + } +} + +/* + * Host Memory Map: + * + * +--------------------------+ TOCM (2 pow 46 - 1) + * | Reserved | + * +--------------------------+ + * | MMIOH (relocatable) | + * +--------------------------+ + * | PCISeg | + * +--------------------------+ TOHM + * | High DRAM Memory | (0x100000000 - 0x107fffffff, 0x3e00000) + * +--------------------------+ 4GiB (0x100000000) + * +--------------------------+ 0xFFFF_FFFF + * | Firmware | (0xff000000 - 0xffffffff, 0x4000) + * +--------------------------+ 0xFF00_0000 + * | Reserved | + * +--------------------------+ 0xFEF0_0000 + * | Local xAPIC | (0xfee00000 - 0xfee00fff, 0x4) ** wrong? + * | Local xAPIC | (0xfee00000 - 0xfeefffff, 0x400) + * +--------------------------+ 0xFEE0_0000 + * | HPET/LT/TPM/Others | (0xfed00000 - 0xfedfffff, 0x400) + * +--------------------------+ 0xFED0_0000 + * | I/O xAPIC | (0xfec00000 - 0xfecfffff, 0x400) + * | I/O xAPIC | (0xfec01000 - 0xfed00fff, 0x400 - wrong??) + * | I/O xAPIC | (0xfec00000 - 0xfec00fff, 0x4 - wrong??) + IOAPIC[0]: apic_id 8, version 32, address 0xfec00000, GSI 0-23 + IOAPIC[1]: apic_id 9, version 32, address 0xfec01000, GSI 24-31 + IOAPIC[2]: apic_id 10, version 32, address 0xfec08000, GSI 32-39 + IOAPIC[3]: apic_id 11, version 32, address 0xfec10000, GSI 40-47 + IOAPIC[4]: apic_id 12, version 32, address 0xfec18000, GSI 48-55 + IOAPIC[5]: apic_id 15, version 32, address 0xfec20000, GSI 72-79 + IOAPIC[6]: apic_id 16, version 32, address 0xfec28000, GSI 80-87 + IOAPIC[7]: apic_id 17, version 32, address 0xfec30000, GSI 88-95 + IOAPIC[8]: apic_id 18, version 32, address 0xfec38000, GSI 96-103 + * +--------------------------+ 0xFEC0_0000 + * | Reserved | (0xfeb80000 - 0xfebfffff, 0x200) + * +--------------------------+ 0xFEB8_0000 + * | Reserved | (0xfeb0)0000 - 0xfeb0_ffff, 0x40) ** wrong? + * +--------------------------+ 0xFEB0_0000 + * | Reserved | (0xfe000000, 0x10000, PCI: 00:1f.2,) - ?? + 00:1f.5 Intel Corporation Lewisburg SPI Controller + Memory at fe010000 (32-bit, non-prefetchable) [size=4K] + * +--------------------------+ 0xFE00_0000 + * | MMIOL (relocatable) | + * | P2SB PCR cfg BAR | (0xfd000000 - 0xfdffffff + * | BAR space | [mem 0x90000000-0xfcffffff] available for PCI devices + * +--------------------------+ 0x9000_0000 + * |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB (0x80000000 - 0x8fffffff, 0x40000) + * +--------------------------+ TOLM + * | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000) + * +--------------------------+ + * | Tseg (relocatable) | N x 8MB (0x70000000 - 0x77ffffff, 0x20000) + * +--------------------------+ + * | Reserved - CBMEM | (0x6fffe000 - 0x6fffffff, 0x2000) + * +--------------------------+ + * | Reserved - FSP | (0x6fbfe000 - 0x6fffdfff, 0x400000) + * +--------------------------+ top_of_ram (0x6fbfdfff) + * | Low DRAM Memory | (0x100000 - 0x6fbfdfff, 0x1bebf8) + * +--------------------------+ FFFFF (1MB) + * | E & F segments | + * +--------------------------+ E0000 + * | C & D segments | + * +--------------------------+ C0000 + * | VGA & SMM Memory | + * +--------------------------+ A0000 + * | Conventional Memory | + * | (DOS Range) | reserved =? nosave memory: [mem 0x00000000-0x00000fff] + * +--------------------------+ 0 + */ + +static void mc_add_dram_resources(struct device *dev, int *res_count) +{ + struct range_entry fsp_mem; + uint64_t base_kb; + uint64_t size_kb; + uint64_t top_of_ram; + uint64_t mc_values[NUM_MAP_ENTRIES]; + struct resource *resource; + int index = *res_count; + + fsp_find_reserved_memory(&fsp_mem); + + /* Read in the MAP registers and report their values. */ + mc_read_map_entries(dev, &mc_values[0]); + mc_report_map_entries(dev, &mc_values[0]); + + top_of_ram = range_entry_base(&fsp_mem) - 1; + printk(BIOS_SPEW, "cbmem_top: 0x%lx, fsp range: [0x%llx - 0x%llx], top_of_ram: 0x%llx\n", (uintptr_t) cbmem_top(), + range_entry_base(&fsp_mem), range_entry_end(&fsp_mem), top_of_ram); + + /* Conventional Memory (DOS region, 0x0 to 0x9FFFF) */ + base_kb = 0; + size_kb = (0xa0000 >> 10); + LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + + /* 1MB -> top_of_ram i.e., fsp_mem_base+1*/ + base_kb = (0x100000 >> 10); + size_kb = (top_of_ram - 0xfffff) >> 10; + LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + + /* + * Add CBMem, FSP Memory, TSEG/MESEG Regions as reserved memory + * src/drivers/intel/fsp2_0/memory_init.c sets CBMEM resered size + * arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); == 2 * CBMEM_ROOT_MIN_SIZE + * typically 0x2000 + * Example config: + * FSP_RESERVED_MEMORY_RESOURCE_HOB + * FspReservedMemoryResource Base : 6FBFE000 + * FspReservedMemoryResource Size : 400000 + * FSP_BOOT_LOADER_TOLUM_HOB + * FspBootLoaderTolum Base : 6FFFE000 + * FspBootLoaderTolum Size : 2000 + */ + + /* Mark FSP region */ + base_kb = (range_entry_base(&fsp_mem) >> 10); + size_kb = (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1) >> 10; + LOG_MEM_RESOURCE("mmio_fsp", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + + /* Mark coreboot region as reserved */ + base_kb = (range_entry_base(&fsp_mem) + (range_entry_end(&fsp_mem) - range_entry_base(&fsp_mem) + 1)) >> 10; + size_kb = (mc_values[TSEG_BASE_REG] - (base_kb << 10)) >> 10; + LOG_MEM_RESOURCE("mmio_coreboot", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + + /* Mark TSEG/SMM region */ + base_kb = (mc_values[TSEG_BASE_REG] >> 10); + size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10; + LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + + /* Mark region between TSEG - TOLM as reserved */ + if (mc_values[TSEG_LIMIT_REG] < mc_values[TOLM_REG]) { + base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10); + size_kb = (mc_values[TOLM_REG] - mc_values[TSEG_LIMIT_REG]) >> 10; + LOG_MEM_RESOURCE("mmio_tolm", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + } + + /* 4GiB -> TOHM */ + if (mc_values[TOHM_REG] > 0x100000000) { + base_kb = (0x100000000 >> 10); + size_kb = (mc_values[TOHM_REG] - 0x100000000 + 1) >> 10; + LOG_MEM_RESOURCE("high_ram", dev, index, base_kb, size_kb); + ram_resource(dev, index++, base_kb, size_kb); + } + + /* add MMIO CFG resource */ + resource = new_resource(dev, index++); + resource->base = (resource_t) mc_values[MMCFG_BASE_REG]; + resource->size = (resource_t) (mc_values[MMCFG_LIMIT_REG] - mc_values[MMCFG_BASE_REG] + 1); + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + LOG_MEM_RESOURCE("mmiocfg_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); + + /* add Local APIC resource */ + resource = new_resource(dev, index++); + resource->base = LAPIC_DEFAULT_BASE; + resource->size = 0x00001000; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + LOG_MEM_RESOURCE("apic_res", dev, index-1, (resource->base >> 10), (resource->size >> 10)); + + /* add legacy region as reserved - 0xa000 - 1MB */ + base_kb = (0xa0000 >> 10); + size_kb = (0x100000 - 0xa0000) >> 10; + LOG_MEM_RESOURCE("legacy_mmio", dev, index, base_kb, size_kb); + mmio_resource(dev, index++, base_kb, size_kb); + + /* add APEI_ERST reserved region */ + /* + Error Record Serialization Table (ERST) support is initialized + APEI firmware first mode is enabled by APEI bit and WHEA _OSC + 6a7a9000-6c8a8fff : Reserved + 6b88e018-6b88e018 : APEI ERST + 6b88e01c-6b88e021 : APEI ERST + 6b88e028-6b88e039 : APEI ERST + 6b88e040-6b88e04c : APEI ERST + */ + + resource = new_resource(dev, index++); + resource->base = APEI_ERST_BASE_ADDRESS; + resource->size = APEI_ERST_BASE_SIZE; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + LOG_MEM_RESOURCE("APEI_ERST", dev, index-1, (resource->base >> 10), (resource->size >> 10)); + + *res_count = index; +} + +static void mmapvtd_read_resources(struct device *dev) +{ + int index = 0; + + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, &index); +} + +static void mmapvtd_init(struct device *dev) +{ + printk(BIOS_DEBUG, "mmapvtd_init\n"); +} + +struct pci_operations soc_pci_ops = { + .set_subsystem = &pci_dev_set_subsystem +}; + +static struct device_operations mmapvtd_ops = { + .read_resources = mmapvtd_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = mmapvtd_init, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short mmapvtd_ids[] = { + SKXSP_MMAP_VTD_CFG_REG_DEVID, /* Memory Map/Intel® VT-d Configuration Registers */ + 0 +}; + +static const struct pci_driver mmapvtd_driver __pci_driver = { + .ops = &mmapvtd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = mmapvtd_ids +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/38985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3cb271a974f06d24ff17987595b700e7bdadc47 Gerrit-Change-Number: 38985 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: xeonsp/skylake-sp: Add FSP SiliconInit invocation
by Andrey Petrov (Code Review) 23 Mar '20

23 Mar '20

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38981 ) Change subject: xeonsp/skylake-sp: Add FSP SiliconInit invocation ...................................................................... xeonsp/skylake-sp: Add FSP SiliconInit invocation Silicon Init is called at ramstage through chip enable function. This patch adds minimal skeleton chip ops. Change-Id: I3e5eeb580207aa7c3d3ab02a3321b658e63c95d0 --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc A src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c 3 files changed, 103 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/38981/1 diff --git a/src/cpu/intel/xeonsp/Kconfig b/src/cpu/intel/xeonsp/Kconfig index 0c6c103..aa9579f 100644 --- a/src/cpu/intel/xeonsp/Kconfig +++ b/src/cpu/intel/xeonsp/Kconfig @@ -44,6 +44,10 @@ string default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/Server_M.fd" +config FSP_S_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/Server_S.fd" + config PCR_BASE_ADDRESS hex default 0xfd000000 diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc index 42fb607..50da224 100644 --- a/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/Makefile.inc @@ -13,6 +13,7 @@ ## romstage-y += romstage.c +ramstage-y += chip.c CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include CPPFLAGS_common += -I$(src)/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include diff --git a/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c new file mode 100644 index 0000000..52488d8 --- /dev/null +++ b/src/cpu/intel/xeonsp/cpu/skylake-sp/chip.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <device/device.h> +#include <fsp/api.h> +#include <lib.h> + +static void skxsp_pci_domain_read_resources(struct device *dev) +{ +} + +static void skxsp_pci_domain_set_resources(struct device *dev) +{ +} + +static void skxsp_pci_domain_scan_bus(struct device *dev) +{ +} + +static struct device_operations pci_domain_ops = { + .read_resources = &skxsp_pci_domain_read_resources, + .set_resources = &skxsp_pci_domain_set_resources, + .scan_bus = &skxsp_pci_domain_scan_bus, +}; + +static void init_cpus(struct device *dev) +{ + /* not implemented yet */ +} + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = init_cpus, + .scan_bus = NULL, +}; + +static void chip_init(void *data) +{ + printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); + fsp_silicon_init(false); +} + +static void chip_final(void *data) +{ + /* nothing implemented yet */ +} + +static void chip_enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations cpu_intel_xeonsp_cpu_skylake_sp_ops = { + CHIP_NAME("Intel Skylake-SP") + .enable_dev = chip_enable_dev, + .init = chip_init, + .final = chip_final +}; + +void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) +{ + const struct microcode *microcode_file; + size_t microcode_len; + + /* Let FSP-S load ucode */ + microcode_file = cbfs_boot_map_with_leak("cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, &microcode_len); + + if ((microcode_file != NULL) && (microcode_len != 0)) { + /* Update CPU Microcode patch base address/size */ + silupd->FspsConfig.PcdCpuMicrocodePatchBase = + (uint32_t)microcode_file; + silupd->FspsConfig.PcdCpuMicrocodePatchSize = + (uint32_t)microcode_len; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e5eeb580207aa7c3d3ab02a3321b658e63c95d0 Gerrit-Change-Number: 38981 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: cpi/xeonsp: Cache SPI region
by Andrey Petrov (Code Review) 23 Mar '20

23 Mar '20

Andrey Petrov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39050 ) Change subject: cpi/xeonsp: Cache SPI region ...................................................................... cpi/xeonsp: Cache SPI region Instead of trying to hardcode caching parameters for FSP-T, use common code to cache BIOS region. This seems to be an undocumented requirement for FSP-M to function correctly. Change-Id: I926722ecd7237bea236a4906b899a51e4963f740 Signed-off-by: Andrey Petrov <anpetrov(a)fb.com> --- M src/cpu/intel/xeonsp/Kconfig M src/cpu/intel/xeonsp/Makefile.inc M src/cpu/intel/xeonsp/bootblock.c A src/cpu/intel/xeonsp/spi.c 4 files changed, 17 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/39050/1 diff --git a/src/cpu/intel/xeonsp/Kconfig b/src/cpu/intel/xeonsp/Kconfig index 1a7d8bc..3fa1d5a 100644 --- a/src/cpu/intel/xeonsp/Kconfig +++ b/src/cpu/intel/xeonsp/Kconfig @@ -29,6 +29,8 @@ select DISPLAY_MTRRS select FSP_M_XIP select INTEL_DESCRIPTOR_MODE_CAPABLE + select SPI_FLASH + select SOC_INTEL_COMMON_BLOCK_FAST_SPI if CPU_INTEL_MODEL_XEONSP config MMCONF_BASE_ADDRESS diff --git a/src/cpu/intel/xeonsp/Makefile.inc b/src/cpu/intel/xeonsp/Makefile.inc index af1bb72..8e20a14 100644 --- a/src/cpu/intel/xeonsp/Makefile.inc +++ b/src/cpu/intel/xeonsp/Makefile.inc @@ -18,9 +18,9 @@ subdirs-y += ../../x86/cache subdirs-y += ../../x86/smm -bootblock-y += bootblock.c -romstage-y += ../../../cpu/intel/car/romstage.c -romstage-y += postcar.c romstage.c -ramstage-y += model_xeonsp_init.c lpc.c ramstage.c +bootblock-y += bootblock.c spi.c +romstage-y += ../../../cpu/intel/car/romstage.c spi.c +romstage-y += postcar.c romstage.c spi.c +ramstage-y += model_xeonsp_init.c lpc.c ramstage.c spi.c CPPFLAGS_common += -I$(src)/cpu/intel/xeonsp/include diff --git a/src/cpu/intel/xeonsp/bootblock.c b/src/cpu/intel/xeonsp/bootblock.c index f3ffe66..6c3a367 100644 --- a/src/cpu/intel/xeonsp/bootblock.c +++ b/src/cpu/intel/xeonsp/bootblock.c @@ -18,6 +18,7 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <FsptUpd.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelblocks/uart.h> #include <soc/pci_devs.h> @@ -44,6 +45,8 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + fast_spi_cache_bios_region(); + /* set up P2SB BAR */ uint8_t p2sb_cmd = pci_mmio_read_config8(PCH_DEV_P2SB, PCI_COMMAND); pci_mmio_write_config8(PCH_DEV_P2SB, PCI_COMMAND, p2sb_cmd|PCI_COMMAND_MEMORY); diff --git a/src/cpu/intel/xeonsp/spi.c b/src/cpu/intel/xeonsp/spi.c new file mode 100644 index 0000000..5bc4da5 --- /dev/null +++ b/src/cpu/intel/xeonsp/spi.c @@ -0,0 +1,8 @@ +#include <spi-generic.h> +#include <intelblocks/fast_spi.h> + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 } + }; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/39050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926722ecd7237bea236a4906b899a51e4963f740 Gerrit-Change-Number: 39050 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: src/soc/intel/common/block/acpi: Change Processor ACPI Name
by Christian Walter (Code Review) 23 Mar '20

23 Mar '20

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37814 ) Change subject: src/soc/intel/common/block/acpi: Change Processor ACPI Name ...................................................................... src/soc/intel/common/block/acpi: Change Processor ACPI Name The ACPI Spec 6.2 states, that Processor declarations should be made within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated and has been removed here. Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Signed-off-by: Christian Walter <christian.walter(a)9elements.com> --- M src/arch/x86/Kconfig M src/soc/intel/common/block/acpi/acpi.c 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/37814/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index e27aec2..e863075 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -283,7 +283,7 @@ config ACPI_CPU_STRING string - default "\\_PR.CP%02d" + default "CP%02d" depends on HAVE_ACPI_TABLES help Sets the ACPI name string in the processor scope as written by diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index 3a34c79..8488e7e 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -427,6 +427,8 @@ printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package); + // Write Scope + acpigen_write_scope("\\_SB"); for (cpu_id = 0; cpu_id < numcpus; cpu_id++) { for (core_id = 0; core_id < cores_per_package; core_id++) { if (core_id > 0) { @@ -453,6 +455,8 @@ /* Add a method to notify processor nodes */ acpigen_write_processor_cnot(cores_per_package); + + acpigen_pop_len(); } #if CONFIG(SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) -- To view, visit https://review.coreboot.org/c/coreboot/+/37814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438 Gerrit-Change-Number: 37814 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

10 57

Change in coreboot[master]: nb/amd/{agesa,pi}/acpi: include thermal zone
by Michał Żygowski (Code Review) 23 Mar '20

23 Mar '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38755 ) Change subject: nb/amd/{agesa,pi}/acpi: include thermal zone ...................................................................... nb/amd/{agesa,pi}/acpi: include thermal zone According to BKDGs these northbridges should support the K10 compatible temperature sensors. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Icbdf44508085964452d74e084b133f1baa39e1a8 --- M src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl M src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl M src/northbridge/amd/pi/00630F01/acpi/northbridge.asl M src/northbridge/amd/pi/00730F01/acpi/northbridge.asl 4 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/38755/1 diff --git a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl index c360da6..aabfed3 100644 --- a/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family15tn/acpi/northbridge.asl @@ -93,3 +93,8 @@ Return (PS7) /* PIC Mode */ } /* end _PRT */ } /* end PBR7 */ + +Device (K10M) { + Name (_ADR, 0x00180003) + #include <northbridge/amd/agesa/family14/acpi/thermal_mixin.asl> +} diff --git a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl index ce889c7..6e8f5b6 100644 --- a/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl +++ b/src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl @@ -93,3 +93,8 @@ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ + +Device (K10M) { + Name (_ADR, 0x00180003) + #include <northbridge/amd/agesa/family14/acpi/thermal_mixin.asl> +} diff --git a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl index ffe1367..975260a 100644 --- a/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00630F01/acpi/northbridge.asl @@ -63,3 +63,8 @@ Return (PS3) /* PIC Mode */ } /* end _PRT */ } /* end PBR3 */ + +Device (K10M) { + Name (_ADR, 0x00180003) + #include <northbridge/amd/agesa/family14/acpi/thermal_mixin.asl> +} diff --git a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl index ce889c7..6e8f5b6 100644 --- a/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00730F01/acpi/northbridge.asl @@ -93,3 +93,8 @@ Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ + +Device (K10M) { + Name (_ADR, 0x00180003) + #include <northbridge/amd/agesa/family14/acpi/thermal_mixin.asl> +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbdf44508085964452d74e084b133f1baa39e1a8 Gerrit-Change-Number: 38755 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entries
by Michał Żygowski (Code Review) 23 Mar '20

23 Mar '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38343 ) Change subject: mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entries ...................................................................... mb/pcengines/apu1/mainboard.c: Add SMBIOS type 16 and 17 entries Use information provided by AGESA to fill the SMBIOS memory tables. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63 --- M src/mainboard/pcengines/apu1/mainboard.c 1 file changed, 98 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38343/1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 854fb8a..d817d57 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <AGESA.h> +#include <AMD.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -24,6 +26,7 @@ #include <string.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include <southbridge/amd/cimx/sb800/pci_devs.h> +#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/family14/pci_devs.h> #include <superio/nuvoton/nct5104d/nct5104d.h> #include "gpio_ftns.h" @@ -174,6 +177,98 @@ /********************************************** * Enable the dedicated functions of the board. **********************************************/ +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, + unsigned long *current) +{ + struct smbios_type16 *t; + u32 max_capacity; + int len = 0; + + t = (struct smbios_type16 *)*current; + len = sizeof(struct smbios_type16); + memset(t, 0, sizeof(struct smbios_type16)); + max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */ + + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = *handle; + t->length = len - 2; + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->use = MEMORY_ARRAY_USE_SYSTEM; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->memory_error_correction = agesa_dmi->T16.MemoryErrorCorrection; + t->maximum_capacity = max_capacity * 1024 * 1024; + t->memory_error_information_handle = 0xfffe; + t->number_of_memory_devices = 1; + + *current += len; + + return len; +} + +static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, + unsigned long *current) +{ + struct smbios_type17 *t; + int len = 0; + + t = (struct smbios_type17 *)*current; + memset(t, 0, sizeof(struct smbios_type17)); + + t->type = SMBIOS_MEMORY_DEVICE; + t->length = sizeof(struct smbios_type17) - 2; + t->handle = *handle + 1; + t->phys_memory_array_handle = *handle; + t->memory_error_information_handle = 0xfffe; + t->total_width = agesa_dmi->T17[0][0][0].TotalWidth; + t->data_width = agesa_dmi->T17[0][0][0].DataWidth; + t->size = agesa_dmi->T17[0][0][0].MemorySize; + t->form_factor = agesa_dmi->T17[0][0][0].FormFactor; + t->device_set = agesa_dmi->T17[0][0][0].DeviceSet; + t->device_locator = smbios_add_string(t->eos, + agesa_dmi->T17[0][0][0].DeviceLocator); + t->bank_locator = smbios_add_string(t->eos, + agesa_dmi->T17[0][0][0].BankLocator); + t->memory_type = agesa_dmi->T17[0][0][0].MemoryType; + t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail; + t->speed = agesa_dmi->T17[0][0][0].Speed; + t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode; + t->serial_number = smbios_add_string(t->eos, + agesa_dmi->T17[0][0][0].SerialNumber); + t->part_number = smbios_add_string(t->eos, + agesa_dmi->T17[0][0][0].PartNumber); + t->attributes = agesa_dmi->T17[0][0][0].Attributes; + t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; + t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed; + t->minimum_voltage = 1500; /* From SPD: 1.5V */ + t->maximum_voltage = 1500; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + + return len; +} + +static int mainboard_smbios_data(struct device *dev, int *handle, + unsigned long *current) +{ + DMI_INFO *agesa_dmi; + int len = 0; + + agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return len; + + len += mainboard_smbios_type16(agesa_dmi, handle, current); + len += mainboard_smbios_type17(agesa_dmi, handle, current); + + *handle += 2; + + return len; +} +#endif + static void mainboard_enable(struct device *dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); @@ -195,6 +290,9 @@ /* Initialize the PIRQ data structures for consumption */ pirq_setup(); +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = mainboard_smbios_data; +#endif } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/38343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id73de7c2b23c6eb71722f1c78dbf0d246f429c63 Gerrit-Change-Number: 38343 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: src: capitalize 'APIC'
by HAOUAS Elyes (Code Review) 23 Mar '20

23 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39030 ) Change subject: src: capitalize 'APIC' ...................................................................... src: capitalize 'APIC' Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/cpu.c M src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/intel/baytrail/include/soc/gpio.h M src/soc/intel/broadwell/smi.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/smi.c M src/southbridge/intel/i82870/82870.h M src/southbridge/intel/i82870/ioapic.c M src/southbridge/intel/lynxpoint/smi.c 14 files changed, 22 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/39030/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 30d2cca..0bfe4c1 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -221,7 +221,7 @@ cpu->ops = driver ? driver->ops : NULL; } -/* Keep track of default apic ids for SMM. */ +/* Keep track of default APIC ids for SMM. */ static int cpus_default_apic_id[CONFIG_MAX_CPUS]; /* diff --git a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl index 3530801..9411b5f 100644 --- a/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl +++ b/src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl @@ -22,11 +22,11 @@ /* Methods called by run-time generated SSDT Processor objects */ Method(CPMA, 1, NotSerialized) { - // _MAT method - create an madt apic buffer + // _MAT method - create an madt APIC buffer // Arg0 = Processor ID = Local APIC ID // Local0 = CPON flag for this cpu Store(DerefOf(Index(CPON, Arg0)), Local0) - // Local1 = Buffer (in madt apic form) to return + // Local1 = Buffer (in madt APIC form) to return Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1) // Update the processor id, lapic id, and enable/disable status Store(Arg0, Index(Local1, 2)) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 074b4b9..27e6daf 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -861,7 +861,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 794428b..1463e5f 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -887,7 +887,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 2295cd6..7c9cde2 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -865,7 +865,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 3e04ec3..f6affcc 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -872,7 +872,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index cf4d78b..2442e36 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -1133,7 +1133,7 @@ * in LocalApicInitializationAtEarly() function. * And reference GetLocalApicIdForCore() * - * Apply apic enumeration rules + * Apply APIC enumeration rules * For systems with >= 16 APICs, put the IO-APICs at 0..n and * put the local-APICs at m..z * diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 2fed005..1161325 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -197,49 +197,49 @@ .io_sel = GPIO_DIR_INPUT, \ .is_gpio = 1 } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELHIGH_NO_PULL \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_LEVELLOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEHIGH_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGELOW_PD_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - pass signal directly to apic */ +/* Direct / dedicated IRQ input - pass signal directly to APIC */ #define GPIO_DIRQ_EDGEBOTH_PU_20K \ { .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \ diff --git a/src/soc/intel/broadwell/smi.c b/src/soc/intel/broadwell/smi.c index 2bdeecc..2beab65 100644 --- a/src/soc/intel/broadwell/smi.c +++ b/src/soc/intel/broadwell/smi.c @@ -73,7 +73,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index dc53220..e85241c 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -306,7 +306,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 5f73f41..2509e0a 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -112,7 +112,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index 1fe40b6..ce76db0 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -/* for io apic 1461 */ +/* for io APIC 1461 */ #define MBAR 0x10 #define ABAR 0x40 diff --git a/src/southbridge/intel/i82870/ioapic.c b/src/southbridge/intel/i82870/ioapic.c index 4fbf329..1f4aa501a 100644 --- a/src/southbridge/intel/i82870/ioapic.c +++ b/src/southbridge/intel/i82870/ioapic.c @@ -43,8 +43,8 @@ uint32_t memoryBase; int apic_index, apic_id; - volatile uint32_t *pIndexRegister; /* io apic io memory space command address */ - volatile uint32_t *pWindowRegister; /* io apic io memory space data address */ + volatile uint32_t *pIndexRegister; /* io APIC io memory space command address */ + volatile uint32_t *pWindowRegister; /* io APIC io memory space data address */ apic_index = num_p64h2_ioapics; num_p64h2_ioapics++; diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index e5c390e..8b6e4e4 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -77,7 +77,7 @@ * - Writes to io 0xb2 (APMC) * - Writes to the Local Apic ICR with Delivery mode SMI. * - * Using the local apic is a bit more tricky. According to + * Using the local APIC is a bit more tricky. According to * AMD Family 11 Processor BKDG no destination shorthand must be * used. * The whole SMM initialization is quite a bit hardware specific, so -- To view, visit https://review.coreboot.org/c/coreboot/+/39030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Gerrit-Change-Number: 39030 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/51nb/x210: merge macOS changes
by Matt DeVillier (Code Review) 21 Mar '20

21 Mar '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39107 ) Change subject: mb/51nb/x210: merge macOS changes ...................................................................... mb/51nb/x210: merge macOS changes merge in macOS-specific changes from https://github.com/harrykipper/coreboot at commit 709cf02. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ie11e13c9db68c2a90822eef845b2ccab19f7bd18 --- M src/mainboard/51nb/x210/acpi/ec.asl M src/mainboard/51nb/x210/acpi/graphics.asl A src/mainboard/51nb/x210/acpi/mac-usb.asl M src/mainboard/51nb/x210/dsdt.asl M src/mainboard/51nb/x210/mainboard.c 5 files changed, 1,110 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/39107/1 diff --git a/src/mainboard/51nb/x210/acpi/ec.asl b/src/mainboard/51nb/x210/acpi/ec.asl index bff02fe..9f834ca 100644 --- a/src/mainboard/51nb/x210/acpi/ec.asl +++ b/src/mainboard/51nb/x210/acpi/ec.asl @@ -67,13 +67,13 @@ /* KEY_BRIGHTNESSUP */ Method (_Q04) { - Notify(\_SB.PCI0.GFX0.LCD, 0x86) + Notify(\_SB.PCI0.IGPU.LCD, 0x86) } /* KEY_BRIGHTNESSDOWN */ Method (_Q05) { - Notify(\_SB.PCI0.GFX0.LCD, 0x87) + Notify(\_SB.PCI0.IGPU.LCD, 0x87) } /* Battery Information Event */ diff --git a/src/mainboard/51nb/x210/acpi/graphics.asl b/src/mainboard/51nb/x210/acpi/graphics.asl index 7ac4794..0a4b67c 100644 --- a/src/mainboard/51nb/x210/acpi/graphics.asl +++ b/src/mainboard/51nb/x210/acpi/graphics.asl @@ -13,9 +13,68 @@ * GNU General Public License for more details. */ -Device (GFX0) +Device (IGPU) { Name (_ADR, 0x00020000) + Method (DTGP, 5, NotSerialized) + { + If (LEqual (Arg0, Buffer (0x10) + { + /* 0000 */ 0xC6, 0xB7, 0xB5, 0xA0, 0x18, 0x13, 0x1C, 0x44, + /* 0008 */ 0xB0, 0xC9, 0xFE, 0x69, 0x5E, 0xAF, 0x94, 0x9B + })) + { + If (LEqual (Arg1, One)) + { + If (LEqual (Arg2, Zero)) + { + Store (Buffer (One) + { + 0x03 + }, Arg4) + + Return (One) + } + + If (LEqual (Arg2, One)) + { + Return (One) + } + } + } + + Store (Buffer (One) + { + 0x00 + }, Arg4) + + Return (Zero) + } + + Method (_DSM, 4, NotSerialized) + { + Store (Package (0x04) + { + "device-id", + Buffer (0x04) + { + 0x16, 0x59, 0x00, 0x00 + + }, +/* "AAPL,ig-platform-id", + Buffer (0x04) + { + 0x00, 0x00, 0x16, 0x19 + }, */ + "hda-gfx", + Buffer (0x0a) + { + "onboard-1" + } + }, Local0) + DTGP (Arg0, Arg1, Arg2, Arg3, RefOf (Local0)) + Return (Local0) + } Method (_DOS, 1, NotSerialized) { /* We never do anything in firmware, so _DOS is a noop */ diff --git a/src/mainboard/51nb/x210/acpi/mac-usb.asl b/src/mainboard/51nb/x210/acpi/mac-usb.asl new file mode 100644 index 0000000..4fd1ebe --- /dev/null +++ b/src/mainboard/51nb/x210/acpi/mac-usb.asl @@ -0,0 +1,1020 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + Device(UIAC) + { + Name(_HID, "UIA00000") + + Name(RMCF, Package() + { + "HUB1", Package() + { + "port-count", Buffer() { 8, 0, 0, 0 }, + "ports", Package() + { + "HP11", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HP12", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HP13", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HP14", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HP15", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HP16", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HP17", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HP18", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 8, 0, 0, 0 }, + }, + }, + }, + "HUB2", Package() + { + "port-count", Buffer() { 6, 0, 0, 0 }, + "ports", Package() + { + "HP21", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HP22", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HP23", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HP24", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HP25", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HP26", Package() + { + //"UsbConnector", 0, + "portType", 0, + "port", Buffer() { 6, 0, 0, 0 }, + }, + }, + }, + "EH01", Package() + { + "port-count", Buffer() { 8, 0, 0, 0 }, + "ports", Package() + { + "PR11", Package() + { + "UsbConnector", 255, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "PR12", Package() + { + "UsbConnector", 0, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "PR13", Package() + { + "UsbConnector", 0, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "PR14", Package() + { + "UsbConnector", 0, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "PR15", Package() + { + "UsbConnector", 0, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "PR16", Package() + { + "UsbConnector", 0, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "PR17", Package() + { + "UsbConnector", 0, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "PR18", Package() + { + "UsbConnector", 0, + "port", Buffer() { 8, 0, 0, 0 }, + }, + }, + }, + "EH02", Package() + { + "port-count", Buffer() { 6, 0, 0, 0 }, + "ports", Package() + { + "PR21", Package() + { + "UsbConnector", 255, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "PR22", Package() + { + "UsbConnector", 0, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "PR23", Package() + { + "UsbConnector", 0, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "PR24", Package() + { + "UsbConnector", 0, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "PR25", Package() + { + "UsbConnector", 0, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "PR26", Package() + { + "UsbConnector", 0, + "port", Buffer() { 6, 0, 0, 0 }, + }, + }, + }, + "8086_1e31", Package() + { + "port-count", Buffer() { 8, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + }, + }, + "8086_8xxx", Package() + { + "port-count", Buffer() { 21, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + "HS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 9, 0, 0, 0 }, + }, + "HS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 10, 0, 0, 0 }, + }, + "HS11", Package() + { + "UsbConnector", 3, + "port", Buffer() { 11, 0, 0, 0 }, + }, + "HS12", Package() + { + "UsbConnector", 3, + "port", Buffer() { 12, 0, 0, 0 }, + }, + "HS13", Package() + { + "UsbConnector", 3, + "port", Buffer() { 13, 0, 0, 0 }, + }, + "HS14", Package() + { + "UsbConnector", 3, + "port", Buffer() { 14, 0, 0, 0 }, + }, + //HS15 is phantom port (port address 15 not used) + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 16, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 17, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 18, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 19, 0, 0, 0 }, + }, + "SS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 20, 0, 0, 0 }, + }, + "SS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 21, 0, 0, 0 }, + }, + }, + }, + "8086_9xxx", Package() + { + "port-count", Buffer() { 13, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + "HS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 9, 0, 0, 0 }, + }, + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 10, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 11, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 12, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 13, 0, 0, 0 }, + }, + }, + }, + "8086_9cb1", Package() + { + "port-count", Buffer() { 15, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + "HS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 9, 0, 0, 0 }, + }, + "HS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 10, 0, 0, 0 }, + }, + "HS11", Package() + { + "UsbConnector", 3, + "port", Buffer() { 11, 0, 0, 0 }, + }, + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 12, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 13, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 14, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 15, 0, 0, 0 }, + }, + }, + }, + "8086_a12f", Package() + { + "port-count", Buffer() { 26, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + "HS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 9, 0, 0, 0 }, + }, + "HS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 10, 0, 0, 0 }, + }, + "HS11", Package() + { + "UsbConnector", 3, + "port", Buffer() { 11, 0, 0, 0 }, + }, + "HS12", Package() + { + "UsbConnector", 3, + "port", Buffer() { 12, 0, 0, 0 }, + }, + "HS13", Package() + { + "UsbConnector", 3, + "port", Buffer() { 13, 0, 0, 0 }, + }, + "HS14", Package() + { + "UsbConnector", 3, + "port", Buffer() { 14, 0, 0, 0 }, + }, + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 17, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 18, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 19, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 20, 0, 0, 0 }, + }, + "SS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 21, 0, 0, 0 }, + }, + "SS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 22, 0, 0, 0 }, + }, + "SS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 23, 0, 0, 0 }, + }, + "SS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 24, 0, 0, 0 }, + }, + "SS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 25, 0, 0, 0 }, + }, + "SS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 26, 0, 0, 0 }, + }, + "USR1", Package() + { + "UsbConnector", 3, + "port", Buffer() { 15, 0, 0, 0 }, + }, + "USR2", Package() + { + "UsbConnector", 3, + "port", Buffer() { 16, 0, 0, 0 }, + }, + }, + }, + "8086_9dxx", Package() // examples: 0x9d2f, 0x9ded + { + "port-count", Buffer() { 18, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + "HS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 9, 0, 0, 0 }, + }, + "HS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 10, 0, 0, 0 }, + }, + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 13, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 14, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 15, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 16, 0, 0, 0 }, + }, + "SS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 17, 0, 0, 0 }, + }, + "SS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 18, 0, 0, 0 }, + }, + "USR1", Package() + { + "UsbConnector", 3, + "port", Buffer() { 11, 0, 0, 0 }, + }, + "USR2", Package() + { + "UsbConnector", 3, + "port", Buffer() { 12, 0, 0, 0 }, + }, + }, + }, + "8086_a2af", Package() + { + "port-count", Buffer() { 26, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + "HS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 9, 0, 0, 0 }, + }, + "HS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 10, 0, 0, 0 }, + }, + "HS11", Package() + { + "UsbConnector", 3, + "port", Buffer() { 11, 0, 0, 0 }, + }, + "HS12", Package() + { + "UsbConnector", 3, + "port", Buffer() { 12, 0, 0, 0 }, + }, + "HS13", Package() + { + "UsbConnector", 3, + "port", Buffer() { 13, 0, 0, 0 }, + }, + "HS14", Package() + { + "UsbConnector", 3, + "port", Buffer() { 14, 0, 0, 0 }, + }, + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 17, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 18, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 19, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 20, 0, 0, 0 }, + }, + "SS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 21, 0, 0, 0 }, + }, + "SS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 22, 0, 0, 0 }, + }, + "SS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 23, 0, 0, 0 }, + }, + "SS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 24, 0, 0, 0 }, + }, + "SS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 25, 0, 0, 0 }, + }, + "SS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 26, 0, 0, 0 }, + }, + "USR1", Package() + { + "UsbConnector", 3, + "port", Buffer() { 15, 0, 0, 0 }, + }, + "USR2", Package() + { + "UsbConnector", 3, + "port", Buffer() { 16, 0, 0, 0 }, + }, + }, + }, + "8086_a36d", Package() + { + "port-count", Buffer() { 26, 0, 0, 0 }, + "ports", Package() + { + "HS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 1, 0, 0, 0 }, + }, + "HS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 2, 0, 0, 0 }, + }, + "HS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 3, 0, 0, 0 }, + }, + "HS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 4, 0, 0, 0 }, + }, + "HS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 5, 0, 0, 0 }, + }, + "HS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 6, 0, 0, 0 }, + }, + "HS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 7, 0, 0, 0 }, + }, + "HS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 8, 0, 0, 0 }, + }, + "HS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 9, 0, 0, 0 }, + }, + "HS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 10, 0, 0, 0 }, + }, + "HS11", Package() + { + "UsbConnector", 3, + "port", Buffer() { 11, 0, 0, 0 }, + }, + "HS12", Package() + { + "UsbConnector", 3, + "port", Buffer() { 12, 0, 0, 0 }, + }, + "HS13", Package() + { + "UsbConnector", 3, + "port", Buffer() { 13, 0, 0, 0 }, + }, + "HS14", Package() + { + "UsbConnector", 3, + "port", Buffer() { 14, 0, 0, 0 }, + }, + "SS01", Package() + { + "UsbConnector", 3, + "port", Buffer() { 17, 0, 0, 0 }, + }, + "SS02", Package() + { + "UsbConnector", 3, + "port", Buffer() { 18, 0, 0, 0 }, + }, + "SS03", Package() + { + "UsbConnector", 3, + "port", Buffer() { 19, 0, 0, 0 }, + }, + "SS04", Package() + { + "UsbConnector", 3, + "port", Buffer() { 20, 0, 0, 0 }, + }, + "SS05", Package() + { + "UsbConnector", 3, + "port", Buffer() { 21, 0, 0, 0 }, + }, + "SS06", Package() + { + "UsbConnector", 3, + "port", Buffer() { 22, 0, 0, 0 }, + }, + "SS07", Package() + { + "UsbConnector", 3, + "port", Buffer() { 23, 0, 0, 0 }, + }, + "SS08", Package() + { + "UsbConnector", 3, + "port", Buffer() { 24, 0, 0, 0 }, + }, + "SS09", Package() + { + "UsbConnector", 3, + "port", Buffer() { 25, 0, 0, 0 }, + }, + "SS10", Package() + { + "UsbConnector", 3, + "port", Buffer() { 26, 0, 0, 0 }, + }, + "USR1", Package() + { + "UsbConnector", 3, + "port", Buffer() { 15, 0, 0, 0 }, + }, + "USR2", Package() + { + "UsbConnector", 3, + "port", Buffer() { 16, 0, 0, 0 }, + }, + }, + }, + }) + } diff --git a/src/mainboard/51nb/x210/dsdt.asl b/src/mainboard/51nb/x210/dsdt.asl index dac04f2..d4fd025 100644 --- a/src/mainboard/51nb/x210/dsdt.asl +++ b/src/mainboard/51nb/x210/dsdt.asl @@ -39,6 +39,12 @@ #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> #include "acpi/graphics.asl" + #include "acpi/mac-usb.asl" + + Device (IMEI) + { + Name (_ADR, 0x00160000) + } } } diff --git a/src/mainboard/51nb/x210/mainboard.c b/src/mainboard/51nb/x210/mainboard.c index 7d8cb3e..449a7bf 100644 --- a/src/mainboard/51nb/x210/mainboard.c +++ b/src/mainboard/51nb/x210/mainboard.c @@ -14,6 +14,8 @@ */ #include <soc/ramstage.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> #include "gpio.h" void mainboard_silicon_init_params(FSP_SIL_UPD *params) @@ -27,6 +29,26 @@ { /* Route 0x4e/4f to LPC */ lpc_enable_fixed_io_ranges(LPC_IOE_EC_4E_4F); + + /* Enable Apple SMC emulation */ + + pcr_write32(PID_PSTH, 0x1e90, 0x001c0301); // Decode 0x300-0x31f + pcr_write32(PID_PSTH, 0x1e94, 0x000200f0); // R/W access, any width + + /* + * New Intel platforms have two documented sets of I/O trap registers, + * one in PSTH space, one in DMI space. The former is where the status + * registers are, so naively you'd think they'd be the ones that + * matter - but in reality, nothing works unless you enable the ones + * in DMI space around the other LPC decode registers. + */ + + /* + * TODO: are these sufficient, or do the PSTH registers need to be + * set as well? + */ + pcr_write32(PID_DMI, 0x2760, 0x001c0301); + pcr_write32(PID_DMI, 0x2764, 0x000200f0); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/39107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie11e13c9db68c2a90822eef845b2ccab19f7bd18 Gerrit-Change-Number: 39107 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: sb/ibexpeak: Use macros instead of hard-coded IDs
by Felix Singer (Code Review) 21 Mar '20

21 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37116 ) Change subject: sb/ibexpeak: Use macros instead of hard-coded IDs ...................................................................... sb/ibexpeak: Use macros instead of hard-coded IDs This patch replaces hard-coded PCI IDs with macros from pci_ids.h and adds the related IDs to it. The resulting binary doesn't differ from the one without this patch. Used documents: - Intel 322170 Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Signed-off-by: Felix Singer <felix.singer(a)9elements.com> --- M src/include/device/pci_ids.h M src/southbridge/intel/ibexpeak/azalia.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/ibexpeak/usb_ehci.c 8 files changed, 50 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/37116/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 18d6f60..d1d26fe 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2675,6 +2675,19 @@ #define PCI_DEVICE_ID_INTEL_PCIE_PB 0x3597 #define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599 +/* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */ +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_QM57 0x3b07 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_HM55 0x3b09 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1 0x3b28 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI 0x3b29 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2 0x3b2e +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_1 0x3b34 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_2 0x3b3c +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_SMBUS 0x3b30 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_AUDIO 0x3b56 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_HECI1 0x3b64 +#define PCI_DEVICE_ID_INTEL_IBEXPEAK_THERMAL 0x3b32 + /* Intel LPC device ids */ #define PCI_DEVICE_ID_INTEL_LPT_MOBILE_SAMPLE 0x8c41 #define PCI_DEVICE_ID_INTEL_LPT_DESKTOP_SAMPLE 0x8c42 diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 5b38ea7..c36ef5e 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -326,7 +326,12 @@ .ops_pci = &azalia_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0x3b56, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c20, + 0x1e20, + PCI_DEVICE_ID_INTEL_IBEXPEAK_AUDIO, + 0 +}; static const struct pci_driver pch_azalia __pci_driver = { .ops = &azalia_ops, diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..c6a73b2 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -779,7 +779,11 @@ }; -static const unsigned short pci_device_ids[] = { 0x3b07, 0x3b09, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_QM57, + PCI_DEVICE_ID_INTEL_IBEXPEAK_LPC_HM55, + 0 +}; static const struct pci_driver pch_lpc __pci_driver = { .ops = &device_ops, diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 63dff6a..e9dc908 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -615,8 +615,11 @@ .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c3a, 0x3b64, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c3a, + PCI_DEVICE_ID_INTEL_IBEXPEAK_HECI1, + 0 +}; static const struct pci_driver intel_me __pci_driver = { diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 2d9412a..4c00e8e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -247,7 +247,12 @@ .ops_pci = &sata_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b28, 0x3b29, 0x3b2e, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_1, + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_AHCI, + PCI_DEVICE_ID_INTEL_IBEXPEAK_MOBILE_SATA_IDE_2, + 0 +}; static const struct pci_driver pch_sata __pci_driver = { .ops = &sata_ops, diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index dd3abfe..589b349 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -98,7 +98,12 @@ .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x3b30, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c22, + 0x1e22, + PCI_DEVICE_ID_INTEL_IBEXPEAK_SMBUS, + 0 +}; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 597d388..540eb6f 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -57,7 +57,10 @@ .ops_pci = &pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x3b32, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_THERMAL, + 0 +}; static const struct pci_driver pch_thermal __pci_driver = { .ops = &thermal_ops, diff --git a/src/southbridge/intel/ibexpeak/usb_ehci.c b/src/southbridge/intel/ibexpeak/usb_ehci.c index d31fd70..9e8d19c 100644 --- a/src/southbridge/intel/ibexpeak/usb_ehci.c +++ b/src/southbridge/intel/ibexpeak/usb_ehci.c @@ -98,7 +98,11 @@ .ops_pci = &lops_pci, }; -static const unsigned short pci_device_ids[] = { 0x3b34, 0x3b3c, 0 }; +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_1, + PCI_DEVICE_ID_INTEL_IBEXPEAK_EHCI_2, + 0 +}; static const struct pci_driver pch_usb_ehci __pci_driver = { .ops = &usb_ehci_ops, -- To view, visit https://review.coreboot.org/c/coreboot/+/37116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3326f142d483f5008fb2ac878f30c1a3a72f500f Gerrit-Change-Number: 37116 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/lenovo/h8: Add a config to indicate whether dock init is needed
by Bill XIE (Code Review) 20 Mar '20

20 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36385 ) Change subject: ec/lenovo/h8: Add a config to indicate whether dock init is needed ...................................................................... ec/lenovo/h8: Add a config to indicate whether dock init is needed Discussed in CB:36093, in the past many lenovo boards need to declare empty h8_mainboard_init_dock() to satisfy h8.c. Since H8_DOCK_EARLY_INIT has a different meaning, it had better add another config to indicate whether dock init is needed, thus eliminating the necessity to declare empty h8_mainboard_init_dock() in the future. Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/ec/lenovo/h8/Kconfig M src/ec/lenovo/h8/h8.c M src/mainboard/lenovo/l520/mainboard.c M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t420/mainboard.c M src/mainboard/lenovo/t420s/mainboard.c M src/mainboard/lenovo/t430/mainboard.c M src/mainboard/lenovo/t430s/mainboard.c M src/mainboard/lenovo/t520/mainboard.c M src/mainboard/lenovo/t530/mainboard.c M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/x131e/mainboard.c M src/mainboard/lenovo/x1_carbon_gen1/mainboard.c M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x200/Makefile.inc D src/mainboard/lenovo/x200/variants/x301/dock.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x220/mainboard.c M src/mainboard/lenovo/x230/mainboard.c M src/mainboard/lenovo/x60/Kconfig 21 files changed, 16 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/36385/1 diff --git a/src/ec/lenovo/h8/Kconfig b/src/ec/lenovo/h8/Kconfig index f3df56a..5cc26d6 100644 --- a/src/ec/lenovo/h8/Kconfig +++ b/src/ec/lenovo/h8/Kconfig @@ -44,7 +44,14 @@ bool default n -endif +config H8_NEED_DOCK_INIT + bool "Dock init during boot is necessary" + +if H8_NEED_DOCK_INIT config H8_DOCK_EARLY_INIT bool + +endif # H8_NEED_DOCK_INIT + +endif # EC_LENOVO_H8 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3a99b52..679b96c 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -354,7 +354,7 @@ h8_set_audio_mute(0); -#if !CONFIG(H8_DOCK_EARLY_INIT) +#if CONFIG(H8_NEED_DOCK_INIT) && !CONFIG(H8_DOCK_EARLY_INIT) h8_mainboard_init_dock(); #endif } diff --git a/src/mainboard/lenovo/l520/mainboard.c b/src/mainboard/lenovo/l520/mainboard.c index db695b1..88c7884 100644 --- a/src/mainboard/lenovo/l520/mainboard.c +++ b/src/mainboard/lenovo/l520/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 2caf1d3..171cb29 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -10,6 +10,7 @@ select EC_LENOVO_PMH7 select EC_LENOVO_H8 select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select BOARD_ROMSIZE_KB_8192 if !BOARD_LENOVO_R500 select BOARD_ROMSIZE_KB_4096 if BOARD_LENOVO_R500 diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 329d08d..600b8a6 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -21,6 +21,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT select MAINBOARD_HAS_LIBGFXINIT config VBOOT diff --git a/src/mainboard/lenovo/t420/mainboard.c b/src/mainboard/lenovo/t420/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420/mainboard.c +++ b/src/mainboard/lenovo/t420/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t420s/mainboard.c b/src/mainboard/lenovo/t420s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t420s/mainboard.c +++ b/src/mainboard/lenovo/t420s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c index 99a5bd8..a86a90e 100644 --- a/src/mainboard/lenovo/t430/mainboard.c +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -17,10 +17,6 @@ #include <drivers/intel/gma/int15.h> #include <ec/lenovo/h8/h8.h> -void h8_mainboard_init_dock (void) -{ -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, diff --git a/src/mainboard/lenovo/t430s/mainboard.c b/src/mainboard/lenovo/t430s/mainboard.c index 6c85aba..bc6dcb1 100644 --- a/src/mainboard/lenovo/t430s/mainboard.c +++ b/src/mainboard/lenovo/t430s/mainboard.c @@ -26,10 +26,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index bd4292a..6825b6b 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -28,10 +28,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t530/mainboard.c b/src/mainboard/lenovo/t530/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/t530/mainboard.c +++ b/src/mainboard/lenovo/t530/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index bc8fa29..86351c8 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -19,6 +19,7 @@ select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT select I945_LVDS diff --git a/src/mainboard/lenovo/x131e/mainboard.c b/src/mainboard/lenovo/x131e/mainboard.c index 1342aca..50b4de1 100644 --- a/src/mainboard/lenovo/x131e/mainboard.c +++ b/src/mainboard/lenovo/x131e/mainboard.c @@ -24,10 +24,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock(void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c index 64cc15b..bc6dcb1 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/mainboard.c @@ -29,8 +29,3 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - -/* TODO: this device doesnt have a dock */ -void h8_mainboard_init_dock (void) -{ -} diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index fab8a88..8cab040 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -23,6 +23,7 @@ select DRIVERS_LENOVO_WACOM select MAINBOARD_HAS_LIBGFXINIT select MAINBOARD_USES_IFD_GBE_REGION + select H8_NEED_DOCK_INIT if BOARD_LENOVO_X200 config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/x200/Makefile.inc b/src/mainboard/lenovo/x200/Makefile.inc index f6c2c0c..7e38a78 100644 --- a/src/mainboard/lenovo/x200/Makefile.inc +++ b/src/mainboard/lenovo/x200/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -ramstage-y += variants/$(VARIANT_DIR)/dock.c +ramstage-$(CONFIG_BOARD_LENOVO_X200) += variants/$(VARIANT_DIR)/dock.c ramstage-y += cstates.c ramstage-y += blc.c romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/lenovo/x200/variants/x301/dock.c b/src/mainboard/lenovo/x200/variants/x301/dock.c deleted file mode 100644 index f8a2dc4..0000000 --- a/src/mainboard/lenovo/x200/variants/x301/dock.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> - * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <ec/lenovo/h8/h8.h> - -void h8_mainboard_init_dock(void) -{ -} diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index e40c0d3..21edec79 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -22,6 +22,7 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION select H8_HAS_BAT_TRESHOLDS_IMPL + select H8_NEED_DOCK_INIT config VBOOT select VBOOT_VBNV_CMOS diff --git a/src/mainboard/lenovo/x220/mainboard.c b/src/mainboard/lenovo/x220/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x220/mainboard.c +++ b/src/mainboard/lenovo/x220/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x230/mainboard.c b/src/mainboard/lenovo/x230/mainboard.c index 29c15e0..144fde7 100644 --- a/src/mainboard/lenovo/x230/mainboard.c +++ b/src/mainboard/lenovo/x230/mainboard.c @@ -29,10 +29,6 @@ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } -void h8_mainboard_init_dock (void) -{ -} - struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index e3aabf3..27c953b 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -22,6 +22,7 @@ select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select USE_OPTION_TABLE + select H8_NEED_DOCK_INIT select H8_DOCK_EARLY_INIT select DRIVERS_LENOVO_WACOM select I945_LVDS -- To view, visit https://review.coreboot.org/c/coreboot/+/36385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5737406d1f6cb6e91b2e2fa349a206a3dba988d1 Gerrit-Change-Number: 36385 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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