coreboot-gerrit February 2020

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Change in coreboot[master]: Documentation: Add new GSoC projects
by Patrick Rudolph (Code Review) 20 Mar '20

20 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38829 ) Change subject: Documentation: Add new GSoC projects ...................................................................... Documentation: Add new GSoC projects Change-Id: I5d67361286da04819def3227b2c6cb41a063fc5b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/contributing/project_ideas.md 1 file changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38829/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 90164a2..4090e9e 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -179,3 +179,54 @@ ### Mentors * Ron Minnich <rminnich(a)google.com> + +## Complete the automatic FMAP generation +Improve automatically generated FMAPs in coreboot. + +FMAPs describe the flash layout, seperating the flash chip into regions +and sub-regions. coreboot is placed in one or multiple of this regions, +but usually additional ones are required (Intel ME, MRC cache, ...). + +Currently the FMAP needs to manually generated on non-x86 devices or if +VBOOT is to be used. It would be useful to extend the current tools +to automatically generated FMAPs based on selected architecture and +SoC. + +### Requirements +* coreboot knowledge: Have a general concept of the build system +* other knowledge: Experience with C and bash +* hardware requirements: Nothing special + +### Mentors +* Patrick Rudolph <patrick.rudolph(a)9elements.com> +* Christian Walter <christian.walter(a)9elements.com> + +## Boardstatus replacement +The [Board status page](https://coreboot.org/status/board-status.html) allows +to see last working commit of a board. The page is generated by a cron job +that runs on a huge git reposity. + +Build an open source replacement using exisiting tools and libraries, +consisting out of a backend, a frontend and client side scripts. +The backend should connect to an SQL database with can be controlled using +a REST API / gRPC / XMLRPC connection. + +The frontend should use React to display the current board status. + +Provide a script that allows to: +1. Push mainboard details from coreboot master CI +2. Push mainboard test results from authenticated users containing + * commit hash + * bootlog + * dmesg + * timestamps + * coreboot config + +### Requirements +* coreboot knowledge: Not required +* software knowledge: You must be able to implement a nice website with + client/server model using an SQL database, authentication and RPC interfaces. + +### Mentors +* Patrick Rudolph <patrick.rudolph(a)9elements.com> +* Christian Walter <christian.walter(a)9elements.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/38829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d67361286da04819def3227b2c6cb41a063fc5b Gerrit-Change-Number: 38829 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asrock: add Asrock B85M Pro4
by Angel Pons (Code Review) 19 Mar '20

19 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36770 ) Change subject: mb/asrock: add Asrock B85M Pro4 ...................................................................... mb/asrock: add Asrock B85M Pro4 Does not boot... Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/asrock/b85m_pro4/Kconfig A src/mainboard/asrock/b85m_pro4/Kconfig.name A src/mainboard/asrock/b85m_pro4/Makefile.inc A src/mainboard/asrock/b85m_pro4/acpi/ec.asl A src/mainboard/asrock/b85m_pro4/acpi/platform.asl A src/mainboard/asrock/b85m_pro4/acpi/superio.asl A src/mainboard/asrock/b85m_pro4/acpi_tables.c A src/mainboard/asrock/b85m_pro4/board_info.txt A src/mainboard/asrock/b85m_pro4/bootblock.c A src/mainboard/asrock/b85m_pro4/cmos.default A src/mainboard/asrock/b85m_pro4/cmos.layout A src/mainboard/asrock/b85m_pro4/data.vbt A src/mainboard/asrock/b85m_pro4/devicetree.cb A src/mainboard/asrock/b85m_pro4/dsdt.asl A src/mainboard/asrock/b85m_pro4/gma-mainboard.ads A src/mainboard/asrock/b85m_pro4/gpio.c A src/mainboard/asrock/b85m_pro4/hda_verb.c A src/mainboard/asrock/b85m_pro4/romstage.c 18 files changed, 837 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/36770/1 diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig new file mode 100644 index 0000000..53e95ca --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -0,0 +1,47 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_ASROCK_B85M_PRO4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + +config MAINBOARD_DIR + string + default asrock/b85m_pro4 + +config MAINBOARD_PART_NUMBER + string + default "B85M Pro4" + +config MAX_CPUS + int + default 8 + +endif diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig.name b/src/mainboard/asrock/b85m_pro4/Kconfig.name new file mode 100644 index 0000000..4bb4dfd --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_B85M_PRO4 + bool "B85M Pro4" diff --git a/src/mainboard/asrock/b85m_pro4/Makefile.inc b/src/mainboard/asrock/b85m_pro4/Makefile.inc new file mode 100644 index 0000000..d9a8d18 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/Makefile.inc @@ -0,0 +1,5 @@ +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +bootblock-y += bootblock.c diff --git a/src/mainboard/asrock/b85m_pro4/acpi/ec.asl b/src/mainboard/asrock/b85m_pro4/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/ec.asl diff --git a/src/mainboard/asrock/b85m_pro4/acpi/platform.asl b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl new file mode 100644 index 0000000..f3b1492 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/platform.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PTS,1) +{ +} + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/asrock/b85m_pro4/acpi/superio.asl b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c new file mode 100644 index 0000000..10e5f94 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/lynxpoint/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/asrock/b85m_pro4/board_info.txt b/src/mainboard/asrock/b85m_pro4/board_info.txt new file mode 100644 index 0000000..21b2cd3 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H81M-HDS/ FIXME +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c new file mode 100644 index 0000000..8e66bed --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Select HWM/LED functions instead of floppy functions. */ + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x1c, 0x03); + pnp_write_config(GLOBAL_PSEUDO_DEV, 0x24, 0x24); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default new file mode 100644 index 0000000..c51001c --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +nmi=Enable +power_on_after_fail=Disable diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout new file mode 100644 index 0000000..4926a45 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -0,0 +1,94 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 3 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 4 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 5 power_on_after_fail + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable + +2 0 Enable +2 1 Disable + +3 0 Fallback +3 1 Normal + +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew + +5 0 Disable +5 1 Enable +5 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asrock/b85m_pro4/data.vbt b/src/mainboard/asrock/b85m_pro4/data.vbt new file mode 100644 index 0000000..93b2418 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/data.vbt Binary files differ diff --git a/src/mainboard/asrock/b85m_pro4/devicetree.cb b/src/mainboard/asrock/b85m_pro4/devicetree.cb new file mode 100644 index 0000000..3f10a01 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/devicetree.cb @@ -0,0 +1,130 @@ +chip northbridge/intel/haswell + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + + register "gpu_ddi_e_connected" = "1" + + device cpu_cluster 0x0 on + chip cpu/intel/haswell + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + + device lapic 0 on end + device lapic 0xacac off end + end + end + + device domain 0x0 on + chip southbridge/intel/lynxpoint + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x83" + register "pirqd_routing" = "0x8a" + register "pirqe_routing" = "0x8b" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x8a" + register "pirqh_routing" = "0x83" + + register "sata_ahci" = "1" + register "sata_port_map" = "0x3f" + + device pci 14.0 on # xHCI controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # Management Engine interface 1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off end # Management Engine interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # EHCI controller #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # HD audio controller + subsystemid 0x1849 0x7662 + end + + device pci 1c.0 on end + device pci 1c.1 on end + device pci 1c.2 on end + device pci 1c.3 on end + device pci 1c.4 on end + device pci 1c.5 on end + device pci 1c.6 on end + device pci 1c.7 on end + + device pci 1d.0 on # EHCI controller #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c5c + + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 # Keyboard + irq 0x72 = 0x0c # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO8 + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 off end # GPIO2 + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + end + device pci 1f.2 on # SATA controller 1 + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/b85m_pro4/dsdt.asl b/src/mainboard/asrock/b85m_pro4/dsdt.asl new file mode 100644 index 0000000..91fe40b --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/dsdt.asl @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + #include "acpi/platform.asl" + #include "acpi/superio.asl" + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/haswell.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } +} diff --git a/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads new file mode 100644 index 0000000..a5b705e --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Angel Pons <th3fanbus(a)gmail.com> +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; version 2 of the License. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI2, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/b85m_pro4/gpio.c b/src/mainboard/asrock/b85m_pro4/gpio.c new file mode 100644 index 0000000..4400451 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/gpio.c @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/b85m_pro4/hda_verb.c b/src/mainboard/asrock/b85m_pro4/hda_verb.c new file mode 100644 index 0000000..7345ad0 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/hda_verb.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0892, /* Codec Vendor / Device ID: Realtek */ + 0x1849c892, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x1849c892), + + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1a, 0x02a11c3f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x01813c30), + AZALIA_PIN_CFG(0x0, 0x1d, 0x598301f0), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x21, 0x0221102f), + + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x1458a002, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x2, 0x1458a002), + AZALIA_PIN_CFG(0x2, 0x11, 0x411110f0), + AZALIA_PIN_CFG(0x2, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x14, 0x01014410), + AZALIA_PIN_CFG(0x2, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x18, 0x01a19c50), + AZALIA_PIN_CFG(0x2, 0x19, 0x02a19c60), + AZALIA_PIN_CFG(0x2, 0x1a, 0x0181345f), + AZALIA_PIN_CFG(0x2, 0x1b, 0x02214c20), + AZALIA_PIN_CFG(0x2, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1d, 0x4004c601), + AZALIA_PIN_CFG(0x2, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x2, 0x1f, 0x41c46060), + + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + AZALIA_PIN_CFG(0x3, 0x05, 0x58560010), + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c new file mode 100644 index 0000000..de1fea4 --- /dev/null +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2018 Tristan Corrick <tristan(a)corrick.kiwi> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/romstage.h> +#include <cpu/intel/haswell/haswell.h> +#include <device/pnp_ops.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/pei_data.h> +#include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> + +static const struct rcba_config_instruction rcba_config[] = { + RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), + RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), + RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), + RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), + RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), + RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), + RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), + RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), + + RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), + + RCBA_END_CONFIG, +}; + +void mainboard_romstage_entry(void) +{ + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = (uintptr_t)DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 1, /* desktop/server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ec_present = 0, + .dimm_channel0_disabled = 0, /* Everything enabled. */ + .dimm_channel1_disabled = 0, /* Everything enabled. */ + .max_ddr3_freq = 1600, + .usb2_ports = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 6, USB_PORT_BACK_PANEL }, + }, + .usb3_ports = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, + }, + }; + + struct romstage_params romstage_params = { + .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, + .rcba_config = &rcba_config[0], + }; + + romstage_common(&romstage_params); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36770 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10a16dfc56f2aa88648c8aaaba4feab40c491504 Gerrit-Change-Number: 36770 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

7 24

Change in coreboot[master]: soc/intel/common/block/lpc: Add support to allow all UART options
by Wim Vervoorn (Code Review) 18 Mar '20

18 Mar '20

Wim Vervoorn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38748 ) Change subject: soc/intel/common/block/lpc: Add support to allow all UART options ...................................................................... soc/intel/common/block/lpc: Add support to allow all UART options The current implementation only allows 0x3f8 for COMA and 0x2f8 for COMB in the LPC decode. Add the support to allow selection of all options supported by the PCH. BUG=N/A TEST=build Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Signed-off-by: Wim Vervoorn <wvervoorn(a)eltan.com> --- M src/soc/intel/common/block/lpc/Kconfig M src/soc/intel/common/block/lpc/lpc_def.h 2 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38748/1 diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig index 41e72c4..b95e9be 100644 --- a/src/soc/intel/common/block/lpc/Kconfig +++ b/src/soc/intel/common/block/lpc/Kconfig @@ -11,3 +11,25 @@ help By default COMA range to LPC is enable. COMB range to LPC is optional and should select based on platform dedicated selection. + +config SOC_INTEL_COMMON_BLOCK_LPC_COMA_UART + int + prompt "Index for COMA UART" + depends on SOC_INTEL_COMMON_BLOCK_LPC && DRIVERS_UART_8250IO + default 0 + range 0 7 + help + Select an I/O port for COMA (Used to open LPC IO window) + 0 = 0x3f8, 1 = 0x2f8, 2 = 0x220, 3 = 0x228, + 4 = 0x238, 5 = 0x2e8, 6 = 0x338, 7 = 0x3e8 + +config SOC_INTEL_COMMON_BLOCK_LPC_COMB_UART + int + prompt "Index for COMB UART" if DRIVERS_UART_8250IO + depends on SOC_INTEL_COMMON_BLOCK_LPC && DRIVERS_UART_8250IO && SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE + default 1 + range 0 7 + help + Select an I/O port for COMB (Used to open LPC IO window) + 0 = 0x3f8, 1 = 0x2f8, 2 = 0x220, 3 = 0x228, + 4 = 0x238, 5 = 0x2e8, 6 = 0x338, 7 = 0x3e8 diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h index 9a72580..7af235f 100644 --- a/src/soc/intel/common/block/lpc/lpc_def.h +++ b/src/soc/intel/common/block/lpc/lpc_def.h @@ -21,8 +21,8 @@ #define LPC_SCNT_EN (1 << 7) #define LPC_SCNT_MODE (1 << 6) #define LPC_IO_DECODE 0x80 -#define LPC_IOD_COMA_RANGE (0 << 0) /* 0x3F8 - 0x3FF COMA*/ -#define LPC_IOD_COMB_RANGE (1 << 4) /* 0x2F8 - 0x2FF COMB*/ +#define LPC_IOD_COMA_RANGE (CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMA_UART << 0) +#define LPC_IOD_COMB_RANGE (CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_COMB_UART << 4) /* Use IO_<peripheral>_<IO port> style macros defined in lpc_lib.h * to enable decoding of I/O locations for a peripheral. */ #define LPC_IO_ENABLES 0x82 -- To view, visit https://review.coreboot.org/c/coreboot/+/38748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad7bb0e44739e8d656a542c79af7f98a4e9bde69 Gerrit-Change-Number: 38748 Gerrit-PatchSet: 1 Gerrit-Owner: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Wim Vervoorn <wvervoorn(a)eltan.com> Gerrit-MessageType: newchange

8 23

Change in coreboot[master]: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
by Brandon Breitenstein (Code Review) 18 Mar '20

18 Mar '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38737 ) Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT ...................................................................... soc/tigerlake: Update FSP UPDs to turn on USB4/TBT FSP needs to know to allow the root ports for USB4/TBT to be enabled This patch may need additional checks for each board as it might not be the right thing to turn them all on for every tigerlake board. BUG=b:141609883 BRANCH=NONE TEST=Built image and verified that the root ports were visible with lspci Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/1 diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index 305748e..22c1b2a 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,10 @@ sizeof(params->SataPortsDevSlp)); } + /* USB4/TBT */ + for (i = 0; i < 4; i++) + params->ITbtPcieRootPortEn[i] = 1; + mainboard_silicon_init_params(params); } diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index fc3155f..0d11306 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -129,6 +129,13 @@ config = config_of_soc(); soc_memory_init_params(m_cfg, config); + + /* USB4/TBT */ + m_cfg->TcssItbtPcie0En = 1; + m_cfg->TcssItbtPcie1En = 1; + m_cfg->TcssItbtPcie2En = 1; + m_cfg->TcssItbtPcie3En = 1; + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf Gerrit-Change-Number: 38737 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

7 20

Change in coreboot[master]: util/autoport: Correct formatting issues
by Angel Pons (Code Review) 18 Mar '20

18 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38901 ) Change subject: util/autoport: Correct formatting issues ...................................................................... util/autoport: Correct formatting issues There is no need to use hexadecimal values in azalia codec IDs, nor need to print a redundant "LPC bridge PCI-LPC bridge" comment. Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/azalia.go M util/autoport/bd82x6x.go 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38901/1 diff --git a/util/autoport/azalia.go b/util/autoport/azalia.go index d94441b..c98b03c 100644 --- a/util/autoport/azalia.go +++ b/util/autoport/azalia.go @@ -26,7 +26,7 @@ codec.SubsystemID) fmt.Fprintf(az, "\t%d,\t\t/* Number of 4 dword sets */\n", len(codec.PinConfig)+1) - fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(0x%x, 0x%08x),\n", + fmt.Fprintf(az, "\tAZALIA_SUBVENDOR(%d, 0x%08x),\n", codec.CodecNo, codec.SubsystemID) keys := []int{} @@ -37,7 +37,7 @@ sort.Ints(keys) for _, nid := range keys { - fmt.Fprintf(az, "\tAZALIA_PIN_CFG(0x%x, 0x%02x, 0x%08x),\n", + fmt.Fprintf(az, "\tAZALIA_PIN_CFG(%d, 0x%02x, 0x%08x),\n", codec.CodecNo, nid, codec.PinConfig[nid]) } az.WriteString("\n"); diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 3ad212b..87e7584 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -277,7 +277,7 @@ } PutPCIChip(addr, cur) - PutPCIDevParent(addr, "PCI-LPC bridge", "lpc") + PutPCIDevParent(addr, "", "lpc") DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/common/acpi/platform.asl", -- To view, visit https://review.coreboot.org/c/coreboot/+/38901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6658051c7a3d5b65a86ccca8bab7834bf4628a16 Gerrit-Change-Number: 38901 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/picasso: Remove unused defines from cpu.h
by Marshall Dawson (Code Review) 17 Mar '20

17 Mar '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38693 ) Change subject: soc/amd/picasso: Remove unused defines from cpu.h ...................................................................... soc/amd/picasso: Remove unused defines from cpu.h Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I4ed3e7c82ef5808a0e96c07c16f4872f8ca3ec76 --- M src/soc/amd/picasso/include/soc/cpu.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38693/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 9af4c0c..338e871 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,9 +18,6 @@ #include <device/device.h> -#define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_TEMPRAM 2 - #define CSTATE_BASE_REG 0xc0010073 void picasso_init_cpus(struct device *dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/38693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ed3e7c82ef5808a0e96c07c16f4872f8ca3ec76 Gerrit-Change-Number: 38693 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Move get_soc_config to common location
by Marshall Dawson (Code Review) 17 Mar '20

17 Mar '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38695 ) Change subject: soc/amd/picasso: Move get_soc_config to common location ...................................................................... soc/amd/picasso: Move get_soc_config to common location Multiple files can eventually take advantage of the static function in i2c.c. Move get_soc_config() into a new common location for all to use. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/cfg_util.c M src/soc/amd/picasso/i2c.c 3 files changed, 31 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/38695/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 59f8e4c..b4ced2c 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -84,6 +84,7 @@ ramstage-y += tsc_freq.c ramstage-y += finalize.c +all-y += cfg_util.c all-y += reset.c smm-y += smihandler.c diff --git a/src/soc/amd/picasso/cfg_util.c b/src/soc/amd/picasso/cfg_util.c new file mode 100644 index 0000000..60555e4 --- /dev/null +++ b/src/soc/amd/picasso/cfg_util.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <soc/pci_devs.h> +#include "chip.h" + +const config_t *get_soc_config(void) +{ + const struct device *dev = pcidev_path_on_root(GNB_DEVFN); + + if (!dev || !dev->chip_info) { + printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", + __func__); + return NULL; + } + + return dev->chip_info; +} diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index bcdf385..408b60b 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -42,19 +42,6 @@ return i2c_bus_address[bus - APU_I2C_MIN_BUS]; } -static const struct soc_amd_picasso_config *get_soc_config(void) -{ - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); - - if (!dev || !dev->chip_info) { - printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n", - __func__); - return NULL; - } - - return dev->chip_info; -} - const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; -- To view, visit https://review.coreboot.org/c/coreboot/+/38695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5d9be2f74cde370979033365af2e355eb6d814e Gerrit-Change-Number: 38695 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINU...
by Jeremy Soller (Code Review) 17 Mar '20

17 Mar '20

Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31536 Change subject: soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE ...................................................................... soc/intel/cannonlake: Set correct serirq mode based on SERIRQ_CONTINUOUS_MODE Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/31536/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index cd8819d..3716640 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -172,6 +172,13 @@ default 24 if SOC_INTEL_CANNONLAKE_PCH_H default 16 +config SERIRQ_CONTINUOUS_MODE + bool + default n + help + If you set this option to y, the serial IRQ machine will be + operated in continuous mode. + config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..c95a68f 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -246,6 +246,12 @@ /* Set TccActivationOffset */ tconfig->TccActivationOffset = config->tcc_offset; + + /* Set correct Sirq mode based on config */ + if (IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)) + params->PchSirqMode = 1; + else + params->PchSirqMode = 0; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59 Gerrit-Change-Number: 31536 Gerrit-PatchSet: 1 Gerrit-Owner: Jeremy Soller <jackpot51(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Correct mask for CxDRT1
by HAOUAS Elyes (Code Review) 16 Mar '20

16 Mar '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31144 Change subject: nb/intel/i945: Correct mask for CxDRT1 ...................................................................... nb/intel/i945: Correct mask for CxDRT1 [27:24] and [31:30] are reserved, so we shouldn't change them. Tested on i945G-M4 board. Change-Id: I0cac9160c756405838706edb0461575241faae35 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/31144/1 diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f3c3df6..2a62ca3 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1475,7 +1475,7 @@ /* Calculate DRT1 */ - temp_drt = MCHBAR32(C0DRT1) & 0x00020088; + temp_drt = MCHBAR32(C0DRT1) & 0xcf020088; /* DRAM RASB Precharge */ temp_drt |= (sysinfo->trp - 2) << 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/31144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cac9160c756405838706edb0461575241faae35 Gerrit-Change-Number: 31144 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/inteltool: Split GPIO community switch-case into its own function
by Mimoja (Code Review) 16 Mar '20

16 Mar '20

Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38631 ) Change subject: util/inteltool: Split GPIO community switch-case into its own function ...................................................................... util/inteltool: Split GPIO community switch-case into its own function So far priting the GPIO groups chose the community defition. As the list of supported platforms grows the massive switch case gets repetetive and hinders the readers view. It also reduces the ability to reuse the code in an potential libinteltool. To takle these issues the detection logic was split into its own function. Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9 Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M util/inteltool/gpio_groups.c M util/inteltool/inteltool.h 2 files changed, 38 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/38631/1 diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 8b60c2b..4c32558 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -96,11 +96,11 @@ } } -void print_gpio_groups(struct pci_dev *const sb) +const struct gpio_community *const *get_gpio_communitys(struct pci_dev *const sb, + size_t* community_count, + size_t* pad_stepping) { - size_t community_count; - const struct gpio_community *const *communities; - size_t pad_stepping = 8; + *pad_stepping = 8; switch (sb->device_id) { case PCI_DEVICE_ID_INTEL_H110: @@ -114,10 +114,8 @@ case PCI_DEVICE_ID_INTEL_QM170: case PCI_DEVICE_ID_INTEL_HM170: case PCI_DEVICE_ID_INTEL_CM236: - community_count = ARRAY_SIZE(sunrise_communities); - communities = sunrise_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(sunrise_communities); + return sunrise_communities; case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL: @@ -128,10 +126,8 @@ case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: - community_count = ARRAY_SIZE(sunrise_lp_communities); - communities = sunrise_lp_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(sunrise_lp_communities); + return sunrise_lp_communities; case PCI_DEVICE_ID_INTEL_C621: case PCI_DEVICE_ID_INTEL_C622: case PCI_DEVICE_ID_INTEL_C624: @@ -145,20 +141,14 @@ case PCI_DEVICE_ID_INTEL_C621_SUPER: case PCI_DEVICE_ID_INTEL_C627_SUPER_2: case PCI_DEVICE_ID_INTEL_C628_SUPER: - community_count = ARRAY_SIZE(lewisburg_communities); - communities = lewisburg_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(lewisburg_communities); + return lewisburg_communities; case PCI_DEVICE_ID_INTEL_DNV_LPC: - community_count = ARRAY_SIZE(denverton_communities); - communities = denverton_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(denverton_communities); + return denverton_communities; case PCI_DEVICE_ID_INTEL_APL_LPC: - community_count = ARRAY_SIZE(apl_communities); - communities = apl_communities; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(apl_communities); + return apl_communities; case PCI_DEVICE_ID_INTEL_H310: case PCI_DEVICE_ID_INTEL_H370: case PCI_DEVICE_ID_INTEL_Z390: @@ -169,20 +159,30 @@ case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: - community_count = ARRAY_SIZE(cannonlake_pch_h_communities); - communities = cannonlake_pch_h_communities; - pad_stepping = 16; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(cannonlake_pch_h_communities); + *pad_stepping = 16; + return cannonlake_pch_h_communities; case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: - community_count = ARRAY_SIZE(icelake_pch_h_communities); - communities = icelake_pch_h_communities; - pad_stepping = 16; - pcr_init(sb); - break; + *community_count = ARRAY_SIZE(icelake_pch_h_communities); + *pad_stepping = 16; + return icelake_pch_h_communities; default: - return; + return NULL; } +} + +void print_gpio_groups(struct pci_dev *const sb) +{ + size_t community_count; + const struct gpio_community *const *communities; + size_t pad_stepping; + + communities = get_gpio_communitys(sb, &community_count, &pad_stepping); + + if (!communities) + return; + + pcr_init(sb); printf("\n============= GPIOS =============\n\n"); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1c1841c..5fa98b5 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -393,6 +393,9 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb, int show_all, int show_diffs); +const struct gpio_community *const *get_gpio_communitys(struct pci_dev *const sb, + size_t* community_count, + size_t* pad_stepping); void print_gpio_groups(struct pci_dev *sb); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); -- To view, visit https://review.coreboot.org/c/coreboot/+/38631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I215c1b7d6ec164b8afd9489ebd54b63d3df50cb9 Gerrit-Change-Number: 38631 Gerrit-PatchSet: 1 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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