coreboot-gerrit February 2020

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Change in coreboot[master]: asus/p2b-ls: Drop SCSI from devicetree
by Keith Hui (Code Review) 29 Mar '20

29 Mar '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38602 ) Change subject: asus/p2b-ls: Drop SCSI from devicetree ...................................................................... asus/p2b-ls: Drop SCSI from devicetree SCSI bus on this board does not need any special treatment facilitated by devicetree.cb. Change-Id: I5ee9cd605bf4c22561f826945be1374fd8257c82 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b-ls/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38602/1 diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b-ls/devicetree.cb index 5e55278..9a5f278 100644 --- a/src/mainboard/asus/p2b-ls/devicetree.cb +++ b/src/mainboard/asus/p2b-ls/devicetree.cb @@ -48,7 +48,6 @@ device pci 4.1 on end # IDE device pci 4.2 on end # USB device pci 4.3 on end # ACPI - device pci 6.0 on end # Onboard SCSI register "ide0_enable" = "1" register "ide1_enable" = "1" register "ide_legacy_enable" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/38602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ee9cd605bf4c22561f826945be1374fd8257c82 Gerrit-Change-Number: 38602 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: SKL: Add ACPI brightness control
by Matthew Garrett (Code Review) 29 Mar '20

29 Mar '20

Matthew Garrett has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32549 Change subject: SKL: Add ACPI brightness control ...................................................................... SKL: Add ACPI brightness control Hook up the generic src/drivers/intel/gma ACPI backlight control for Skylake. Based on a patch by Matt DeVillier <matt.devillier(a)gmail.com>. Signed-off-by: Matthew Garrett <mjg59(a)google.com> Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 --- M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/graphics.h M src/soc/intel/skylake/acpi/globalnvs.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/graphics.c M src/soc/intel/skylake/include/soc/nvs.h 7 files changed, 40 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32549/1 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 5d3b4a1..6489e8e 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -33,6 +33,10 @@ pci_dev_init(dev); } +__weak void gma_ssdt(struct device *dev) +{ +} + static uintptr_t graphics_get_bar(unsigned long index) { struct device *dev = SA_DEV_IGD; @@ -104,6 +108,7 @@ .init = graphics_soc_init, .ops_pci = &pci_dev_ops_pci, .write_acpi_tables = graphics_soc_write_acpi_opregion, + .acpi_fill_ssdt_generator = gma_ssdt, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/common/block/include/intelblocks/graphics.h b/src/soc/intel/common/block/include/intelblocks/graphics.h index 6be7661..077f0db 100644 --- a/src/soc/intel/common/block/include/intelblocks/graphics.h +++ b/src/soc/intel/common/block/include/intelblocks/graphics.h @@ -51,4 +51,7 @@ void graphics_gtt_rmw(unsigned long reg, uint32_t andmask, uint32_t ormask); uintptr_t graphics_get_memory_base(void); +void gma_ssdt(struct device *dev); +struct i915_gpu_controller_info *intel_igd_get_controller_info(void); + #endif /* SOC_INTEL_COMMON_BLOCK_GRAPHICS_H */ diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index c4544e8..6963f70 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -70,6 +70,9 @@ EPCS, 8, // 0x43 - SGX Enabled status EMNA, 64, // 0x44 - 0x4B EPC base address ELNG, 64, // 0x4C - 0x53 EPC Length + BRTL, 32, // 0x54 - 0x57 Brightness Level + CSTE, 16, // 0x58 - 0x59 Current display state + NSTE, 16, // 0x5a - 0x5b Next display state /* IGD OpRegion */ Offset (0xb4), diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl index 0aba2e7..f0095bc 100644 --- a/src/soc/intel/skylake/acpi/pch.asl +++ b/src/soc/intel/skylake/acpi/pch.asl @@ -56,6 +56,9 @@ /* USB XHCI 0:14.0 */ #include "xhci.asl" +/* Graphics */ +#include <drivers/intel/gma/acpi/pch.asl> + Method (_OSC, 4) { /* Check for proper GUID */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 57d51e7..51bb740 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -22,6 +22,7 @@ #include <arch/acpi_device.h> #include <device/i2c_simple.h> #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/i915.h> #include <intelblocks/chip.h> #include <intelblocks/gspi.h> #include <intelblocks/lpc_lib.h> @@ -580,6 +581,8 @@ /* Enable/Disable Sata power optimization */ u8 SataPwrOptEnable; + + struct i915_gpu_controller_info gfx; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c index 07ee67a..1be5f9d 100644 --- a/src/soc/intel/skylake/graphics.c +++ b/src/soc/intel/skylake/graphics.c @@ -122,3 +122,22 @@ printk(BIOS_DEBUG, "current = %lx\n", current); return current; } + +struct i915_gpu_controller_info *intel_igd_get_controller_info(void) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + if (!dev) + return NULL; + struct soc_intel_skylake_config *chip = dev->chip_info; + return &chip->gfx; +} + +void gma_ssdt(struct device *dev) +{ + struct i915_gpu_controller_info *gfx = intel_igd_get_controller_info(); + + if (!gfx) + return; + + drivers_intel_gma_displays_ssdt_generate(gfx); +} diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 72b1ac9..5a2ca38 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -60,7 +60,10 @@ u8 ecps; /* 0x43 - SGX Enabled status */ u64 emna; /* 0x44 - 0x4B EPC base address */ u64 elng; /* 0x4C - 0x53 EPC Length */ - u8 rsvd[96]; + u32 brtl; /* 0x54 - 0x57 Brightness Level */ + u16 cste; /* 0x58 - 0x59 Current display state */ + u16 nste; /* 0x5a - 0x5b Next display state */ + u8 rsvd[88]; /* IGD OpRegion */ u32 aslb; /* 0xb4 - IGD OpRegion Base Address */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I993770fdcd0a28cee756df2bd6a795498f175952 Gerrit-Change-Number: 32549 Gerrit-PatchSet: 1 Gerrit-Owner: Matthew Garrett <mjg59(a)google.com> Gerrit-MessageType: newchange

8 23

Change in ...coreboot[master]: Disable SeaBIOS options not supported by hardware: scripts to apply t...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33885 Change subject: Disable SeaBIOS options not supported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options not supported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:33870 and CB:33871 to disable SeaBIOS options not supported by G505S and AM1I-A hardware. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/33870 src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware https://review.coreboot.org/c/coreboot/+/33871 src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/33885/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..c1212bf --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +patch -p1 < "./0cd2b7a.diff" +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..5e4c1ef --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./053e2ea.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./0cd2b7a.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..0ce0113c --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33870 +### src/mainboard/lenovo/g505s: Disable SeaBIOS options not supported by hardware +### +rm -f "./053e2ea.diff" +wget "https://review.coreboot.org/changes/33870/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./053e2ea.diff" +### +### https://review.coreboot.org/c/coreboot/+/33871 +### src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware +### +rm -f "./0cd2b7a.diff" +wget "https://review.coreboot.org/changes/33871/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./0cd2b7a.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..5135520 --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +ed3f92502e35897256e364e146ad7515414552c4e4e87031bfaae1f30ecdad1d ./053e2ea.diff +6c5fd1060ccf3b84687eb76594ed63a76472c573ea968d9efec40f4c3eccb53d ./0cd2b7a.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33885 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e50be0454b3a7e0a89a77e6846f8a7d9cf0a5e Gerrit-Change-Number: 33885 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 11

Change in ...coreboot[master]: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by h...
by Mike Banon (Code Review) 28 Mar '20

28 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33871 Change subject: src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware ...................................................................... src/mainboard/asus/am1i-a: Disable SeaBIOS options not supported by hardware AM1I-A does not have any SAS or NVMe controllers, so it makes sense to disable the related SeaBIOS options for this motherboard. This reduces the size of compiled SeaBIOS by 129344-124096 = 5248 bytes. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 --- M src/mainboard/asus/am1i-a/Kconfig A src/mainboard/asus/am1i-a/config_seabios 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/33871/1 diff --git a/src/mainboard/asus/am1i-a/Kconfig b/src/mainboard/asus/am1i-a/Kconfig index d50edbe..6d88992 100644 --- a/src/mainboard/asus/am1i-a/Kconfig +++ b/src/mainboard/asus/am1i-a/Kconfig @@ -54,4 +54,8 @@ bool default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" if PAYLOAD_SEABIOS + endif # BOARD_ASUS_AM1I_A diff --git a/src/mainboard/asus/am1i-a/config_seabios b/src/mainboard/asus/am1i-a/config_seabios new file mode 100644 index 0000000..0ee9cea --- /dev/null +++ b/src/mainboard/asus/am1i-a/config_seabios @@ -0,0 +1,6 @@ +### +### SeaBIOS custom configuration for ASUS AM1I-A +### +# CONFIG_MEGASAS is not set +# CONFIG_NVME is not set +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ddf695f4f349697d08a685fa04c90d3afd723c5 Gerrit-Change-Number: 33871 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: mb/*/*{i440BX}: Enable console in bootblock
by Arthur Heymans (Code Review) 27 Mar '20

27 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36775 ) Change subject: mb/*/*{i440BX}: Enable console in bootblock ...................................................................... mb/*/*{i440BX}: Enable console in bootblock This renames and links romstage.c into both the bootblock and the romstage. The definition of spd_read_byte needs to be guarded in bootblock as the declaration is only done in bootblock. Change-Id: I87e5eb93c15a72f790739eff8395e7eecbf1eb04 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asus/p2b-d/Makefile.inc R src/mainboard/asus/p2b-d/early_init.c A src/mainboard/asus/p2b-ds/Makefile.inc R src/mainboard/asus/p2b-ds/early_init.c A src/mainboard/asus/p2b-f/Makefile.inc R src/mainboard/asus/p2b-f/early_init.c A src/mainboard/asus/p2b-ls/Makefile.inc R src/mainboard/asus/p2b-ls/early_init.c A src/mainboard/asus/p2b/Makefile.inc R src/mainboard/asus/p2b/early_init.c A src/mainboard/asus/p3b-f/Makefile.inc R src/mainboard/asus/p3b-f/early_init.c M src/northbridge/intel/i440bx/Kconfig M src/southbridge/intel/i82371eb/i82371eb.h 14 files changed, 46 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/36775/1 diff --git a/src/mainboard/asus/p2b-d/Makefile.inc b/src/mainboard/asus/p2b-d/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-d/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/early_init.c similarity index 94% rename from src/mainboard/asus/p2b-d/romstage.c rename to src/mainboard/asus/p2b-d/early_init.c index 7fad06b..172ee95 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/early_init.c @@ -15,4 +15,4 @@ */ /* Shares romstage with P2B-DS */ -#include "../p2b-ds/romstage.c" +#include "../p2b-ds/early_init.c" diff --git a/src/mainboard/asus/p2b-ds/Makefile.inc b/src/mainboard/asus/p2b-ds/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-ds/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/early_init.c similarity index 91% rename from src/mainboard/asus/p2b-ds/romstage.c rename to src/mainboard/asus/p2b-ds/early_init.c index 5b3a30b..248cb21 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/early_init.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <device/pci_def.h> +#include <bootblock_common.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> @@ -25,16 +25,20 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } +#endif void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); diff --git a/src/mainboard/asus/p2b-f/Makefile.inc b/src/mainboard/asus/p2b-f/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-f/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/early_init.c similarity index 94% rename from src/mainboard/asus/p2b-f/romstage.c rename to src/mainboard/asus/p2b-f/early_init.c index 31a100c..b61a318 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/early_init.c @@ -15,4 +15,4 @@ */ /* Shares romstage with the better supported P2B-LS sibling. */ -#include "../p2b-ls/romstage.c" +#include "../p2b-ls/early_init.c" diff --git a/src/mainboard/asus/p2b-ls/Makefile.inc b/src/mainboard/asus/p2b-ls/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b-ls/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/early_init.c similarity index 92% rename from src/mainboard/asus/p2b-ls/romstage.c rename to src/mainboard/asus/p2b-ls/early_init.c index f933c77..ef7d3d8 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/early_init.c @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include <device/pci_def.h> +#include <bootblock_common.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> @@ -26,6 +26,12 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); @@ -33,10 +39,8 @@ void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); } +#endif diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/early_init.c similarity index 91% rename from src/mainboard/asus/p2b/romstage.c rename to src/mainboard/asus/p2b/early_init.c index 1d7c928..69450de 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/early_init.c @@ -14,8 +14,7 @@ * GNU General Public License for more details. */ -#include <device/pci_def.h> -#include <console/console.h> +#include <bootblock_common.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> @@ -25,16 +24,20 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } +#endif void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); sdram_initialize(); cbmem_initialize_empty(); diff --git a/src/mainboard/asus/p3b-f/Makefile.inc b/src/mainboard/asus/p3b-f/Makefile.inc new file mode 100644 index 0000000..0a9a8c0 --- /dev/null +++ b/src/mainboard/asus/p3b-f/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-y += early_init.c +romstage-y += early_init.c \ No newline at end of file diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/early_init.c similarity index 95% rename from src/mainboard/asus/p3b-f/romstage.c rename to src/mainboard/asus/p3b-f/early_init.c index 8fc135d..8524098 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/early_init.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <arch/io.h> -#include <device/pci_def.h> #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> @@ -28,10 +28,17 @@ /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +#if ENV_ROMSTAGE int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } +#endif /* * ASUS P3B-F specific SPD enable magic. @@ -66,9 +73,6 @@ void mainboard_romstage_entry(void) { - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_smbus(); enable_pm(); diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 01154da..45cdd9c 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -18,7 +18,6 @@ select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select UDELAY_IO - select NO_BOOTBLOCK_CONSOLE config SDRAMPWR_4DIMM bool diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@ #if !defined(__ACPI__) -#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif void i82371eb_hard_reset(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87e5eb93c15a72f790739eff8395e7eecbf1eb04 Gerrit-Change-Number: 36775 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: vc/amd/fsp/picasso: Add PCIe and DDI helpers
by Marshall Dawson (Code Review) 27 Mar '20

27 Mar '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38698 ) Change subject: vc/amd/fsp/picasso: Add PCIe and DDI helpers ...................................................................... vc/amd/fsp/picasso: Add PCIe and DDI helpers Add a file for generating PCIe and DDI descriptors that will be understandable to the FSP. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 --- A src/vendorcode/amd/fsp/picasso/platform_descriptors.h 1 file changed, 155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/38698/1 diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h new file mode 100644 index 0000000..71603d2 --- /dev/null +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * These definitions are used to describe PCIe bifurcation and display physical + * connector types connected to the SOC. + */ + +#ifndef __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ +#define __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ + +/* Engine descriptor type */ +typedef enum { + UNUSED_ENGINE = 0, // Unused descriptor + PCIE_ENGINE = 1, // PCIe port + USB_ENGINE = 2, // USB port + SATA_ENGINE = 3, // SATA + DP_ENGINE = 8, // Digital Display + ETHERNET_ENGINE = 0x10, // Ethernet (GBe, XGBe) + MAX_ENGINE // Max engine type for boundary check. +} dxio_engine_type; + +/* PCIe link capability/speed */ +typedef enum { + GEN_MAX, // Maximum supported + GEN1 = 1, // Gen1 + GEN2, // Gen2 + GEN3, // Gen3 + GEN_INVALID // Max Gen for boundary check +} dxio_link_speed_cap; + +/* SATA ChannelType initialization */ +typedef enum { + SATA_CHANNEL_OTHER, // Default Channel Type + SATA_CHANNEL_SHORT, // Short Trace Channel Type + SATA_CHANNEL_LONG // Long Trace Channel Type +} dxio_sata_channel_type; + +/* CLKREQ for PCIe type descriptors */ +typedef enum { + CLK_DISABLE = 0x00, + CLK_REQ0, + CLK_REQ1, + CLK_REQ2, + CLK_REQ3, + CLK_REQ4, + CLK_REQ5, + CLK_REQ6, + CLK_REQ7, + CLK_REQ8, + CLK_REQGFX = 0x0c, +} cpm_clk_req; + +/* PCIe link ASPM initialization */ +typedef enum { + ASPM_DISABLED, // Disabled + ASPM_L0s, // PCIe L0s link state + ASPM_L1, // PCIe L1 link state + ASPM_L0sL1, // PCIe L0s & L1 link state + ASPM_MAX // Not valid value, used to verify input +} dxio_aspm_type; + +/* DDI Aux channel */ +typedef enum { + AUX1, // Aux1 + AUX2, // Aux2 + AUX3, // Aux3 + AUX4, // Aux4 + AUX5, // Aux5 + AUX6, // Aux6 + AUX_MAX // Not valid value, used to verify input +} pcie_aux_type; + +/* DDI Hdp Index */ +typedef enum { + HDP1, // Hdp1 + HDP2, // Hdp2 + HDP3, // Hdp3 + HDP4, // Hdp4 + HDP5, // Hdp5 + HDP6, // Hdp6 + HDP_MAX // Not valid value, used to verify input +} pcie_hdp_type; + +/* DDI display connector type */ +typedef enum { + DP, // DP + EDP, // eDP + SINGLE_LINK_DVI, // Single Link DVI-D + DUAL_LINK_DVI, // Dual Link DVI-D + HDMI, // HDMI + DP_TO_VGA, // DP-to-VGA + DP_TO_LVDS, // DP-to-LVDS + NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + SINGLE_LINK_DVI_I, // Single Link DVI-I + CRT, // CRT (VGA) + LVDS, // LVDS + EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + AUTO_DETECT, // VBIOS auto detect connector type + UNUSED_PTYPE, // UnusedType + MAX_CONNECTOR_TYPE // Not valid value, used to verify input +} pcie_connector_type; + +/* DDI Descriptor: used for configuring display outputs */ +typedef struct __packed { + uint8_t connector_type; + uint8_t aux_index; + uint8_t hdp_index; + uint8_t reserved; +} fsp_ddi_descriptor; + +/* PCIe Descriptor: used for assigning lanes, bifurcation and other settings */ +typedef struct __packed { + uint8_t engine_type; + uint8_t start_lane; // Start lane of the pci device + uint8_t end_lane; // End lane of the pci device + uint8_t gpio_group_id; // FCH reset number. 0 is global reset + unsigned int port_present:1; // Should be TRUE if train link + unsigned int reserved_3:7; + unsigned int device_number:5; // Desired root port device number + unsigned int function_number:3; // Desired root port function number + unsigned int link_speed_capability:2; + unsigned int auto_spd_change:2; + unsigned int eq_preset:4; + unsigned int link_aspm:2; + unsigned int link_aspm_L1_1:1; + unsigned int link_aspm_L1_2:1; + unsigned int clk_req:4; + uint8_t link_hotplug; + uint8_t slot_power_limit; + unsigned int slot_power_limit_scale:2; + unsigned int reserved_4:6; + unsigned int link_compliance_mode:1; + unsigned int link_safe_mode:1; + unsigned int sb_link:1; + unsigned int clk_pm_support:1; + unsigned int channel_type:3; + unsigned int turn_off_unused_lanes:1; + uint8_t reserved[4]; +} fsp_pcie_descriptor; + +#endif /* __PI_PICASSO_PLATFORM_DESCRIPTORS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38698 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa4d81a0f2909cb66e551e34e1f3fa4725560d60 Gerrit-Change-Number: 38698 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

6 12

Change in coreboot[master]: mb/*/*/gpio: Remove null-initialized members
by Peter Lemenkov (Code Review) 27 Mar '20

27 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35900 ) Change subject: mb/*/*/gpio: Remove null-initialized members ...................................................................... mb/*/*/gpio: Remove null-initialized members Made with this oneliner: $ find src/mainboard/ -type f -name gpio.c -print -exec sed -i -e '/^\s*.gpio[0-9]\+\s*=\s*$GPIO_MODE_NATIVE\|GPIO_DIR_OUTPUT\|GPIO_NO_INVERT\|GPIO_LEVEL_LOW\|GPIO_NO_BLINK\|GPIO_RESET_PWROK$\s*$/d' {} \; It didn't touch lines with comments. Change-Id: I2799293585bcfcf41c93a9dbe358cd806f9374f5 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/apple/macbook21/gpio.c M src/mainboard/apple/macbookair4_2/gpio.c M src/mainboard/asrock/b75pro3-m/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41c-gs/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-gs/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-s3/gpio.c M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/gpio.c M src/mainboard/asrock/h81m-hds/gpio.c M src/mainboard/asus/h61m-cs/gpio.c M src/mainboard/asus/maximus_iv_gene-z/gpio.c M src/mainboard/asus/p5gc-mx/gpio.c M src/mainboard/asus/p5qc/gpio.c M src/mainboard/asus/p5qc/variants/p5ql_pro/gpio.c M src/mainboard/asus/p5qpl-am/variants/p5g41t-m_lx/gpio.c M src/mainboard/asus/p5qpl-am/variants/p5qpl-am/gpio.c M src/mainboard/asus/p8h61-m_lx/gpio.c M src/mainboard/asus/p8h61-m_pro/gpio.c M src/mainboard/asus/p8z77-m_pro/gpio.c M src/mainboard/compulab/intense_pc/gpio.c M src/mainboard/foxconn/d41s/gpio.c M src/mainboard/foxconn/g41s-k/gpio.c M src/mainboard/getac/p470/gpio.c M src/mainboard/gigabyte/ga-945gcm-s2l/gpio.c M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3h/gpio.c M src/mainboard/gigabyte/ga-b75m-d3h/variants/ga-b75m-d3v/gpio.c M src/mainboard/gigabyte/ga-g41m-es2l/gpio.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c M src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c M src/mainboard/google/link/gpio.c M src/mainboard/google/parrot/gpio.c M src/mainboard/google/stout/gpio.c M src/mainboard/hp/2570p/gpio.c M src/mainboard/hp/2760p/gpio.c M src/mainboard/hp/8460p/gpio.c M src/mainboard/hp/8470p/gpio.c M src/mainboard/hp/8770w/gpio.c M src/mainboard/hp/compaq_8200_elite_sff/gpio.c M src/mainboard/hp/folio_9470m/gpio.c M src/mainboard/hp/revolve_810_g1/gpio.c M src/mainboard/hp/z220_sff_workstation/gpio.c M src/mainboard/ibase/mb899/gpio.c M src/mainboard/intel/d510mo/gpio.c M src/mainboard/intel/d945gclf/gpio.c M src/mainboard/intel/dcp847ske/gpio.c M src/mainboard/intel/dg41wv/gpio.c M src/mainboard/intel/dg43gt/gpio.c M src/mainboard/kontron/986lcd-m/gpio.c M src/mainboard/lenovo/l520/gpio.c M src/mainboard/lenovo/s230u/gpio.c M src/mainboard/lenovo/t400/variants/r500/gpio.c M src/mainboard/lenovo/t400/variants/t400/gpio.c M src/mainboard/lenovo/t420/gpio.c M src/mainboard/lenovo/t420s/gpio.c M src/mainboard/lenovo/t430s/variants/t430s/gpio.c M src/mainboard/lenovo/t430s/variants/t431s/gpio.c M src/mainboard/lenovo/t520/variants/t520/gpio.c M src/mainboard/lenovo/t520/variants/w520/gpio.c M src/mainboard/lenovo/t530/variants/t530/gpio.c M src/mainboard/lenovo/t530/variants/w530/gpio.c M src/mainboard/lenovo/t60/gpio.c M src/mainboard/lenovo/thinkcentre_a58/gpio.c M src/mainboard/lenovo/x131e/gpio.c M src/mainboard/lenovo/x1_carbon_gen1/gpio.c M src/mainboard/lenovo/x200/gpio.c M src/mainboard/lenovo/x201/gpio.c M src/mainboard/lenovo/x220/variants/x1/gpio.c M src/mainboard/lenovo/x220/variants/x220/gpio.c M src/mainboard/lenovo/x230/gpio.c M src/mainboard/lenovo/x60/gpio.c M src/mainboard/msi/ms7707/gpio.c M src/mainboard/packardbell/ms2290/gpio.c M src/mainboard/roda/rk886ex/gpio.c M src/mainboard/roda/rk9/gpio.c M src/mainboard/roda/rv11/gpio.c M src/mainboard/samsung/lumpy/gpio.c M src/mainboard/samsung/stumpy/gpio.c M src/mainboard/sapphire/pureplatinumh61/gpio.c M src/mainboard/supermicro/x10slm-f/gpio.c 79 files changed, 0 insertions(+), 4,228 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35900/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/35900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2799293585bcfcf41c93a9dbe358cd806f9374f5 Gerrit-Change-Number: 35900 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: libgfxinit: Allow to override screen rotation via CMOS option
by Nico Huber (Code Review) 27 Mar '20

27 Mar '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38924 ) Change subject: libgfxinit: Allow to override screen rotation via CMOS option ...................................................................... libgfxinit: Allow to override screen rotation via CMOS option Change-Id: I30a0aca6b7f79b1bbd96b7f527b896885affc77d Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/drivers/intel/gma/hires_fb/gma-gfx_init.adb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/38924/1 diff --git a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb index 014e92b..40ed0c3 100644 --- a/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb +++ b/src/drivers/intel/gma/hires_fb/gma-gfx_init.adb @@ -1,4 +1,5 @@ with CB.Config; +with CB.NVRAM; use CB; @@ -56,12 +57,19 @@ procedure Screen_Rotation (rotation : out Rotation_Type) is + use type word8; + raw_rotation : word8 := 255; begin rotation := (if Config.DEFAULT_SCREEN_ROTATION_90 then Rotated_90 elsif Config.DEFAULT_SCREEN_ROTATION_180 then Rotated_180 elsif Config.DEFAULT_SCREEN_ROTATION_270 then Rotated_270 else No_Rotation); + + NVRAM.get_option (raw_rotation, "screen_rotation"); + if raw_rotation <= Rotation_Type'pos (Rotation_Type'last) then + rotation := Rotation_Type'val (raw_rotation); + end if; end Screen_Rotation; procedure gfxinit (lightup_ok : out Interfaces.C.int) -- To view, visit https://review.coreboot.org/c/coreboot/+/38924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30a0aca6b7f79b1bbd96b7f527b896885affc77d Gerrit-Change-Number: 38924 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: G505S dGPU support: scripts for applying the unofficial (not-merged-y...
by Mike Banon (Code Review) 27 Mar '20

27 Mar '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33874 Change subject: G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches ...................................................................... G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches These scripts will help you to securely and conveniently apply two changes CB:31448 and CB:31450 to add the discrete GPU support for AMD Lenovo G505S. Save to ./coreboot/ then run ./get_dgpu_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/31448 src/device/pci: Add support for discrete VGA initialization and OpROM loading https://review.coreboot.org/c/coreboot/+/31450 lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2452a75d425f8f647e81314111c462d1195d595d --- A apply_dgpu_patches.sh A check_dgpu_patches.sh A get_dgpu_patches.sh A sha256sums_dgpu_correct.txt 4 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33874/1 diff --git a/apply_dgpu_patches.sh b/apply_dgpu_patches.sh new file mode 100755 index 0000000..aca4adb --- /dev/null +++ b/apply_dgpu_patches.sh @@ -0,0 +1,12 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +patch -p1 < "./b7d4266.diff" +### diff --git a/check_dgpu_patches.sh b/check_dgpu_patches.sh new file mode 100755 index 0000000..6137cc4 --- /dev/null +++ b/check_dgpu_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_dgpu_my.txt" +sha256sum "./8e35cfe.diff" > "./sha256sums_dgpu_my.txt" +sha256sum "./b7d4266.diff" >> "./sha256sums_dgpu_my.txt" +if cmp -s "./sha256sums_dgpu_my.txt" "./sha256sums_dgpu_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_dgpu_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_dgpu_my.txt and ./sha256sums_dgpu_correct.txt" + exit 1 +fi +# diff --git a/get_dgpu_patches.sh b/get_dgpu_patches.sh new file mode 100755 index 0000000..e0d4a2a --- /dev/null +++ b/get_dgpu_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/31448 +### src/device/pci: Add support for discrete VGA initialization and OpROM loading +### +rm -f "./8e35cfe.diff" +wget "https://review.coreboot.org/changes/31448/revisions/17/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./8e35cfe.diff" +### +### https://review.coreboot.org/c/coreboot/+/31450 +### lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop +### +rm -f "./b7d4266.diff" +wget "https://review.coreboot.org/changes/31450/revisions/12/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./b7d4266.diff" +### diff --git a/sha256sums_dgpu_correct.txt b/sha256sums_dgpu_correct.txt new file mode 100644 index 0000000..b607b61 --- /dev/null +++ b/sha256sums_dgpu_correct.txt @@ -0,0 +1,2 @@ +284cb0908c498c730dd8ed994c65ffd186d1dd34b4bc3432c9e7ccf7f40313e2 ./8e35cfe.diff +0edfa4f1bb2310220f0d6be2228f0be15d2ab0256e63fa1ed6fecc1650e1f938 ./b7d4266.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/33874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2452a75d425f8f647e81314111c462d1195d595d Gerrit-Change-Number: 33874 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 6

Change in coreboot[master]: mb/google/sarien: Modify Melfas touchscreen reset delay
by Ivy Jian (Code Review) 27 Mar '20

27 Mar '20

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34162 ) Change subject: mb/google/sarien: Modify Melfas touchscreen reset delay ...................................................................... mb/google/sarien: Modify Melfas touchscreen reset delay Modify reset_delay_ms as 115ms to waiting for Melfas device I2C interface ready after touch fw AU and rebind driver. BUG=b:136560969 BRANCH=sarien TEST=Touchscreen works fine after touch FW auto updated. Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Signed-off-by: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34162/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 739a849..53189ce 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -343,7 +343,7 @@ register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" - register "reset_delay_ms" = "10" + register "reset_delay_ms" = "115" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "enable_delay_ms" = "55" register "has_power_resource" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/34162 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45bd93bb841c7dd49705a9d6b61cb9f66f7d7bcb Gerrit-Change-Number: 34162 Gerrit-PatchSet: 1 Gerrit-Owner: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020