coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: soc/amd/picasso: Add basic MTRR settings to hybrid romstage
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35297 ) Change subject: soc/amd/picasso: Add basic MTRR settings to hybrid romstage ...................................................................... soc/amd/picasso: Add basic MTRR settings to hybrid romstage Program the system flash as WP to allow it to be cacheable. This was done during bootblock on previous systems. Since this code and its data are in DRAM, set them to WP. Prior to running ramstage, set its anticipated target location as WP also. Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/romstage.c 2 files changed, 75 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/35297/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 66e6650..15f319f 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -25,8 +25,18 @@ #define ROMSTAGE_SIZE (64 * KiB) /* Enforced by Makefile.inc for PSP info */ #define ROMSTAGE_TOP (CONFIG_ROMSTAGE_ADDR + ROMSTAGE_SIZE) +#define EARLYRAM_TOP (ROMSTAGE_TOP + CONFIG_EARLYRAM_SIZE) #if ROMSTAGE_TOP & 0xffff # error Top of the BIOS binary image must be 64KB aligned #endif +#define EARLY_DRAM_MTRR_BASE \ + ALIGN_DOWN(CONFIG_ROMSTAGE_ADDR, 32 * MiB) +#define EARLY_DRAM_MTRR_SIZE \ + ALIGN_UP(ROMSTAGE_SIZE + CONFIG_EARLYRAM_SIZE, 32 * MiB) +#define EARLY_DRAM_MTRR_TOP \ + (EARLY_DRAM_MTRR_BASE + EARLY_DRAM_MTRR_SIZE) + +#define EARLY_RAMSTAGE_MTRR_SZ (16 * MiB) + #endif /* __PICASSO_CPU_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 92361f9..b4c8013 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -21,8 +21,10 @@ #include <delay.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <cpu/x86/bist.h> +#include <cpu/amd/mtrr.h> #include <cpu/amd/msr.h> #include <cbmem.h> #include <console/console.h> @@ -56,10 +58,68 @@ fch_early_init(); } +static int set_early_mtrrs(void) +{ + int mtrr; + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, EARLY_DRAM_MTRR_BASE, EARLY_DRAM_MTRR_SIZE, + MTRR_TYPE_WRBACK); + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return 1; + + set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, + MTRR_TYPE_WRPROT); + return 0; +} + +static void set_mtrrs_for_ramstage(void) +{ + uintptr_t smm_base; + size_t smm_size; + uintptr_t smm_top; + uintptr_t mem_top; + uintptr_t ramstage_wb_base; + size_t ramstage_wb_size; + int mtrr; + + smm_region(&smm_base, &smm_size); + smm_top = smm_base + smm_size; + + mem_top = (uintptr_t)cbmem_top(); + + /* Cache anticipated ramstage location through the top of TSEG */ + ramstage_wb_base = mem_top - EARLY_RAMSTAGE_MTRR_SZ; + ramstage_wb_size = smm_top - ramstage_wb_base; + + /* Make sure MTRR base and size are usable */ + if (ramstage_wb_size != 1 << fms(ramstage_wb_size)) { + ramstage_wb_size = 1 << (1 + fms(ramstage_wb_size)); + ramstage_wb_base = smm_top - ramstage_wb_size; + } + if (mem_top - EARLY_RAMSTAGE_MTRR_SZ < EARLY_DRAM_MTRR_TOP) { + printk(BIOS_WARNING, "Warning: Skipping ramstage cacheable due to configuration\n"); + return; + } + + mtrr = get_free_var_mtrr(); + if (mtrr >= 0) + set_var_mtrr(mtrr, ramstage_wb_base, ramstage_wb_size, + MTRR_TYPE_WRBACK); + else + printk(BIOS_WARNING, "Warning: Unable to make ramstage cacheable\n"); +} + asmlinkage void soc_hybrid_romstage_entry(uint32_t bist, uint64_t early_tsc) { uintptr_t top_of_mem; int s3_resume; + int early_mtrr_err; post_code(0x40); if (CONFIG(COLLECT_TIMESTAMPS)) { @@ -70,6 +130,7 @@ /* Many of these tasks typically happen in bootblock, but execution * begins in romstage for this device. */ post_code(0x41); + early_mtrr_err = set_early_mtrrs(); post_code(0x42); romstage_soc_early_init(); @@ -96,6 +157,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + if (early_mtrr_err) + printk(BIOS_WARNING, "Early MTRRs were not set properly\n"); + post_code(0x48); if (!s3_resume && CONFIG(ELOG_BOOT_COUNT)) boot_count_increment(); @@ -111,6 +175,7 @@ printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x4b); + set_mtrrs_for_ramstage(); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73222097a6a859827c4f91851ab55300cb0d9dcc Gerrit-Change-Number: 35297 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM
by Marshall Dawson (Code Review) 04 Apr '20

04 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37491 ) Change subject: x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM ...................................................................... x86: Implement a romstage-only version of RESET_VECTOR_IN_RAM In continuing the flexibility of RESET_VECTOR_IN_RAM, add Kconfig options for declaring whether the first stage of execution is bootblock or romstage. For the romstage version, rely on the existing x86 reset vector handling and initialization, as well as assembly_entry.S (previously intended only to reinitialize the x86's basic settings in early stages). Add a new function to be called earlyram_stage_entry() that transmits the BIST information to be checked. Adjust linker scripts accordingly. Note that flipping the default build to a hybrid romstage arrangement is intentional. Implementations intending to use a traditional bootblock should select RESET_VECTOR_IN_RAM_BOOTBLOCK. Sample build using amd/mandolin (currently WIP): Name Offset Type Size Comp cbfs master header 0x0 cbfs header 32 none fallback/ramstage 0x80 stage 76100 none config 0x12a00 raw 364 none revision 0x12bc0 raw 674 none payload_config 0x12ec0 raw 1593 none payload_revision 0x13540 raw 262 none (empty) 0x136c0 null 1752 none fspm.bin 0x13dc0 fsp 786432 none (empty) 0xd3e00 null 3992 none fsps.bin 0xd4dc0 fsp 262144 none pci1002,15d8.rom 0x114e00 optionrom 54272 none fallback/dsdt.aml 0x122280 raw 8365 none fallback/payload 0x124380 simple elf 68099 none (empty) 0x134dc0 null 2928536 none bootblock 0x3ffd80 bootblock 64 none readelf of build/cbfs/fallback/romstage.elf: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 [ 1] .text PROGBITS 08000000 001000 007c20 00 AX 0 0 32 [ 2] .rel.text REL 00000000 0838f4 001ac0 08 I 9 1 4 [ 3] .earlyram.data NOBITS 0802d000 008c20 045ed8 00 WA 0 0 32 [ 4] .near_reset_vecto PROGBITS 0807f000 080000 0000c8 00 AX 0 0 4096 [ 5] .rel.near_reset_v REL 00000000 0853b4 000058 08 I 9 4 4 [ 6] .reset PROGBITS 0807fff0 080ff0 000010 00 AX 0 0 1 [ 7] .rel.reset REL 00000000 08540c 000008 08 I 9 6 4 [ 8] .gnu_debuglink PROGBITS 00000000 081000 000014 00 0 0 4 [ 9] .symtab SYMTAB 00000000 081014 001590 10 10 122 4 [10] .strtab STRTAB 00000000 0825a4 001350 00 0 0 1 [11] .shstrtab STRTAB 00000000 085414 000065 00 0 0 1 167: 0802d000 0 NOTYPE GLOBAL DEFAULT 3 _earlyram_stack 134: 0802d800 0 NOTYPE GLOBAL DEFAULT 3 _eearlyram_stack 274: 0802d800 0 NOTYPE GLOBAL DEFAULT 3 _preram_cbmem_console 310: 0802ee00 0 NOTYPE GLOBAL DEFAULT 3 _epreram_cbmem_console 202: 0802ee00 0 NOTYPE GLOBAL DEFAULT 3 _timestamp 335: 0802f000 0 NOTYPE GLOBAL DEFAULT 3 _etimestamp 244: 0802f000 0 NOTYPE GLOBAL DEFAULT 3 _bss 216: 08072ed8 0 NOTYPE GLOBAL DEFAULT 3 _ebss Change-Id: Ida2bc90fdd3e953445065929124adaa168164250 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M Makefile.inc M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc M src/arch/x86/assembly_entry.S M src/arch/x86/include/arch/cpu.h M src/arch/x86/memlayout.ld M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/reset16.ld M src/cpu/x86/32bit/entry32.inc 9 files changed, 57 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/37491/1 diff --git a/Makefile.inc b/Makefile.inc index e4defc1..6a11ae8 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1153,6 +1153,8 @@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifneq ($(CONFIG_RESET_VECTOR_IN_RAM_ROMSTAGE),y) + cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-type := stage @@ -1192,6 +1194,7 @@ ifeq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) $(CONFIG_CBFS_PREFIX)/romstage-options += $(TXTIBB) endif +endif # !CONFIG_RESET_VECTOR_IN_RAM_ROMSTAGE cbfs-files-$(CONFIG_HAVE_RAMSTAGE) += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(RAMSTAGE) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 0547193..467dbf2 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -106,6 +106,23 @@ The first stage executed may be a bootblock, or a hybrid romstage, combining certain elements of bootblock and romstage. +config RESET_VECTOR_IN_RAM_BOOTBLOCK + bool + depends on RESET_VECTOR_IN_RAM + select HAVE_BOOTBLOCK + help + Build a traditional bootblock that begins execution in RAM. This + implementation uses a C environment, and romcc is not supported. + +config RESET_VECTOR_IN_RAM_ROMSTAGE + bool + depends on RESET_VECTOR_IN_RAM + default !RESET_VECTOR_IN_RAM_BOOTBLOCK + help + Build a hybrid romstage, combining the bootblock operations of + bringing the x86 online and setting flat protected mode, with the + romstage operations of determining memory setup and bring up cbmem. + # Aligns 16bit entry code in bootblock so that hyper-threading CPUs # can boot AP CPUs to enable their shared caches. config SIPI_VECTOR_IN_ROM diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 423c351..973ef65 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -224,8 +224,10 @@ # gdt_init.S is included by entry32.inc when romstage is the first C # environment. ifneq ($(CONFIG_ROMCC_BOOTBLOCK),y) +ifneq ($(CONFIG_RESET_VECTOR_IN_RAM_ROMSTAGE),y) romstage-y += gdt_init.S endif +endif romstage-y += cbmem.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += exception.c romstage-$(CONFIG_IDT_IN_EVERY_STAGE) += idt.S diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 273045a..56f18f8 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -28,12 +28,19 @@ #define _STACK_TOP _ecar_stack #endif -.section ".text._start", "ax", @progbits -.global _start -_start: +#if CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) + #include <arch/x86/prologue.inc> + #include <cpu/x86/16bit/entry16.inc> + #include <cpu/x86/16bit/reset16.inc> /* includes _start symbol */ + #include <cpu/x86/32bit/entry32.inc> /* includes gdt_init */ +#else + .section ".text._start", "ax", @progbits + .global _start + _start: /* Migrate GDT to this text segment */ call gdt_init +#endif /* reset stack pointer to CAR stack */ mov $_STACK_TOP, %esp @@ -62,7 +69,14 @@ #if CONFIG(IDT_IN_EVERY_STAGE) call exception_init #endif + +#if CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) + subl $12, %esp + pushl %ebp /* BIST value */ + call earlyram_stage_entry +#else call car_stage_entry +#endif /* Expect to never return. */ 1: diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 50d636b..22fcce8 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -293,6 +293,13 @@ */ asmlinkage void car_stage_entry(void); +/* + * A system using RESET_VECTOR_IN_RAM_ROMSTAGE eliminates bootblock and calls + * earlyram_stage_entry() as the platform's entry point. + * entry point. + */ +asmlinkage void earlyram_stage_entry(uint32_t bist); + #endif /* diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index 978925f..b7a1891 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -60,12 +60,14 @@ #endif } -#if ENV_BOOTBLOCK +#if (ENV_BOOTBLOCK || (CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) && ENV_ROMSTAGE)) /* Bootblock specific scripts which provide more SECTION directives. */ #include <cpu/x86/16bit/entry16.ld> #include <cpu/x86/16bit/reset16.ld> +#if ENV_BOOTBLOCK #include <arch/x86/id.ld> +#endif #if CONFIG(CPU_INTEL_FIRMWARE_INTERFACE_TABLE) #include <cpu/intel/fit/fit.ld> #endif -#endif /* ENV_BOOTBLOCK */ +#endif /* ENV_BOOTBLOCK || (CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE) && ENV_ROMSTAGE) */ diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2aa8240..0dca67e 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,7 +29,8 @@ #include <arch/rom_segs.h> -#if (!CONFIG(ROMCC_BOOTBLOCK) && CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000) +#if ((!CONFIG(ROMCC_BOOTBLOCK) && (CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000)) \ + || CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE)) .section ".near_reset_vector", "ax", @progbits #endif diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index 28893c6..4c4bdcb 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -14,7 +14,8 @@ /* _RESET_VECTOR: typically the top of the ROM */ SECTIONS { -#if (!CONFIG(ROMCC_BOOTBLOCK) && CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000) +#if ((!CONFIG(ROMCC_BOOTBLOCK) && (CONFIG_C_ENV_BOOTBLOCK_SIZE > 0x10000)) \ + || CONFIG(RESET_VECTOR_IN_RAM_ROMSTAGE)) /* Trigger an error if I have an unuseable start address */ _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 52c0768..7f60ca5 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -13,6 +13,8 @@ /* For starting coreboot in protected mode */ +#define _START_IN_ENTRY32 (!ENV_BOOTBLOCK && !CONFIG(RESET_VECTOR_IN_RAM)) + #include <arch/rom_segs.h> #include <cpu/x86/post_code.h> #include <arch/x86/gdt_init.S> @@ -35,7 +37,7 @@ * expose the _start symbol for bootblock. */ .align 4 -#if !ENV_BOOTBLOCK +#if _START_IN_ENTRY32 .globl _start _start: #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/37491 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida2bc90fdd3e953445065929124adaa168164250 Gerrit-Change-Number: 37491 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: Add Intel SkyLake Scalable Processor support
by Jonathan Zhang (Code Review) 03 Apr '20

03 Apr '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38548 ) Change subject: Add Intel SkyLake Scalable Processor support ...................................................................... Add Intel SkyLake Scalable Processor support This patch set adds support for Intel skylake-sp. This SOC belongs to Xeon Scalable Processor family. The skylake-sp FSP is based on FSP 2.0. It is an engineering build that will not be shared in public, at least for the time being. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Reddy Chagam <anjaneya.chagam(a)intel.com> Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/Kconfig A src/soc/intel/skylake_sp/Kconfig A src/soc/intel/skylake_sp/Makefile.inc A src/soc/intel/skylake_sp/acpi.c A src/soc/intel/skylake_sp/acpi/globalnvs.asl A src/soc/intel/skylake_sp/acpi/iiostack.asl A src/soc/intel/skylake_sp/acpi/pci_irq.asl A src/soc/intel/skylake_sp/acpi/uncore.asl A src/soc/intel/skylake_sp/acpi/uncore_irq.asl A src/soc/intel/skylake_sp/bootblock/bootblock.c A src/soc/intel/skylake_sp/chip.c A src/soc/intel/skylake_sp/chip.h A src/soc/intel/skylake_sp/cpu.c A src/soc/intel/skylake_sp/hob_display.c A src/soc/intel/skylake_sp/include/soc/acpi.h A src/soc/intel/skylake_sp/include/soc/bootblock.h A src/soc/intel/skylake_sp/include/soc/cpu.h A src/soc/intel/skylake_sp/include/soc/gpe.h A src/soc/intel/skylake_sp/include/soc/gpio_fsp.h A src/soc/intel/skylake_sp/include/soc/gpio_soc_defs.h A src/soc/intel/skylake_sp/include/soc/hob_iiouds.h A src/soc/intel/skylake_sp/include/soc/hob_memmap.h A src/soc/intel/skylake_sp/include/soc/iomap.h A src/soc/intel/skylake_sp/include/soc/irq.h A src/soc/intel/skylake_sp/include/soc/itss.h A src/soc/intel/skylake_sp/include/soc/msr.h A src/soc/intel/skylake_sp/include/soc/nvs.h A src/soc/intel/skylake_sp/include/soc/p2sb.h A src/soc/intel/skylake_sp/include/soc/pci_devs.h A src/soc/intel/skylake_sp/include/soc/pcr_ids.h A src/soc/intel/skylake_sp/include/soc/pm.h A src/soc/intel/skylake_sp/include/soc/pmc.h A src/soc/intel/skylake_sp/include/soc/ramstage.h A src/soc/intel/skylake_sp/include/soc/romstage.h A src/soc/intel/skylake_sp/include/soc/smbus.h A src/soc/intel/skylake_sp/include/soc/soc_config.h A src/soc/intel/skylake_sp/include/soc/soc_util.h A src/soc/intel/skylake_sp/lpc.c A src/soc/intel/skylake_sp/reset.c A src/soc/intel/skylake_sp/romstage.c A src/soc/intel/skylake_sp/smihandler.c A src/soc/intel/skylake_sp/soc_util.c A src/soc/intel/skylake_sp/spi.c A src/soc/intel/skylake_sp/uncore.c A src/soc/intel/skylake_sp/upd_display.c 46 files changed, 8,799 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/38548/1 -- To view, visit https://review.coreboot.org/c/coreboot/+/38548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc9c3bee17caf8b4841f0bc190cb1aa9d38fc23e Gerrit-Change-Number: 38548 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

14 133

Change in coreboot[master]: security/vboot: Decouple measured boot from verified boot
by Bill XIE (Code Review) 31 Mar '20

31 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35077 ) Change subject: security/vboot: Decouple measured boot from verified boot ...................................................................... security/vboot: Decouple measured boot from verified boot As said in CB:34977, currently TPM and CRTM are initialized just before romstage loads a file within CBFS, or initialized in vboot_logic() if CONFIG_VBOOT is set. Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/lib/cbfs.c M src/security/tpm/Makefile.inc M src/security/tpm/tspi/tspi.c M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc M src/security/vboot/misc.h M src/security/vboot/vboot_crtm.c M src/security/vboot/vboot_crtm.h 8 files changed, 136 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/35077/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..246e741 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -327,6 +327,9 @@ * devices. */ const struct cbfs_locator __weak cbfs_master_header_locator = { .name = "Master Header Locator", +#if !CONFIG(VBOOT) && CONFIG(VBOOT_MEASURED_BOOT) + .prepare = measured_boot_init_crtm, +#endif .locate = cbfs_master_header_props, }; diff --git a/src/security/tpm/Makefile.inc b/src/security/tpm/Makefile.inc index a2d32cf..cb936cf 100644 --- a/src/security/tpm/Makefile.inc +++ b/src/security/tpm/Makefile.inc @@ -8,7 +8,10 @@ romstage-y += tss/tcg-1.2/tss.c verstage-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c -postcar-$(CONFIG_VBOOT) += tss/tcg-1.2/tss.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tss/tcg-1.2/tss.c +endif ## TSPI @@ -16,7 +19,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c @@ -45,7 +51,10 @@ romstage-y += tspi/tspi.c verstage-$(CONFIG_VBOOT) += tspi/tspi.c -postcar-$(CONFIG_VBOOT) += tspi/tspi.c + +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) +postcar-y += tspi/tspi.c +endif ramstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c romstage-$(CONFIG_VBOOT_MEASURED_BOOT) += tspi/log.c diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..36dd3dd 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -20,7 +20,7 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <stdlib.h> -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) #include <vb2_api.h> #include <vb2_sha.h> #include <assert.h> @@ -220,7 +220,7 @@ return TPM_SUCCESS; } -#if CONFIG(VBOOT) +#if CONFIG(VBOOT) || CONFIG(VBOOT_MEASURED_BOOT) uint32_t tpm_measure_region(const struct region_device *rdev, uint8_t pcr, const char *rname) { @@ -279,4 +279,4 @@ printk(BIOS_DEBUG, "TPM: Measured %s into PCR %d\n", rname, pcr); return TPM_SUCCESS; } -#endif /* VBOOT */ +#endif /* VBOOT || VBOOT_MEASURED_BOOT */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index c5146c6..955e8a6 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -menu "Verified Boot (vboot)" +menu "vboot functionalities" config VBOOT bool "Verify firmware with vboot." @@ -21,21 +21,17 @@ select VBOOT_MOCK_SECDATA if !TPM1 && !TPM2 depends on !MISSING_BOARD_RESET help - Enabling VBOOT will use vboot to verify the components of the firmware + Enabling verified voot will use vboot to verify the components of the firmware (stages, payload, etc). -if VBOOT - -comment "Anti-Rollback Protection disabled because mocking secdata is enabled." - depends on VBOOT_MOCK_SECDATA - config VBOOT_MEASURED_BOOT - bool "Enable Measured Boot" + bool "Measure firmware components with vboot." default n depends on TPM1 || TPM2 depends on !VBOOT_RETURN_FROM_VERSTAGE help - Enables measured boot mode in vboot (experimental) + Enables measured boot will use vboot to measure the components of the firmware + (stages, payload, etc) to PCRs within TPM. (experimental) config VBOOT_MEASURED_BOOT_RUNTIME_DATA string "Runtime data whitelist" @@ -45,6 +41,13 @@ Runtime data whitelist of cbfs filenames. Needs to be a comma separated list +if VBOOT + +comment "Anti-Rollback Protection disabled because mocking secdata is enabled." + depends on VBOOT_MOCK_SECDATA + +comment "A non-trivial fmd file with sections required by vboot is needed." + config VBOOT_SLOTS_RW_A bool "Firmware RO + RW_A" help diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index d554f10..0729d9f 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -14,6 +14,58 @@ ## GNU General Public License for more details. ## +ifneq ($(CONFIG_VBOOT_MEASURED_BOOT)$(CONFIG_VBOOT),) + +ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) +verstage-y += tpm_common.c +endif + + +vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ + $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ + $(filter-out -I$(obj),$(1)))) + +# call with $1 = stage name to create rules for building the library +# for the stage and adding it to the stage's set of object files. +define vboot-for-stage +VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) +VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) +VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) +VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes +VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG + +$$(VB2_LIB_$(1)): $(obj)/config.h + printf " MAKE $(subst $(obj)/,,$(@))\n" + +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ + CC="$$(CC_$(1))" \ + CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ + $(MAKE) -C $(VBOOT_SOURCE) \ + BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ + V=$(V) \ + fwlib20 + +$(1)-srcs += $$(VB2_LIB_$(1)) + +endef # vboot-for-stage + +CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include + +$(eval $(call vboot-for-stage,bootblock)) +$(eval $(call vboot-for-stage,romstage)) +$(eval $(call vboot-for-stage,ramstage)) +$(eval $(call vboot-for-stage,postcar)) + +endif # CONFIG_VBOOT_MEASURED_BOOT || CONFIG_VBOOT + +ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) +bootblock-y += vboot_crtm.c +verstage-y += vboot_crtm.c +romstage-y += vboot_crtm.c +ramstage-y += vboot_crtm.c +postcar-y += vboot_crtm.c +endif # CONFIG_VBOOT_MEASURED_BOOT + ifeq ($(CONFIG_VBOOT),y) bootblock-y += bootmode.c @@ -22,6 +74,12 @@ verstage-y += bootmode.c postcar-y += bootmode.c +bootblock-y += vboot_common.c +verstage-y += vboot_common.c +romstage-y += vboot_common.c +ramstage-y += vboot_common.c +postcar-y += vboot_common.c + # When VBOOT_STARTS_IN_ROMSTAGE is selected, DRAM is already up by # the time verstage runs. ifneq ($(CONFIG_VBOOT_STARTS_IN_ROMSTAGE),y) @@ -63,19 +121,7 @@ verstage-y += vboot_loader.c postcar-y += vboot_loader.c -bootblock-y += vboot_common.c -verstage-y += vboot_common.c -romstage-y += vboot_common.c -ramstage-y += vboot_common.c -postcar-y += vboot_common.c -ifeq ($(CONFIG_VBOOT_MEASURED_BOOT),y) -bootblock-y += vboot_crtm.c -verstage-y += vboot_crtm.c -romstage-y += vboot_crtm.c -ramstage-y += vboot_crtm.c -postcar-y += vboot_crtm.c -endif bootblock-y += common.c verstage-y += vboot_logic.c @@ -89,10 +135,6 @@ romstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += secdata_tpm.c endif -ifneq ($(CONFIG_TPM1)$(CONFIG_TPM2),) -verstage-y += tpm_common.c -endif - romstage-y += vboot_logic.c romstage-y += common.c @@ -101,41 +143,6 @@ romstage-$(CONFIG_FSP2_0_USES_TPM_MRC_HASH) += mrc_cache_hash_tpm.c -vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ - $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ - $(filter-out -I$(obj),$(1)))) - -# call with $1 = stage name to create rules for building the library -# for the stage and adding it to the stage's set of object files. -define vboot-for-stage -VB2_LIB_$(1) = $(obj)/external/vboot_reference-$(1)/vboot_fw20.a -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$(CPPFLAGS_$(1))) -VBOOT_CFLAGS_$(1) += $$(CFLAGS_$(1)) -VBOOT_CFLAGS_$(1) += $$(call vboot-fixup-includes,$$($(1)-c-ccopts)) -VBOOT_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes -VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG - -$$(VB2_LIB_$(1)): $(obj)/config.h - printf " MAKE $(subst $(obj)/,,$(@))\n" - +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ - CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ - $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$$(abspath $$(dir $$(VB2_LIB_$(1)))) \ - V=$(V) \ - fwlib20 - -$(1)-srcs += $$(VB2_LIB_$(1)) - -endef # vboot-for-stage - -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include - -$(eval $(call vboot-for-stage,bootblock)) -$(eval $(call vboot-for-stage,romstage)) -$(eval $(call vboot-for-stage,ramstage)) -$(eval $(call vboot-for-stage,postcar)) - ifeq ($(CONFIG_VBOOT_SEPARATE_VERSTAGE),y) $(eval $(call vboot-for-stage,verstage)) diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index 725f5fd..8761b84 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -127,5 +127,21 @@ } } +static inline int vboot_crtm_is_set(void) +{ + extern int crtm_is_set; + if (CONFIG(VBOOT)) { + return vboot_logic_executed(); + } else if(ENV_ROMSTAGE) { + return car_get_var(crtm_is_set); + } else { +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } +} + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_crtm.c b/src/security/vboot/vboot_crtm.c index e4266b2..92f05e5 100644 --- a/src/security/vboot/vboot_crtm.c +++ b/src/security/vboot/vboot_crtm.c @@ -19,11 +19,13 @@ #include <security/vboot/vboot_crtm.h> #include <security/vboot/misc.h> #include <string.h> +#include <timestamp.h> /* * This functions sets the TCPA log namespace * for the cbfs file (region) lookup. */ + static int create_tcpa_metadata(const struct region_device *rdev, const char *cbfs_name, char log_string[TCPA_PCR_HASH_NAME]) { @@ -90,7 +92,8 @@ } } - if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE) || + CONFIG(VBOOT_MEASURED_BOOT)) { struct cbfsf romstage_data; /* measure romstage from RO */ if (cbfs_boot_locate(&romstage_data, @@ -164,7 +167,7 @@ struct region_device rdev; char tcpa_metadata[TCPA_PCR_HASH_NAME]; - if (!vboot_logic_executed()) + if (!vboot_crtm_is_set()) return 0; cbfsf_file_type(fh, &cbfs_type); @@ -193,3 +196,26 @@ return tpm_measure_region(&rdev, pcr_index, tcpa_metadata); } + +int crtm_is_set CAR_GLOBAL; + +void measured_boot_init_crtm(void) +{ + if (ENV_ROMSTAGE) { + timestamp_add_now(TS_START_TPMINIT); + int result = tpm_setup(vboot_platform_is_resuming()); + timestamp_add_now(TS_END_TPMINIT); + + if (result == TPM_SUCCESS) { + result = vboot_init_crtm(); + if(result != VB2_SUCCESS) { + printk(BIOS_INFO, + "Initializing CRTM failed!"); + } else { + car_set_var(crtm_is_set, 1); + } + } else { + printk(BIOS_INFO, "TPM setup failed!"); + } + } +} diff --git a/src/security/vboot/vboot_crtm.h b/src/security/vboot/vboot_crtm.h index 64cb4f2..87bfa2d 100644 --- a/src/security/vboot/vboot_crtm.h +++ b/src/security/vboot/vboot_crtm.h @@ -53,6 +53,10 @@ * return 0 if successful, else an error */ uint32_t vboot_measure_cbfs_hook(struct cbfsf *fh, const char *name); +/* + * Initialize crtm without running vboot_logic() + */ +void measured_boot_init_crtm(void); #else #define vboot_measure_cbfs_hook(fh, name) 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/35077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb376b4a8b98baffaee4d574937797bba1f8aee Gerrit-Change-Number: 35077 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

12 184

Change in coreboot[master]: security/vboot: relocate and rename vboot_platform_is_resuming()
by Bill XIE (Code Review) 31 Mar '20

31 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39103 ) Change subject: security/vboot: relocate and rename vboot_platform_is_resuming() ...................................................................... security/vboot: relocate and rename vboot_platform_is_resuming() After measured boot is decoupled from verified boot in CB:35077, vboot_platform_is_resuming() is never vboot-specific, thus it is renamed to platform_is_resuming() and declared in bootmode.h. Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/include/bootmode.h M src/lib/cbfs.c M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/crtm.h M src/security/vboot/vboot_common.h M src/security/vboot/vboot_logic.c M src/soc/amd/common/block/acpi/acpi.c M src/soc/intel/baytrail/pmutil.c M src/soc/intel/braswell/pmutil.c M src/soc/intel/broadwell/pmutil.c M src/soc/intel/common/block/pmc/pmclib.c M src/southbridge/intel/common/pmbase.c M src/vendorcode/eltan/security/verified_boot/vboot_check.c 13 files changed, 37 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/39103/1 diff --git a/src/include/bootmode.h b/src/include/bootmode.h index 3ae8746..9391296 100644 --- a/src/include/bootmode.h +++ b/src/include/bootmode.h @@ -30,4 +30,10 @@ int gfx_get_init_done(void); void gfx_set_init_done(int done); +/* + * Determine if the platform is resuming from suspend. Returns 0 when + * not resuming, > 0 if resuming, and < 0 on error. + */ +int platform_is_resuming(void); + #endif /* __BOOTMODE_H__ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index a375cba..49b4fb2 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -57,10 +57,7 @@ * Files can be added to the RO_REGION_ONLY config option to use this feature. */ printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); - if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) - ERROR("RO region not found\n"); - else - ret = cbfs_locate(fh, &rdev, name, type); + ret = cbfs_locate_file_in_region(fh, "COREBOOT", name, type); } if (!ret) @@ -90,18 +87,14 @@ const char *name, uint32_t *type) { struct region_device rdev; - int ret = 0; + if (fmap_locate_area_as_rdev(region_name, &rdev)) { LOG("%s region not found while looking for %s\n", region_name, name); return -1; } - ret = cbfs_locate(fh, &rdev, name, type); - if (!ret) - if (tspi_measure_cbfs_hook(fh, name)) - return -1; - return ret; + return cbfs_locate(fh, &rdev, name, type); } size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index d404f12..2a2dbec 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -200,14 +200,10 @@ cbfs_file_data(&rdev, fh); switch (cbfs_type) { + case CBFS_TYPE_MRC: case CBFS_TYPE_MRC_CACHE: pcr_index = TPM_RUNTIME_DATA_PCR; break; - /* - * mrc.bin is code executed on CPU, so it - * should not be considered runtime data - */ - case CBFS_TYPE_MRC: case CBFS_TYPE_STAGE: case CBFS_TYPE_SELF: case CBFS_TYPE_FIT: @@ -232,7 +228,7 @@ if ((!CONFIG(TPM_CRTM_INIT_OUTSIDE_BOOTBLOCK) && ENV_BOOTBLOCK) || (CONFIG(TPM_CRTM_INIT_OUTSIDE_BOOTBLOCK) && ENV_ROMSTAGE)) { timestamp_add_now(TS_START_TPMINIT); - int result = tpm_setup(vboot_platform_is_resuming()); + int result = tpm_setup(platform_is_resuming()); timestamp_add_now(TS_END_TPMINIT); if (result == TPM_SUCCESS) { diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index a71443d..aaa01f9 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -46,7 +46,7 @@ */ uint32_t tspi_init_crtm(void); -#if !ENV_SMM && CONFIG(TPM_MEASURED_BOOT) +#if CONFIG(TPM_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) * fh is the cbfs file handle to measure diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index 57f3475..f3884b4 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -49,12 +49,6 @@ */ int vboot_retrieve_hash(void *digest, size_t digest_size); -/* - * Determine if the platform is resuming from suspend. Returns 0 when - * not resuming, > 0 if resuming, and < 0 on error. - */ -int vboot_platform_is_resuming(void); - /* ============================= VERSTAGE ================================== */ /* * Main logic for verified boot. verstage_main() is just the core vboot logic. diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 66929ac..6b1de93 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -114,7 +114,7 @@ if (!CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) return 0; - is_resume = vboot_platform_is_resuming(); + is_resume = platform_is_resuming(); if (is_resume > 0) { uint8_t saved_hash[VBOOT_MAX_HASH_SIZE]; @@ -273,7 +273,7 @@ * does verification of memory init and thus must ensure it resumes with * the same slot that it booted from. */ if (CONFIG(RESUME_PATH_SAME_AS_BOOT) && - vboot_platform_is_resuming()) + platform_is_resuming()) ctx->flags |= VB2_CONTEXT_S3_RESUME; /* Read secdata from TPM. Initialize TPM if secdata not found. We don't diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index e18933b..84970b9 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -13,15 +13,18 @@ * GNU General Public License for more details. */ -#include <arch/acpi.h> -#include <cbmem.h> -#include <elog.h> -#include <console/console.h> -#include <soc/southbridge.h> #include <amdblocks/acpimmio.h> #include <amdblocks/acpi.h> +#include <arch/acpi.h> +#include <bootmode.h> +#include <cbmem.h> +#include <console/console.h> +#include <elog.h> #include <halt.h> #include <security/vboot/vboot_common.h> +#include <soc/southbridge.h> + +#include <halt.h> void poweroff(void) { @@ -137,7 +140,7 @@ return acpi_sleep_from_pm1(acpi_read16(MMIO_ACPI_PM1_CNT_BLK)); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(acpi_read16(MMIO_ACPI_PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index 51174fc..5fed72a 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -16,6 +16,7 @@ #include <stdint.h> #include <arch/acpi.h> #include <arch/io.h> +#include <bootmode.h> #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> @@ -28,7 +29,6 @@ #include <soc/pci_devs.h> #include <soc/pmc.h> #include <security/vboot/vbnv.h> -#include <security/vboot/vboot_common.h> #if defined(__SIMPLE_DEVICE__) @@ -388,7 +388,7 @@ return rtc_failure(); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 18cb04d..cb63d67 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -17,6 +17,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <assert.h> +#include <bootmode.h> #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> @@ -28,7 +29,6 @@ #include <soc/pm.h> #include <stdint.h> #include <security/vboot/vbnv.h> -#include <security/vboot/vboot_common.h> #if defined(__SIMPLE_DEVICE__) @@ -383,7 +383,7 @@ return rtc_failure(); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 2445dfa..826ee8c 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -20,6 +20,7 @@ #include <arch/acpi.h> #include <arch/io.h> +#include <bootmode.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> @@ -31,7 +32,6 @@ #include <soc/pm.h> #include <soc/gpio.h> #include <security/vboot/vbnv.h> -#include <security/vboot/vboot_common.h> /* Print status bits with descriptive names */ static void print_status_bits(u32 status, const char *bit_names[]) @@ -451,7 +451,7 @@ return sci_irq; } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index d022666..7f09384 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <bootmode.h> #include <device/mmio.h> #include <cbmem.h> #include <console/console.h> @@ -22,11 +23,12 @@ #include <intelblocks/gpio.h> #include <intelblocks/tco.h> #include <option.h> +#include <pc80/mc146818rtc.h> +#include <security/vboot/vboot_common.h> #include <soc/pm.h> #include <stdint.h> #include <string.h> #include <timer.h> -#include <security/vboot/vboot_common.h> static struct chipset_power_state power_state; @@ -441,7 +443,7 @@ } #endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) return 0; diff --git a/src/southbridge/intel/common/pmbase.c b/src/southbridge/intel/common/pmbase.c index ff0410a..a7d0476 100644 --- a/src/southbridge/intel/common/pmbase.c +++ b/src/southbridge/intel/common/pmbase.c @@ -16,11 +16,11 @@ #include <stdint.h> #include <arch/acpi.h> #include <arch/io.h> +#include <bootmode.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <assert.h> -#include <security/vboot/vboot_common.h> #include "pmbase.h" #include "pmutil.h" @@ -95,7 +95,7 @@ return inb(lpc_get_pmbase() + addr); } -int vboot_platform_is_resuming(void) +int platform_is_resuming(void) { u16 reg16 = read_pmbase16(PM1_STS); diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 9d99e02..e0a247c 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -16,6 +16,7 @@ #include <boot_device.h> #include <bootmem.h> +#include <bootmode.h> #include <cbfs.h> #include <vboot_check.h> #include <vboot_common.h> @@ -292,7 +293,7 @@ if (CONFIG(VENDORCODE_ELTAN_MBOOT)) { printk(BIOS_DEBUG, "mb_measure returned 0x%x\n", - mb_measure(vboot_platform_is_resuming())); + mb_measure(platform_is_resuming())); } printk(BIOS_SPEW, "%s: process early verify list\n", __func__); -- To view, visit https://review.coreboot.org/c/coreboot/+/39103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29b5b88af0576c34c10cfbd99659a5cdc0c75842 Gerrit-Change-Number: 39103 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: security/tpm: Include mrc.bin in CRTM if present
by Bill XIE (Code Review) 31 Mar '20

31 Mar '20

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38858 ) Change subject: security/tpm: Include mrc.bin in CRTM if present ...................................................................... security/tpm: Include mrc.bin in CRTM if present mrc.bin, on platforms where it presents, is code executed on CPU, so it should be considered a part of CRTM. cbfs_locate_file_in_region() is hooked to measurement here too, since mrc.bin is loaded with it, and CBFS_TYPE_MRC (the type of mrc.bin) is measured to TPM_CRTM_PCR rather than TPM_RUNTIME_DATA_PCR. TODO: I have heard that SMM is too resource-limited to link with vboot library, so currently tspi_measure_cbfs_hook() is masked in SMM. Please correct me if I am wrong. Change-Id: Ib4c3cf47b919864056baf725001ca8a4aaafa110 Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/lib/cbfs.c M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/crtm.h 3 files changed, 16 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/38858/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 517f59d..f9d9af4 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -58,7 +58,11 @@ * Files can be added to the RO_REGION_ONLY config option to use this feature. */ printk(BIOS_DEBUG, "Fall back to RO region for %s\n", name); - ret = cbfs_locate_file_in_region(fh, "COREBOOT", name, type); + if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) + ERROR("RO region not found\n"); + else + ret = cbfs_locate(fh, &rdev, name, type); + } if (!ret) @@ -95,7 +99,11 @@ return -1; } - return cbfs_locate(fh, &rdev, name, type); + int ret = cbfs_locate(fh, &rdev, name, type); + if (!ret) + if (tspi_measure_cbfs_hook(fh, name)) + return -1; + return ret; } size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 89c53a1..1c5438d 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -133,10 +133,14 @@ cbfs_file_data(&rdev, fh); switch (cbfs_type) { - case CBFS_TYPE_MRC: case CBFS_TYPE_MRC_CACHE: pcr_index = TPM_RUNTIME_DATA_PCR; break; + /* + * mrc.bin is code executed on CPU, so it + * should not be considered runtime data + */ + case CBFS_TYPE_MRC: case CBFS_TYPE_STAGE: case CBFS_TYPE_SELF: case CBFS_TYPE_FIT: diff --git a/src/security/tpm/tspi/crtm.h b/src/security/tpm/tspi/crtm.h index 2c2f18b..8899498 100644 --- a/src/security/tpm/tspi/crtm.h +++ b/src/security/tpm/tspi/crtm.h @@ -46,7 +46,7 @@ */ uint32_t tspi_init_crtm(void); -#if CONFIG(TPM_MEASURED_BOOT) +#if !ENV_SMM && CONFIG(TPM_MEASURED_BOOT) /* * Measures cbfs data via hook (cbfs) * fh is the cbfs file handle to measure -- To view, visit https://review.coreboot.org/c/coreboot/+/38858 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4c3cf47b919864056baf725001ca8a4aaafa110 Gerrit-Change-Number: 38858 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/lenovo/t530: Switch to overridetree
by Peter Lemenkov (Code Review) 30 Mar '20

30 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37602 ) Change subject: mb/lenovo/t530: Switch to overridetree ...................................................................... mb/lenovo/t530: Switch to overridetree Change-Id: I3dfa303b6aae2446fa3a1d67a6e31448277cacdb Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/Kconfig R src/mainboard/lenovo/t530/devicetree.cb A src/mainboard/lenovo/t530/variants/t530/overridetree.cb D src/mainboard/lenovo/t530/variants/w530/devicetree.cb A src/mainboard/lenovo/t530/variants/w530/overridetree.cb 5 files changed, 43 insertions(+), 198 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/37602/1 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index d1ba6a8..4b3303b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -37,9 +37,9 @@ string default "lenovo/t530" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb similarity index 97% rename from src/mainboard/lenovo/t530/variants/t530/devicetree.cb rename to src/mainboard/lenovo/t530/devicetree.cb index c2a9259..62b622f 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -142,10 +142,6 @@ register "has_bdc_detection" = "1" register "bdc_gpio_num" = "54" register "bdc_gpio_lvl" = "0" - - register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" end chip drivers/lenovo/hybrid_graphics device pnp ff.f on end # dummy diff --git a/src/mainboard/lenovo/t530/variants/t530/overridetree.cb b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb new file mode 100644 index 0000000..e106aa6 --- /dev/null +++ b/src/mainboard/lenovo/t530/variants/t530/overridetree.cb @@ -0,0 +1,13 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end + end + end +end diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb deleted file mode 100644 index f814c3f..0000000 --- a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb +++ /dev/null @@ -1,192 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - register "gpu_dp_b_hotplug" = "0" - register "gpu_dp_c_hotplug" = "0" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms - register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms - register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x11551155" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21f6 inherit - - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on # Internal graphics VGA controller - subsystemid 0x17aa 0x21f5 - end - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) - register "sata_port_map" = "0x3f" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - register "c2_latency" = "101" # c2 not supported - - register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }" - - register "xhci_switchable_ports" = "0xf" - register "superspeed_capable_ports" = "0xf" - register "xhci_overcurrent_mapping" = "0x4000201" - - register "docking_supported" = "1" - - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 on end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21f3 - end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on # PCIe Port #1 - chip drivers/ricoh/rce822 # Ricoh cardreader - register "disable_mask" = "0x83" - register "sdwppol" = "1" - device pci 00.0 on end # Ricoh SD card reader - end - end - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on # PCIe Port #3 - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # PCI-LPC bridge - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x01" - register "config2" = "0xa0" - register "config3" = "0xe2" - - register "has_keyboard_backlight" = "1" - - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xd0" - register "event5_enable" = "0xfc" - register "event6_enable" = "0x00" - register "event7_enable" = "0x01" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal - end - end -end diff --git a/src/mainboard/lenovo/t530/variants/w530/overridetree.cb b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb new file mode 100644 index 0000000..31de364 --- /dev/null +++ b/src/mainboard/lenovo/t530/variants/w530/overridetree.cb @@ -0,0 +1,28 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + device domain 0 on + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f5 + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "docking_supported" = "1" + device pci 16.3 on end # Management Engine KT + device pci 1c.0 on # PCIe Port #1 + chip drivers/ricoh/rce822 # Ricoh cardreader + register "disable_mask" = "0x83" + register "sdwppol" = "1" + device pci 00.0 on end # Ricoh SD card reader + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "config1" = "0x01" + register "config3" = "0xe2" + end + end + device pci 1f.6 off end # Thermal + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/37602 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3dfa303b6aae2446fa3a1d67a6e31448277cacdb Gerrit-Change-Number: 37602 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 21

Change in coreboot[master]: asus/p2b-*: Fold into p2b as variants thereof
by Keith Hui (Code Review) 30 Mar '20

30 Mar '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38621 ) Change subject: asus/p2b-*: Fold into p2b as variants thereof ...................................................................... asus/p2b-*: Fold into p2b as variants thereof Their DSDTs are unified in the process. As a result: p2b-ls gets the S1 entry from p2b All other p2b-* boards gain a DSDT paving the way for ACPI support. TEST=abuild Change-Id: Ibc9bfa4fc5b582bf658215bda298523e8ee7b36b Signed-off-by: Keith Hui <buurin(a)gmail.com> --- D src/mainboard/asus/p2b-d/Kconfig D src/mainboard/asus/p2b-d/Kconfig.name D src/mainboard/asus/p2b-d/board_info.txt D src/mainboard/asus/p2b-d/romstage.c D src/mainboard/asus/p2b-ds/Kconfig D src/mainboard/asus/p2b-ds/Kconfig.name D src/mainboard/asus/p2b-ds/board_info.txt D src/mainboard/asus/p2b-ds/mptable.c D src/mainboard/asus/p2b-ds/romstage.c D src/mainboard/asus/p2b-f/Kconfig D src/mainboard/asus/p2b-f/Kconfig.name D src/mainboard/asus/p2b-f/board_info.txt D src/mainboard/asus/p2b-f/romstage.c D src/mainboard/asus/p2b-ls/Kconfig D src/mainboard/asus/p2b-ls/Kconfig.name D src/mainboard/asus/p2b-ls/acpi_tables.c D src/mainboard/asus/p2b-ls/board_info.txt D src/mainboard/asus/p2b-ls/dsdt.asl D src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/Kconfig M src/mainboard/asus/p2b/Kconfig.name M src/mainboard/asus/p2b/dsdt.asl R src/mainboard/asus/p2b/mptable.c R src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c R src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c R src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c R src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb R src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c 31 files changed, 145 insertions(+), 665 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/38621/1 diff --git a/src/mainboard/asus/p2b-d/Kconfig b/src/mainboard/asus/p2b-d/Kconfig deleted file mode 100644 index 8db9b7a..0000000 --- a/src/mainboard/asus/p2b-d/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_D - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select IOAPIC - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - -config MAINBOARD_DIR - string - default "asus/p2b-d" - -config MAINBOARD_PART_NUMBER - string - default "P2B-D" - -config IRQ_SLOT_COUNT - int - default 6 - -config MAX_CPUS - int - default 2 - -endif # BOARD_ASUS_P2B_D diff --git a/src/mainboard/asus/p2b-d/Kconfig.name b/src/mainboard/asus/p2b-d/Kconfig.name deleted file mode 100644 index 23e7808..0000000 --- a/src/mainboard/asus/p2b-d/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_D - bool "P2B-D" diff --git a/src/mainboard/asus/p2b-d/board_info.txt b/src/mainboard/asus/p2b-d/board_info.txt deleted file mode 100644 index fdee74e..0000000 --- a/src/mainboard/asus/p2b-d/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-d/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c deleted file mode 100644 index 7fad06b..0000000 --- a/src/mainboard/asus/p2b-d/romstage.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Shares romstage with P2B-DS */ -#include "../p2b-ds/romstage.c" diff --git a/src/mainboard/asus/p2b-ds/Kconfig b/src/mainboard/asus/p2b-ds/Kconfig deleted file mode 100644 index 8b55174..0000000 --- a/src/mainboard/asus/p2b-ds/Kconfig +++ /dev/null @@ -1,46 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_DS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select SMP - select IOAPIC - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - -config MAINBOARD_DIR - string - default "asus/p2b-ds" - -config MAINBOARD_PART_NUMBER - string - default "P2B-DS" - -config IRQ_SLOT_COUNT - int - default 7 - -config MAX_CPUS - int - default 2 - -endif # BOARD_ASUS_P2B_DS diff --git a/src/mainboard/asus/p2b-ds/Kconfig.name b/src/mainboard/asus/p2b-ds/Kconfig.name deleted file mode 100644 index 0335139..0000000 --- a/src/mainboard/asus/p2b-ds/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_DS - bool "P2B-DS" diff --git a/src/mainboard/asus/p2b-ds/board_info.txt b/src/mainboard/asus/p2b-ds/board_info.txt deleted file mode 100644 index 29a7266..0000000 --- a/src/mainboard/asus/p2b-ds/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ds/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-ds/mptable.c b/src/mainboard/asus/p2b-ds/mptable.c deleted file mode 100644 index b492511..0000000 --- a/src/mainboard/asus/p2b-ds/mptable.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - int ioapic_id, ioapic_ver, isa_bus; - struct mp_config_table *mc; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - mptable_write_buses(mc, NULL, &isa_bus); - - ioapic_id = 2; - ioapic_ver = 0x11; /* External Intel 82093AA IOAPIC. */ - smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); - - /* Legacy Interrupts */ - mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0); - - /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); - - /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, 0x1); - - /* Compute the checksums. */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c deleted file mode 100644 index d0456e5..0000000 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/intel/i440bx/raminit.h> -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83977tf/w83977tf.h> - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/asus/p2b-f/Kconfig b/src/mainboard/asus/p2b-f/Kconfig deleted file mode 100644 index efe625c..0000000 --- a/src/mainboard/asus/p2b-f/Kconfig +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_F - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - -config MAINBOARD_DIR - string - default "asus/p2b-f" - -config MAINBOARD_PART_NUMBER - string - default "P2B-F" - -config IRQ_SLOT_COUNT - int - default 7 - -endif # BOARD_ASUS_P2B_F diff --git a/src/mainboard/asus/p2b-f/Kconfig.name b/src/mainboard/asus/p2b-f/Kconfig.name deleted file mode 100644 index a433376..0000000 --- a/src/mainboard/asus/p2b-f/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_F - bool "P2B-F" diff --git a/src/mainboard/asus/p2b-f/board_info.txt b/src/mainboard/asus/p2b-f/board_info.txt deleted file mode 100644 index 79b8d91..0000000 --- a/src/mainboard/asus/p2b-f/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-f/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c deleted file mode 100644 index 31a100c..0000000 --- a/src/mainboard/asus/p2b-f/romstage.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* Shares romstage with the better supported P2B-LS sibling. */ -#include "../p2b-ls/romstage.c" diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig deleted file mode 100644 index 60124fe..0000000 --- a/src/mainboard/asus/p2b-ls/Kconfig +++ /dev/null @@ -1,40 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Keith Hui <buurin(a)gmail.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -if BOARD_ASUS_P2B_LS - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select CPU_INTEL_SLOT_1 - select NORTHBRIDGE_INTEL_I440BX - select SOUTHBRIDGE_INTEL_I82371EB - select SUPERIO_WINBOND_W83977TF - select HAVE_PIRQ_TABLE - select BOARD_ROMSIZE_KB_256 - select SDRAMPWR_4DIMM - select HAVE_ACPI_TABLES - -config MAINBOARD_DIR - string - default "asus/p2b-ls" - -config MAINBOARD_PART_NUMBER - string - default "P2B-LS" - -config IRQ_SLOT_COUNT - int - default 8 - -endif # BOARD_ASUS_P2B_LS diff --git a/src/mainboard/asus/p2b-ls/Kconfig.name b/src/mainboard/asus/p2b-ls/Kconfig.name deleted file mode 100644 index 0ad0f47..0000000 --- a/src/mainboard/asus/p2b-ls/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_ASUS_P2B_LS - bool "P2B-LS" diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c deleted file mode 100644 index d740ee1..0000000 --- a/src/mainboard/asus/p2b-ls/acpi_tables.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/acpi.h> - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* mainboard has no ioapic */ - return current; -} diff --git a/src/mainboard/asus/p2b-ls/board_info.txt b/src/mainboard/asus/p2b-ls/board_info.txt deleted file mode 100644 index 21bf26e..0000000 --- a/src/mainboard/asus/p2b-ls/board_info.txt +++ /dev/null @@ -1,7 +0,0 @@ -Category: desktop -Board URL: ftp://ftp.asus.com.tw/pub/ASUS/mb/slot1/440bx/p2b-ls/ -ROM package: DIP32 -ROM protocol: Parallel -ROM socketed: y -Flashrom support: y -Release year: 1998 diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl deleted file mode 100644 index b350bc9..0000000 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ /dev/null @@ -1,272 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Keith Hui <buurin(a)gmail.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <southbridge/intel/i82371eb/i82371eb.h> - -#define SUPERIO_PNP_BASE 0x3F0 -#define SUPERIO_SHOW_UARTA -#define SUPERIO_SHOW_UARTB -#define SUPERIO_SHOW_FDC -#define SUPERIO_SHOW_LPT - -#include <arch/acpi.h> -DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) -{ - /* \_PR scope defining the main processor is generated in SSDT. */ - - OperationRegion(X80, SystemIO, 0x80, 1) - Field(X80, ByteAcc, NoLock, Preserve) - { - P80, 8 - } - - /* - * For now only define 2 power states: - * - S0 which is fully on - * - S5 which is soft off - * Any others would involve declaring the wake up methods. - */ - - /* - * Intel 82371EB (PIIX4E) datasheet, section 7.2.3, page 142 - * - * 0: soft off/suspend to disk S5 - * 1: suspend to ram S3 - * 2: powered on suspend, context lost S2 - * Note: 'context lost' means the CPU restarts at the reset - * vector - * 3: powered on suspend, CPU context lost S1 - * Note: Looks like 'CPU context lost' does _not_ mean the - * CPU restarts at the reset vector. Most likely only - * caches are lost, so both 0x3 and 0x4 map to ACPI S1 - * 4: powered on suspend, context maintained S1 - * 5: working (clock control) S0 - * 6: reserved - * 7: reserved - */ - Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 }) - /* - * Kept as a memo of the value needed, but blocked out until - * suspend/resume support is implemented. - */ - /*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/ - /*Name (\_S4, Package () { 0x01, 0x06, 0x00, 0x00 })*/ - Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 }) - - OperationRegion (GPOB, SystemIO, DEFAULT_PMBASE+DEVCTL, 0x10) - Field (GPOB, ByteAcc, NoLock, Preserve) - { - Offset (0x03), - TO12, 1, /* Device trap 12 */ - Offset (0x08), - FANM, 1, /* GPO0, meant for fan */ - Offset (0x09), - PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */ - , 3, /* this goes low when power is cut from its core. */ - , 2, - , 16, - MSG0, 1 /* GPO30, message LED */ - } - - /* Prepare To Sleep, Arg0 is target S-state */ - Method (\_PTS, 1, NotSerialized) - { - /* Disable fan, blink power LED, if not turning off */ - If (LNotEqual (Arg0, 0x05)) - { - Store (Zero, FANM) - Store (Zero, PLED) - } - - /* Arms SMI for device 12 */ - Store (One, TO12) - /* Put out a POST code */ - Or (Arg0, 0xF0, P80) - } - - Method (\_WAK, 1, NotSerialized) - { - /* Re-enable fan, stop power led blinking */ - Store (One, FANM) - Store (One, PLED) - /* wake OK */ - Return(Package(0x02){0x00, 0x00}) - } - - /* Root of the bus hierarchy */ - Scope (\_SB) - { - Device (PWRB) - { - /* Power Button Device */ - Name (_HID, EisaId ("PNP0C0C")) - Method (_STA, 0, NotSerialized) - { - Return (0x0B) - } - } - #include <southbridge/intel/i82371eb/acpi/intx.asl> - - PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1) - PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2) - PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3) - PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4) - - /* Top PCI device */ - Device (PCI0) - { - Name (_HID, EisaId ("PNP0A03")) - Name (_UID, 0x00) - Name (_BBN, 0x00) - - /* PCI Routing Table */ - Name (_PRT, Package () { - Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, - Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, - Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, - Package (0x04) { 0x0001FFFF, 3, LNKD, 0 }, - - Package (0x04) { 0x0004FFFF, 0, LNKA, 0 }, - Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, - Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, - Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, - - Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, - Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, - Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, - Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, - - Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, - Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, - Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, - Package (0x04) { 0x0009FFFF, 3, LNKC, 0 }, - - Package (0x04) { 0x000AFFFF, 0, LNKC, 0 }, - Package (0x04) { 0x000AFFFF, 1, LNKD, 0 }, - Package (0x04) { 0x000AFFFF, 2, LNKA, 0 }, - Package (0x04) { 0x000AFFFF, 3, LNKB, 0 }, - - Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, - Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, - Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, - Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, - - Package (0x04) { 0x000BFFFF, 0, LNKB, 0 }, - Package (0x04) { 0x000BFFFF, 1, LNKC, 0 }, - Package (0x04) { 0x000BFFFF, 2, LNKD, 0 }, - Package (0x04) { 0x000BFFFF, 3, LNKA, 0 }, - - Package (0x04) { 0x000CFFFF, 0, LNKA, 0 }, - Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, - Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, - Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, - - }) - #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> - #include <southbridge/intel/i82371eb/acpi/isabridge.asl> - - /* Begin southbridge block */ - Device (PX40) - { - Name(_ADR, 0x00040000) - OperationRegion (PIRQ, PCI_Config, 0x60, 0x04) - Field (PIRQ, ByteAcc, NoLock, Preserve) - { - PIRA, 8, - PIRB, 8, - PIRC, 8, - PIRD, 8 - } - - /* PNP Motherboard Resources */ - Device (SYSR) - { - Name (_HID, EisaId ("PNP0C02")) - Name (_UID, 0x02) - Method (_CRS, 0, NotSerialized) - { - Name (BUF1, ResourceTemplate () - { - /* PM register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06) - /* SMBus register ports */ - IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07) - /* PIIX4E ports */ - /* Aliased DMA ports */ - IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, ) - /* Aliased PIC ports */ - IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, ) - /* Aliased timer ports */ - IO (Decode16, 0x0050, 0x0050, 0x01, 0x04, ) - IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, ) - IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, ) - IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, ) - IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, ) - IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, ) - IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, ) - IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, ) - IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, ) - IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, ) - }) - CreateWordField (BUF1, _Y06._MIN, PMLO) - CreateWordField (BUF1, _Y06._MAX, PMRL) - CreateWordField (BUF1, _Y07._MIN, SBLO) - CreateWordField (BUF1, _Y07._MAX, SBRL) - - And (\_SB.PCI0.PX43.PM00, 0xFFFE, PMLO) - And (\_SB.PCI0.PX43.SB00, 0xFFFE, SBLO) - Store (PMLO, PMRL) - Store (SBLO, SBRL) - Return (BUF1) - } - } - #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> - } - Device (PX43) - { - Name (_ADR, 0x00040003) // _ADR: Address - OperationRegion (IPMU, PCI_Config, PMBA, 0x02) - Field (IPMU, ByteAcc, NoLock, Preserve) - { - PM00, 16 - } - - OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) - Field (ISMB, ByteAcc, NoLock, Preserve) - { - SB00, 16 - } - } - - #include <superio/winbond/w83977tf/acpi/superio.asl> - } - } - - /* ACPI Message */ - Scope (\_SI) - { - Method (_MSG, 1, NotSerialized) - { - If (LEqual (Arg0, Zero)) - { - Store (One, MSG0) - } - Else - { - Store (Zero, MSG0) - } - } - } -} diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c deleted file mode 100644 index b79ac82..0000000 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <northbridge/intel/i440bx/raminit.h> -#include <superio/winbond/common/winbond.h> -/* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ -#include <superio/winbond/w83977tf/w83977tf.h> - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -void mainboard_enable_serial(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/asus/p2b/Kconfig b/src/mainboard/asus/p2b/Kconfig index 65e7681..3d18bf8 100644 --- a/src/mainboard/asus/p2b/Kconfig +++ b/src/mainboard/asus/p2b/Kconfig @@ -12,7 +12,15 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -if BOARD_ASUS_P2B + +if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS || BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS + +config BASE_ASUS_P2B_D + def_bool n + select SDRAMPWR_4DIMM + select HAVE_MP_TABLE + select IOAPIC + select SMP config BOARD_SPECIFIC_OPTIONS def_bool y @@ -22,18 +30,42 @@ select SUPERIO_WINBOND_W83977TF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 - select HAVE_ACPI_TABLES + select HAVE_ACPI_TABLES if BOARD_ASUS_P2B || BOARD_ASUS_P2B_LS + select SDRAMPWR_4DIMM if BOARD_ASUS_P2B_F || BOARD_ASUS_P2B_LS + select BASE_ASUS_P2B_D if BOARD_ASUS_P2B_D || BOARD_ASUS_P2B_DS + +config MAX_CPUS + int + default 2 if BASE_ASUS_P2B_D + default 1 config MAINBOARD_DIR string default "asus/p2b" -config MAINBOARD_PART_NUMBER +config VARIANT_DIR string - default "P2B" + default "p2b-d" if BOARD_ASUS_P2B_D + default "p2b-ds" if BOARD_ASUS_P2B_DS + default "p2b-f" if BOARD_ASUS_P2B_F + default "p2b-ls" if BOARD_ASUS_P2B_LS + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" if ! BOARD_ASUS_P2B config IRQ_SLOT_COUNT int - default 6 + default 8 if BOARD_ASUS_P2B_LS + default 6 if BOARD_ASUS_P2B || BOARD_ASUS_P2B_D + default 7 -endif # BOARD_ASUS_P2B +config MAINBOARD_PART_NUMBER + string + default "P2B" if BOARD_ASUS_P2B + default "P2B-D" if BOARD_ASUS_P2B_D + default "P2B-DS" if BOARD_ASUS_P2B_DS + default "P2B-F" if BOARD_ASUS_P2B_F + default "P2B-LS" if BOARD_ASUS_P2B_LS + +endif diff --git a/src/mainboard/asus/p2b/Kconfig.name b/src/mainboard/asus/p2b/Kconfig.name index 60d6028..a6cd510 100644 --- a/src/mainboard/asus/p2b/Kconfig.name +++ b/src/mainboard/asus/p2b/Kconfig.name @@ -1,2 +1,15 @@ config BOARD_ASUS_P2B bool "P2B" + +config BOARD_ASUS_P2B_D + bool "P2B-D" + +config BOARD_ASUS_P2B_DS + bool "P2B-DS" + +config BOARD_ASUS_P2B_F + bool "P2B-F" + +config BOARD_ASUS_P2B_LS + bool "P2B-LS" + diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 3fc531a..08fb3a5b 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -46,12 +46,12 @@ * 0: soft off/suspend to disk S5 * 1: suspend to ram S3 * 2: powered on suspend, context lost S2 - * Note: 'context lost' means the CPU restarts at the reset - * vector + * Note: 'context lost' means the CPU restarts at the reset + * vector * 3: powered on suspend, CPU context lost S1 - * Note: Looks like 'CPU context lost' does _not_ mean the - * CPU restarts at the reset vector. Most likely only - * caches are lost, so both 0x3 and 0x4 map to ACPI S1 + * Note: Looks like 'CPU context lost' does _not_ mean the + * CPU restarts at the reset vector. Most likely only + * caches are lost, so both 0x3 and 0x4 map to ACPI S1 * 4: powered on suspend, context maintained S1 * 5: working (clock control) S0 * 6: reserved @@ -70,23 +70,32 @@ FANM, 1, /* GPO0, meant for fan */ Offset (0x09), PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet */ - , 3, /* this goes low when power is cut from its core. */ - , 2, - , 16, + , 3, /* this goes low when power is cut from its core. */ + , 2, + , 16, MSG0, 1 /* GPO30, message LED */ } +#if CONFIG(BOARD_ASUS_P2B_D) || CONFIG(BOARD_ASUS_P2B_DS) + Name (\PICF, 0x00) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model (ACPI spec 2.0c, 5.8.1) + { + \PICF = Arg0 + } +#endif + /* Prepare To Sleep, Arg0 is target S-state */ Method (\_PTS, 1, NotSerialized) { /* Disable fan, blink power LED, if not turning off */ If (LNotEqual (Arg0, 0x05)) { - Store (Zero, FANM) - Store (Zero, PLED) + Store (Zero, FANM) + Store (Zero, PLED) } /* Arms SMI for device 12 */ + /* TODO: Factory BIOS only does this for S1 */ Store (One, TO12) /* Put out a POST code */ Or (Arg0, 0xF0, P80) @@ -128,7 +137,11 @@ Name (_BBN, 0x00) /* PCI Routing Table */ +#if CONFIG(BOARD_ASUS_P2B_D) || CONFIG(BOARD_ASUS_P2B_DS) + Name (PICM, Package () { +#else Name (_PRT, Package () { +#endif Package (0x04) { 0x0001FFFF, 0, LNKA, 0 }, Package (0x04) { 0x0001FFFF, 1, LNKB, 0 }, Package (0x04) { 0x0001FFFF, 2, LNKC, 0 }, @@ -138,7 +151,18 @@ Package (0x04) { 0x0004FFFF, 1, LNKB, 0 }, Package (0x04) { 0x0004FFFF, 2, LNKC, 0 }, Package (0x04) { 0x0004FFFF, 3, LNKD, 0 }, - +#if CONFIG(BOARD_ASUS_P2B_LS) || CONFIG(BOARD_ASUS_P2B_DS) + Package (0x04) { 0x0006FFFF, 0, LNKD, 0 }, + Package (0x04) { 0x0006FFFF, 1, LNKA, 0 }, + Package (0x04) { 0x0006FFFF, 2, LNKB, 0 }, + Package (0x04) { 0x0006FFFF, 3, LNKC, 0 }, +#endif +#if CONFIG(BOARD_ASUS_P2B_LS) + Package (0x04) { 0x0007FFFF, 0, LNKC, 0 }, + Package (0x04) { 0x0007FFFF, 1, LNKD, 0 }, + Package (0x04) { 0x0007FFFF, 2, LNKA, 0 }, + Package (0x04) { 0x0007FFFF, 3, LNKB, 0 }, +#endif Package (0x04) { 0x0009FFFF, 0, LNKD, 0 }, Package (0x04) { 0x0009FFFF, 1, LNKA, 0 }, Package (0x04) { 0x0009FFFF, 2, LNKB, 0 }, @@ -158,8 +182,63 @@ Package (0x04) { 0x000CFFFF, 1, LNKB, 0 }, Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, +#if CONFIG(BOARD_ASUS_P2B_F) + Package (0x04) { 0x000DFFFF, 0, LNKD, 0 }, + Package (0x04) { 0x000DFFFF, 1, LNKA, 0 }, + Package (0x04) { 0x000DFFFF, 2, LNKB, 0 }, + Package (0x04) { 0x000DFFFF, 3, LNKC, 0 }, +#endif }) +#if CONFIG(BOARD_ASUS_P2B_D) || CONFIG(BOARD_ASUS_P2B_DS) + Name (APIC, Package () { + Package (0x04) { 0x000CFFFF, 0, 0, 0x10 }, + Package (0x04) { 0x000CFFFF, 1, 0, 0x11 }, + Package (0x04) { 0x000CFFFF, 2, 0, 0x12 }, + Package (0x04) { 0x000CFFFF, 3, 0, 0x13 }, + + Package (0x04) { 0x000BFFFF, 0, 0, 0x11 }, + Package (0x04) { 0x000BFFFF, 1, 0, 0x12 }, + Package (0x04) { 0x000BFFFF, 2, 0, 0x13 }, + Package (0x04) { 0x000BFFFF, 3, 0, 0x10 }, + + Package (0x04) { 0x000AFFFF, 0, 0, 0x12 }, + Package (0x04) { 0x000AFFFF, 1, 0, 0x13 }, + Package (0x04) { 0x000AFFFF, 2, 0, 0x10 }, + Package (0x04) { 0x000AFFFF, 3, 0, 0x11 }, + + Package (0x04) { 0x0009FFFF, 0, 0, 0x13 }, + Package (0x04) { 0x0009FFFF, 1, 0, 0x10 }, + Package (0x04) { 0x0009FFFF, 2, 0, 0x11 }, + Package (0x04) { 0x0009FFFF, 3, 0, 0x12 }, +#if CONFIG(BOARD_ASUS_P2B_DS) + Package (0x04) { 0x0006FFFF, 0, 0, 0x13 }, + Package (0x04) { 0x0006FFFF, 1, 0, 0x10 }, + Package (0x04) { 0x0006FFFF, 2, 0, 0x11 }, + Package (0x04) { 0x0006FFFF, 3, 0, 0x12 }, +#endif + Package (0x04) { 0x0004FFFF, 0, 0, 0x10 }, + Package (0x04) { 0x0004FFFF, 1, 0, 0x11 }, + Package (0x04) { 0x0004FFFF, 2, 0, 0x12 }, + Package (0x04) { 0x0004FFFF, 3, 0, 0x13 }, + + Package (0x04) { 0x0001FFFF, 0, 0, 0x10 }, + Package (0x04) { 0x0001FFFF, 1, 0, 0x11 }, + Package (0x04) { 0x0001FFFF, 2, 0, 0x12 }, + Package (0x04) { 0x0001FFFF, 3, 0, 0x13 } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If (!\PICF) + { + Return (PICM) + } + Else + { + Return (APIC) + } + } +#endif #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> #include <southbridge/intel/i82371eb/acpi/isabridge.asl> @@ -226,13 +305,13 @@ OperationRegion (IPMU, PCI_Config, PMBA, 0x02) Field (IPMU, ByteAcc, NoLock, Preserve) { - PM00, 16 + PM00, 16 } OperationRegion (ISMB, PCI_Config, SMBBA, 0x02) Field (ISMB, ByteAcc, NoLock, Preserve) { - SB00, 16 + SB00, 16 } } diff --git a/src/mainboard/asus/p2b-d/mptable.c b/src/mainboard/asus/p2b/mptable.c similarity index 92% rename from src/mainboard/asus/p2b-d/mptable.c rename to src/mainboard/asus/p2b/mptable.c index 8f643d1..fddb218 100644 --- a/src/mainboard/asus/p2b-d/mptable.c +++ b/src/mainboard/asus/p2b/mptable.c @@ -40,6 +40,8 @@ /* I/O Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x13, ioapic_id, 0x13); /* UHCI */ + if (CONFIG(BOARD_ASUS_P2B_DS)) + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, 0x0, 0x18, ioapic_id, 0x13); /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); diff --git a/src/mainboard/asus/p2b-d/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-d/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-d/devicetree.cb diff --git a/src/mainboard/asus/p2b-d/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-d/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-d/irq_tables.c diff --git a/src/mainboard/asus/p2b-ds/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-ds/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-ds/devicetree.cb diff --git a/src/mainboard/asus/p2b-ds/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-ds/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-ds/irq_tables.c diff --git a/src/mainboard/asus/p2b-f/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-f/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-f/devicetree.cb diff --git a/src/mainboard/asus/p2b-f/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-f/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-f/irq_tables.c diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb similarity index 100% rename from src/mainboard/asus/p2b-ls/devicetree.cb rename to src/mainboard/asus/p2b/variants/p2b-ls/devicetree.cb diff --git a/src/mainboard/asus/p2b-ls/irq_tables.c b/src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c similarity index 100% rename from src/mainboard/asus/p2b-ls/irq_tables.c rename to src/mainboard/asus/p2b/variants/p2b-ls/irq_tables.c -- To view, visit https://review.coreboot.org/c/coreboot/+/38621 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc9bfa4fc5b582bf658215bda298523e8ee7b36b Gerrit-Change-Number: 38621 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: cpu/x86/Makefile.inc: Fix external toolchain build
by Arthur Heymans (Code Review) 29 Mar '20

29 Mar '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37193 ) Change subject: cpu/x86/Makefile.inc: Fix external toolchain build ...................................................................... cpu/x86/Makefile.inc: Fix external toolchain build The sipi_vector.S just needs to be linked as relocatable so there is no need to invoke the compiler. TEST: BUILD_TIMELESS=1 has the same hashes Change-Id: I0370f1590a70cffb48c7930f6ae85956b506b09c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/37193/1 diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9c18d44..194a76c 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -27,7 +27,7 @@ rmodules_$(ARCH-$(TARGET_STAGE)-y)-$(CONFIG_PARALLEL_MP) += sipi_vector.S $(SIPI_DOTO): $(call src-to-obj,rmodules_$(ARCH-$(TARGET_STAGE)-y),src/cpu/x86/sipi_vector.S) - $(CC_rmodules_$(ARCH-$(TARGET_STAGE)-y)) $(CFLAGS_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ + $(LD_rmodules_$(ARCH-$(TARGET_STAGE)-y)) -nostdlib -r -o $@ $^ $(eval $(call rmodule_link,$(SIPI_ELF), $(SIPI_DOTO), 0,$(ARCH-$(TARGET_STAGE)-y))) -- To view, visit https://review.coreboot.org/c/coreboot/+/37193 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0370f1590a70cffb48c7930f6ae85956b506b09c Gerrit-Change-Number: 37193 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/lenovo/t530/devicetree: Trim DID entries to actual size.
by Peter Lemenkov (Code Review) 29 Mar '20

29 Mar '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38707 ) Change subject: mb/lenovo/t530/devicetree: Trim DID entries to actual size. ...................................................................... mb/lenovo/t530/devicetree: Trim DID entries to actual size. Change-Id: I6da5b3270c14b4953cd25b4d8776479eb8a239c8 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t530/variants/t530/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38707/1 diff --git a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb index 674b0f8..6f6dd1c 100644 --- a/src/mainboard/lenovo/t530/variants/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb @@ -1,7 +1,7 @@ chip northbridge/intel/sandybridge # IGD Displays register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" # Enable DisplayPort Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" -- To view, visit https://review.coreboot.org/c/coreboot/+/38707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6da5b3270c14b4953cd25b4d8776479eb8a239c8 Gerrit-Change-Number: 38707 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

3 10

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020