coreboot-gerrit February 2020

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Change in coreboot[master]: soc/mediatek/mt8183: Add get dram type API at ATF
by huayang duan (Code Review) 16 Mar '20

16 Mar '20

Hello Duan huayang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39097 to review the following change. Change subject: soc/mediatek/mt8183: Add get dram type API at ATF ...................................................................... soc/mediatek/mt8183: Add get dram type API at ATF DVFS module need know the dram type at ATF for loading the correct spm binary. BRANCH=kukui BUG=none TEST=bootup pass Change-Id: I20afc00c4c671abcbb6f36eb8e3e364529e9389c Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/mainboard/google/kukui/mainboard.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/39097/1 diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c index 844496d..da39c1c 100644 --- a/src/mainboard/google/kukui/mainboard.c +++ b/src/mainboard/google/kukui/mainboard.c @@ -184,8 +184,19 @@ .gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH }, }; + /* use .polarity to save dram type value */ + static struct bl_aux_param_gpio param_dram_type = { + .h = { .type = BL_AUX_PARAM_MTK_DRAM_TYPE }, +#if CONFIG(MT8183_DRAM_EMCP) + .gpio = { .polarity = DRAMC_CONFIG_EMCP }, +#else + .gpio = { .polarity = 0 }, +#endif + }; + param_reset.gpio.index = GPIO_RESET.id; register_bl31_aux_param(&param_reset.h); + register_bl31_aux_param(&param_dram_type.h); } static void mainboard_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/39097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20afc00c4c671abcbb6f36eb8e3e364529e9389c Gerrit-Change-Number: 39097 Gerrit-PatchSet: 1 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: mainboard/google/hatch: Add Palkia support
by Kane Chen (Code Review) 16 Mar '20

16 Mar '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39096 ) Change subject: mainboard/google/hatch: Add Palkia support ...................................................................... mainboard/google/hatch: Add Palkia support Add Palkia as a variant of Hatch. BUG=b:none BRANCH=None TEST=util/abuild/abuild -p none -t google/hatch -x -a attempts to build a Helios target. Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ifeb1e2808f3779a1a1c4da9b71b535b02fb4e1e0 --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/39096/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 783ec73..3add7ab 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -98,6 +98,7 @@ default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU default "Mushu" if BOARD_GOOGLE_MUSHU + default "Palkia" if BOARD_GOOGLE_PALKIA default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE @@ -121,6 +122,7 @@ default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU default "mushu" if BOARD_GOOGLE_MUSHU + default "palkia" if BOARD_GOOGLE_PALKIA default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index e216135..c2dd7ca 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -60,3 +60,10 @@ bool "-> Stryke" select BOARD_GOOGLE_BASEBOARD_HATCH select BOARD_ROMSIZE_KB_16384 + +config BOARD_GOOGLE_PALKIA + bool "-> Palkia" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + select CHROMEOS_DSM_CALIB + select DRIVERS_I2C_RT1011 -- To view, visit https://review.coreboot.org/c/coreboot/+/39096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifeb1e2808f3779a1a1c4da9b71b535b02fb4e1e0 Gerrit-Change-Number: 39096 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

8 17

Change in coreboot[master]: soc/intel/common: Check prerequisites for GLOBAL_RESET command
by Sridhar Siricilla (Code Review) 15 Mar '20

15 Mar '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38800 ) Change subject: soc/intel/common: Check prerequisites for GLOBAL_RESET command ...................................................................... soc/intel/common: Check prerequisites for GLOBAL_RESET command Check prerequisites before sending GLOBAL RESET command to CSE. TEST=Verified on hatch. Change-Id: Ia583e4033f15ec20e942202fa78e7884cf370ce4 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38800/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 072dd05..735c0e1 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -607,6 +607,17 @@ return pci_read_config32(PCH_DEV_CSE, offset); } +static int cse_check_global_reset_prerequisites(void) +{ + if (cse_is_hfs1_cws_normal() && cse_is_hfs1_com_normal()) + return 1; + else if (cse_is_hfs3_fw_sku_custom() && cse_is_hfs1_cws_normal() + && (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_secover_mei_msg())) + return 1; + + return 0; +} + /* * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/ * HOST_RESET_ONLY/CSE_RESET_ONLY. @@ -631,12 +642,18 @@ size_t reply_size; printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); + if (!((rst_type == GLOBAL_RESET) || (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) { printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); return 0; } + if (!cse_check_global_reset_prerequisites()) { + printk(BIOS_ERR, "HECI: CSE is not meeting required prerequisites\n"); + return 0; + } + heci_reset(); reply_size = sizeof(reply); -- To view, visit https://review.coreboot.org/c/coreboot/+/38800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia583e4033f15ec20e942202fa78e7884cf370ce4 Gerrit-Change-Number: 38800 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

5 18

Change in coreboot[master]: soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command
by Sridhar Siricilla (Code Review) 15 Mar '20

15 Mar '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37283 ) Change subject: soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command ...................................................................... soc/intel/common/block/cse: Modify handling of HMRFPO_ENABLE command Below changes have been done in the send_hmrfpo_enable_msg(): 1. Allow execution of HMRFPO_ENABLE command only when CSE's operation mode is Temp Disable Mode. 2. Add check for response status. 3. Add description for the send_hmrfpo_enable_msg() The HMRFPO (Host ME Region Flash Protection Override) mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks the CSE region to perfom updates to it.This command is only valid before EOP. When MRP feature is enabled, procedure to place CSE in HMRFPO mode: 1. Ensure CSE to boot from BP1. When CSE boots from BP1, it will have opmode: Temp Disable Mode. 2. Send HMRFPO_ENABLE command to CSE. Then, CSE enters HMRFPO mode. The MRP feature enables CSE FW to support redundant boot partitions, and allow CSE to operate with 'Temporary Disable Mode'. The feature is enabled through FIT settings during build phase. Also, CSE can boot from either BP1 or BP2. CSE Image Layout with MRP enabled: = [RO] + [RW + DATA PART] = [BP1] + [BP2 + BP3 + DATA PART] Here, BP1 is replica of BP2, and the BP1 will be CSE's RO partition and [BP2 + BP3 + DATA PART] together will represent CSE's RW partition. Existing CSE Image Layout without MRP feature: = BP2 + BP3 + DATA PART Change-Id: I7c87998fa105947e5ba4638a8e68625e46703448 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 24 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37283/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 46ad8ce..b60d888 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -659,15 +659,13 @@ printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); hfs1.data = me_read_config32(PCI_ME_HFSTS1); + /* * This command can be run only if: - * - Working state is normal and - * - Operation mode is normal or temporary disable mode. + * - Operation mode is temporary disable mode. */ - if (hfs1.fields.working_state != ME_HFS_CWS_NORMAL || - (hfs1.fields.operation_mode != ME_HFS_MODE_NORMAL && - hfs1.fields.operation_mode != ME_HFS_MODE_TEMP_DISABLE)) { - printk(BIOS_ERR, "HECI: ME not in required Mode\n"); + if (hfs1.fields.operation_mode != ME_HFS_MODE_TEMP_DISABLE) { + printk(BIOS_ERR, "HECI: ME is not in expected mode/state(0x%x)\n", hfs1.data); goto failed; } @@ -679,6 +677,12 @@ printk(BIOS_ERR, "HECI: Resp Failed:%d\n", resp.hdr.result); goto failed; } + + if (resp.status) { + printk(BIOS_ERR, "HECI: Enable Failed, resp status:%d\n", resp.status); + goto failed; + } + return 1; failed: diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 3c00b87..53f5493 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -128,8 +128,20 @@ int send_heci_reset_req_message(uint8_t rst_type); /* - * Send HMRFPO_ENABLE command. - * returns 0 on failure and 1 on success. + * Sends HMRFPO_ENABLE command. + * HMRFPO - Host ME Region Flash Protection Override. + * When MRP feature is enabled, procedure to place CSE in HMRFPO (SECOVER_MEI_MSG) mode: + * 1. Ensure CSE boots from BP1(RO). + * - Send set_next_boot_partition(BP1) + * - Issue CSE Only Reset + * 2. Send HMRFPO_ENABLE command to CSE. Further, no reset is required. + * + * The HMRFPO mode prevents CSE to execute SPI I/O cycles to CSE region, and unlocks + * the CSE region to perfom updates to it. + * This command is only valid before EOP. + * + * Returns 0 on failure to send heci command and to enable hmrfpo mode, and 1 on success. + * */ int send_hmrfpo_enable_msg(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/37283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c87998fa105947e5ba4638a8e68625e46703448 Gerrit-Change-Number: 37283 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

8 45

Change in coreboot[master]: cpu/intel/model_2065x: Add missing CPU IDs
by Angel Pons (Code Review) 15 Mar '20

15 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38943 ) Change subject: cpu/intel/model_2065x: Add missing CPU IDs ...................................................................... cpu/intel/model_2065x: Add missing CPU IDs The missing CPU IDs were found on CPU-World's database: - 0x20650: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132688 - 0x20651: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132689 - 0x20652: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132690 - 0x20654: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132692 - 0x20655: http://www.cpu-world.com/cgi-bin/CPUID.pl?SIGNATURE=132693 Note that these CPUs are not Nehalem, but rather Arrandale on laptops and Clarksdale on desktops, so also update the comments accordingly. Change-Id: I285961b62b9a8ada5a1659cd9ad75f7075259664 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_2065x/model_2065x_init.c 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/38943/1 diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index b736943..93fcc46 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -342,9 +342,13 @@ .init = model_2065x_init, }; +/* Arrandale / Clarksdale CPU IDs */ static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x20652 }, /* Intel Nehalem */ - { X86_VENDOR_INTEL, 0x20655 }, /* Intel Nehalem */ + { X86_VENDOR_INTEL, 0x20650 }, + { X86_VENDOR_INTEL, 0x20651 }, + { X86_VENDOR_INTEL, 0x20652 }, + { X86_VENDOR_INTEL, 0x20654 }, + { X86_VENDOR_INTEL, 0x20655 }, { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/38943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I285961b62b9a8ada5a1659cd9ad75f7075259664 Gerrit-Change-Number: 38943 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

6 9

Change in coreboot[master]: treewide: Replace uses of "Nehalem"
by Angel Pons (Code Review) 15 Mar '20

15 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38942 ) Change subject: treewide: Replace uses of "Nehalem" ...................................................................... treewide: Replace uses of "Nehalem" The code in coreboot is actually for the Arrandale processors, which are a MCM (Multi-Chip Module) with two different dies: - Hillel: 32nm Westmere dual-core CPU - Ironlake: 45nm northbridge with integrated graphics This has nothing to do with the older, single-die Nehalem processors. Therefore, replace the references to Nehalem with the correct names. Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/common/fsb.c M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_2065x/model_2065x.h M src/drivers/intel/gma/Kconfig M src/include/cpu/intel/em64t101_save_state.h M src/northbridge/intel/ironlake/northbridge.c M src/security/tpm/Kconfig 7 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/38942/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 726ab1c..3dfcd0b 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -48,7 +48,7 @@ *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; - case 0x25: /* Nehalem BCLK fixed at 133MHz */ + case 0x25: /* Arrandale BCLK fixed at 133MHz */ *fsb = 133; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 1868876..af2606c 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -338,5 +338,5 @@ } struct chip_operations cpu_intel_model_2065x_ops = { - CHIP_NAME("Intel Nehalem CPU") + CHIP_NAME("Intel Arrandale CPU") }; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 730ab35..0a07f3c 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -15,7 +15,7 @@ #ifndef _CPU_INTEL_MODEL_2065X_H #define _CPU_INTEL_MODEL_2065X_H -/* Nehalem bus clock is fixed at 133MHz */ +/* Arrandale bus clock is fixed at 133MHz */ #define IRONLAKE_BCLK 133 #define MSR_CORE_THREAD_COUNT 0x35 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 87889d3..c35e44e 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -39,7 +39,7 @@ To be set by northbridge or mainboard Kconfig. For most platforms, there is no choice, i.e. for i945 and gm45 the SSC reference always differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz - DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's + DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's the same frequency for SSC/non-SSC (120MHz). The only, currently supported platform with a choice seems to be Pineview, where the alternative is 100MHz vs. the default 96MHz. diff --git a/src/include/cpu/intel/em64t101_save_state.h b/src/include/cpu/intel/em64t101_save_state.h index 7493c85..5d3f9ed 100644 --- a/src/include/cpu/intel/em64t101_save_state.h +++ b/src/include/cpu/intel/em64t101_save_state.h @@ -20,7 +20,7 @@ /* Intel Revision 30101 SMM State-Save Area * The following processor architectures use this: - * - Nehalem + * - Westmere * - SandyBridge * - IvyBridge * - Haswell diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index fe8eed3..91bcc11 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -263,10 +263,10 @@ .ops_pci = &intel_pci_ops, }; -static const struct pci_driver mc_driver_44 __pci_driver = { +static const struct pci_driver mc_driver_ard __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x0044, /* Nehalem */ + .device = 0x0044, /* Arrandale DRAM controller */ }; static struct device_operations cpu_bus_ops = { @@ -288,7 +288,7 @@ } struct chip_operations northbridge_intel_ironlake_ops = { - CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") + CHIP_NAME("Intel i7 (Arrandale) integrated Northbridge") .enable_dev = enable_dev, .init = ironlake_init, }; diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 95c0bb9..fbe1735 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -99,7 +99,7 @@ Select this to ignore POSTINIT INVALID return codes on TPM startup. This is useful on platforms where a previous stage issued a TPM startup. Examples of use cases are Intel TXT - or VBOOT on the Intel Nehalem northbridge which issues a + or VBOOT on the Intel Arrandale processor, which issues a CPU-only reset during the romstage. endmenu # Trusted Platform Module (tpm) -- To view, visit https://review.coreboot.org/c/coreboot/+/38942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c10a2618c519d2411211b9b8f66d24f0018f908 Gerrit-Change-Number: 38942 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: nb/intel/nehalem: Rename to ironlake
by Angel Pons (Code Review) 15 Mar '20

15 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38941 ) Change subject: nb/intel/nehalem: Rename to ironlake ...................................................................... nb/intel/nehalem: Rename to ironlake The code is for Arrandale CPUs, whose System Agent is Ironlake. Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/Makefile.inc M src/cpu/intel/model_2065x/acpi.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_2065x/model_2065x_init.c M src/cpu/x86/Kconfig M src/drivers/intel/gma/Kconfig M src/mainboard/lenovo/t410/Kconfig M src/mainboard/lenovo/t410/devicetree.cb M src/mainboard/lenovo/t410/dsdt.asl M src/mainboard/lenovo/t410/romstage.c M src/mainboard/lenovo/t410/smihandler.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/lenovo/x201/devicetree.cb M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x201/smihandler.c M src/mainboard/packardbell/ms2290/Kconfig M src/mainboard/packardbell/ms2290/devicetree.cb M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/packardbell/ms2290/smihandler.c R src/northbridge/intel/ironlake/Kconfig R src/northbridge/intel/ironlake/Makefile.inc R src/northbridge/intel/ironlake/acpi.c R src/northbridge/intel/ironlake/acpi/hostbridge.asl R src/northbridge/intel/ironlake/acpi/ironlake.asl R src/northbridge/intel/ironlake/bootblock.c R src/northbridge/intel/ironlake/chip.h R src/northbridge/intel/ironlake/early_init.c R src/northbridge/intel/ironlake/finalize.c R src/northbridge/intel/ironlake/gma.c R src/northbridge/intel/ironlake/ironlake.h R src/northbridge/intel/ironlake/memmap.c R src/northbridge/intel/ironlake/northbridge.c R src/northbridge/intel/ironlake/raminit.c R src/northbridge/intel/ironlake/raminit.h R src/northbridge/intel/ironlake/raminit_tables.c R src/northbridge/intel/ironlake/raminit_tables.h R src/northbridge/intel/ironlake/romstage.c R src/northbridge/intel/ironlake/smi.c M src/southbridge/intel/common/firmware/Kconfig M src/southbridge/intel/ibexpeak/early_cir.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/smihandler.c 46 files changed, 76 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/38941/1 diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 904b61bb..1849f19 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -10,7 +10,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 -subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x +subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c index 51acc278..1868876 100644 --- a/src/cpu/intel/model_2065x/acpi.c +++ b/src/cpu/intel/model_2065x/acpi.c @@ -216,7 +216,7 @@ /* Max Non-Turbo Ratio */ ratio_max = (msr.lo >> 8) & 0xff; } - clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3; + clock_max = ratio_max * IRONLAKE_BCLK + ratio_max / 3; /* Calculate CPU TDP in mW */ power_max = 25000; @@ -277,7 +277,7 @@ /* Calculate power at this ratio */ power = calculate_power(power_max, ratio_max, ratio); - clock = ratio * NEHALEM_BCLK + ratio / 3; + clock = ratio * IRONLAKE_BCLK + ratio / 3; acpigen_write_PSS_package( clock, /*MHz*/ diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f6982d9..730ab35 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -16,7 +16,7 @@ #define _CPU_INTEL_MODEL_2065X_H /* Nehalem bus clock is fixed at 133MHz */ -#define NEHALEM_BCLK 133 +#define IRONLAKE_BCLK 133 #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_FEATURE_CONFIG 0x13c diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index a9c28f6..b736943 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -197,7 +197,7 @@ wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK); } static void set_energy_perf_bias(u8 policy) diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 76446a0..f6dfca3 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -140,7 +140,7 @@ bool default y if NORTHBRIDGE_INTEL_I945 default y if NORTHBRIDGE_INTEL_GM45 - default y if NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_IRONLAKE default n config SERIALIZED_SMM_INITIALIZATION diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index 2071351..87889d3 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -66,7 +66,7 @@ config GFX_GMA def_bool y depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ - || NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE \ + || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ || NORTHBRIDGE_INTEL_HASWELL \ || SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || SOC_INTEL_APOLLOLAKE \ || SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE \ @@ -83,7 +83,7 @@ config GFX_GMA_INTERNAL_IS_LVDS bool depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT - default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_NEHALEM + default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE default n if GFX_GMA @@ -99,7 +99,7 @@ default "Skylake" if SOC_INTEL_SKYLAKE || SOC_INTEL_KABYLAKE || \ SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL - default "Ironlake" if NORTHBRIDGE_INTEL_NEHALEM || NORTHBRIDGE_INTEL_SANDYBRIDGE + default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X config GFX_GMA_INTERNAL_PORT diff --git a/src/mainboard/lenovo/t410/Kconfig b/src/mainboard/lenovo/t410/Kconfig index 5d60565..86cfce8 100644 --- a/src/mainboard/lenovo/t410/Kconfig +++ b/src/mainboard/lenovo/t410/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/t410/devicetree.cb b/src/mainboard/lenovo/t410/devicetree.cb index 808e057..e18ec38 100644 --- a/src/mainboard/lenovo/t410/devicetree.cb +++ b/src/mainboard/lenovo/t410/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" diff --git a/src/mainboard/lenovo/t410/dsdt.asl b/src/mainboard/lenovo/t410/dsdt.asl index 4f67bd8..f8e989a 100644 --- a/src/mainboard/lenovo/t410/dsdt.asl +++ b/src/mainboard/lenovo/t410/dsdt.asl @@ -45,7 +45,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <northbridge/intel/ironlake/acpi/ironlake.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/lenovo/t410/romstage.c b/src/mainboard/lenovo/t410/romstage.c index 4908ec5..f15a919 100644 --- a/src/mainboard/lenovo/t410/romstage.c +++ b/src/mainboard/lenovo/t410/romstage.c @@ -20,7 +20,7 @@ #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/pch.h> #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ diff --git a/src/mainboard/lenovo/t410/smihandler.c b/src/mainboard/lenovo/t410/smihandler.c index 91cb0ce..70a9e5d 100644 --- a/src/mainboard/lenovo/t410/smihandler.c +++ b/src/mainboard/lenovo/t410/smihandler.c @@ -19,7 +19,7 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a94d24e..42cf8f9 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select EC_LENOVO_PMH7 select EC_LENOVO_H8 diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index 3ababc9..ba4434c 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 4f67bd8..f8e989a 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -45,7 +45,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <northbridge/intel/ironlake/acpi/ironlake.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 4cd3bde..ebfe7a8 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <ec/acpi/ec.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/bd82x6x/pch.h> #include "dock.h" #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index aec63db..8bf6f90 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -21,7 +21,7 @@ #include <ec/acpi/ec.h> #include <southbridge/intel/ibexpeak/pch.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> const struct southbridge_usb_port mainboard_usb_ports[] = { /* Enabled, Current table lookup index, OC map */ diff --git a/src/mainboard/lenovo/x201/smihandler.c b/src/mainboard/lenovo/x201/smihandler.c index 91cb0ce..70a9e5d 100644 --- a/src/mainboard/lenovo/x201/smihandler.c +++ b/src/mainboard/lenovo/x201/smihandler.c @@ -19,7 +19,7 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> #include <delay.h> diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 8194002..4fc971f 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -3,7 +3,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SYSTEM_TYPE_LAPTOP - select NORTHBRIDGE_INTEL_NEHALEM + select NORTHBRIDGE_INTEL_IRONLAKE select SOUTHBRIDGE_INTEL_IBEXPEAK select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/packardbell/ms2290/devicetree.cb b/src/mainboard/packardbell/ms2290/devicetree.cb index bf1c171..21b6a6d 100644 --- a/src/mainboard/packardbell/ms2290/devicetree.cb +++ b/src/mainboard/packardbell/ms2290/devicetree.cb @@ -15,7 +15,7 @@ ## GNU General Public License for more details. ## -chip northbridge/intel/nehalem +chip northbridge/intel/ironlake # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index bbd2b29..e53d728 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -39,7 +39,7 @@ Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <northbridge/intel/ironlake/acpi/ironlake.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 169b0ac..805eecb 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -18,7 +18,7 @@ #include <device/device.h> #include <arch/io.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> #include <drivers/intel/gma/int15.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 1f9d229..03ea86d 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <southbridge/intel/ibexpeak/pch.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> /* Seems copied from Lenovo Thinkpad x201, might be wrong */ const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index bc5067b..2d77564 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -19,7 +19,7 @@ #include <device/pci_ops.h> #include <southbridge/intel/ibexpeak/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <ec/acpi/ec.h> void mainboard_smi_gpi(u32 gpi_sts) diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/ironlake/Kconfig similarity index 95% rename from src/northbridge/intel/nehalem/Kconfig rename to src/northbridge/intel/ironlake/Kconfig index a119b81..4f76dab 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/ironlake/Kconfig @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -config NORTHBRIDGE_INTEL_NEHALEM +config NORTHBRIDGE_INTEL_IRONLAKE bool select CPU_INTEL_MODEL_2065X select VGA @@ -22,7 +22,7 @@ select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP -if NORTHBRIDGE_INTEL_NEHALEM +if NORTHBRIDGE_INTEL_IRONLAKE config VBOOT select VBOOT_MUST_REQUEST_DISPLAY diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc similarity index 94% rename from src/northbridge/intel/nehalem/Makefile.inc rename to src/northbridge/intel/ironlake/Makefile.inc index 225f0ce..1fde37d 100644 --- a/src/northbridge/intel/nehalem/Makefile.inc +++ b/src/northbridge/intel/ironlake/Makefile.inc @@ -13,7 +13,7 @@ # GNU General Public License for more details. # -ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y) +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE),y) bootblock-y += bootblock.c diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/ironlake/acpi.c similarity index 98% rename from src/northbridge/intel/nehalem/acpi.c rename to src/northbridge/intel/ironlake/acpi.c index 462cdc0..aa83369 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/ironlake/acpi.c @@ -22,7 +22,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include "nehalem.h" +#include "ironlake.h" unsigned long acpi_fill_mcfg(unsigned long current) { diff --git a/src/northbridge/intel/nehalem/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl similarity index 100% rename from src/northbridge/intel/nehalem/acpi/hostbridge.asl rename to src/northbridge/intel/ironlake/acpi/hostbridge.asl diff --git a/src/northbridge/intel/nehalem/acpi/nehalem.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl similarity index 97% rename from src/northbridge/intel/nehalem/acpi/nehalem.asl rename to src/northbridge/intel/ironlake/acpi/ironlake.asl index 404801e..659234b4 100644 --- a/src/northbridge/intel/nehalem/acpi/nehalem.asl +++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -#include "../nehalem.h" +#include "../ironlake.h" #include "hostbridge.asl" #include <southbridge/intel/common/rcba.h> diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c similarity index 100% rename from src/northbridge/intel/nehalem/bootblock.c rename to src/northbridge/intel/ironlake/bootblock.c diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/ironlake/chip.h similarity index 89% rename from src/northbridge/intel/nehalem/chip.h rename to src/northbridge/intel/ironlake/chip.h index a9d136b..dad03da 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/ironlake/chip.h @@ -13,8 +13,8 @@ * GNU General Public License for more details. */ -#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H -#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H +#ifndef NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H +#define NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H #include <drivers/intel/gma/i915.h> @@ -25,7 +25,7 @@ * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ -struct northbridge_intel_nehalem_config { +struct northbridge_intel_ironlake_config { u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ @@ -48,4 +48,4 @@ u16 pci_mmio_size; }; -#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ +#endif /* NORTHBRIDGE_INTEL_IRONLAKE_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/ironlake/early_init.c similarity index 96% rename from src/northbridge/intel/nehalem/early_init.c rename to src/northbridge/intel/ironlake/early_init.c index a809121..fe4ad7f 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -26,9 +26,9 @@ #include <cpu/intel/turbo.h> #include <arch/cpu.h> -#include "nehalem.h" +#include "ironlake.h" -static void nehalem_setup_bars(void) +static void ironlake_setup_bars(void) { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); @@ -114,7 +114,7 @@ wrmsr(IA32_MISC_ENABLE, m); } -void nehalem_early_initialization(int chipset_type) +void ironlake_early_initialization(int chipset_type) { u32 capid0_a; u8 reg8; @@ -126,14 +126,14 @@ reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3); reg8 &= ~7; /* Clear 2:0 */ - if (chipset_type == NEHALEM_MOBILE) + if (chipset_type == IRONLAKE_MOBILE) reg8 |= 1; /* Set bit 0 */ pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8); } /* Setup all BARs required for early PCIe and raminit */ - nehalem_setup_bars(); + ironlake_setup_bars(); s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3); diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/ironlake/finalize.c similarity index 94% rename from src/northbridge/intel/nehalem/finalize.c rename to src/northbridge/intel/ironlake/finalize.c index c03b067..f76124b 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/ironlake/finalize.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ -#include "nehalem.h" +#include "ironlake.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) -void intel_nehalem_finalize_smm(void) +void intel_ironlake_finalize_smm(void) { MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/ironlake/gma.c similarity index 96% rename from src/northbridge/intel/nehalem/gma.c rename to src/northbridge/intel/ironlake/gma.c index d717e48..27c0827 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/ironlake/gma.c @@ -33,7 +33,7 @@ #include <types.h> #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" /* some vga option roms are used for several chipsets but they only have one * PCI ID in their header. If we encounter such an option rom, we need to do @@ -93,7 +93,7 @@ static void gma_pm_init_post_vbios(struct device *dev) { - struct northbridge_intel_nehalem_config *conf = dev->chip_info; + struct northbridge_intel_ironlake_config *conf = dev->chip_info; u32 reg32; printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n"); @@ -177,7 +177,7 @@ if (!acpi_is_wakeup_s3() && CONFIG(MAINBOARD_USE_LIBGFXINIT)) { - struct northbridge_intel_nehalem_config *conf = dev->chip_info; + struct northbridge_intel_ironlake_config *conf = dev->chip_info; int lightup_ok; printk(BIOS_SPEW, "Initializing VGA without OPROM."); @@ -223,7 +223,7 @@ if (!dev) { return NULL; } - struct northbridge_intel_nehalem_config *chip = dev->chip_info; + struct northbridge_intel_ironlake_config *chip = dev->chip_info; return &chip->gfx; } diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/ironlake/ironlake.h similarity index 94% rename from src/northbridge/intel/nehalem/nehalem.h rename to src/northbridge/intel/ironlake/ironlake.h index 493c5b1..aa8cb7f 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -15,8 +15,8 @@ * GNU General Public License for more details. */ -#ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ +#ifndef __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ +#define __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ #ifndef __ASSEMBLER__ @@ -99,9 +99,9 @@ #define D1F0_VC0RCTL 0x114 /* Chipset types */ -#define NEHALEM_MOBILE 0 -#define NEHALEM_DESKTOP 1 -#define NEHALEM_SERVER 2 +#define IRONLAKE_MOBILE 0 +#define IRONLAKE_DESKTOP 1 +#define IRONLAKE_SERVER 2 /* Device ID for SandyBridge and IvyBridge */ #define BASE_REV_SNB 0x00 @@ -249,14 +249,14 @@ #define PCI_DEVICE_ID_SB 0x0104 #define PCI_DEVICE_ID_IB 0x0154 -void intel_nehalem_finalize_smm(void); +void intel_ironlake_finalize_smm(void); int bridge_silicon_revision(void); -void nehalem_early_initialization(int chipset_type); -void nehalem_late_initialization(void); +void ironlake_early_initialization(int chipset_type); +void ironlake_late_initialization(void); void mainboard_pre_raminit(void); void mainboard_get_spd_map(u8 *spd_addrmap); #endif #endif -#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ +#endif /* __NORTHBRIDGE_INTEL_IRONLAKE_IRONLAKE_H__ */ diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/ironlake/memmap.c similarity index 98% rename from src/northbridge/intel/nehalem/memmap.c rename to src/northbridge/intel/ironlake/memmap.c index 5de4b80..b2d61fe 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -23,7 +23,7 @@ #include <cpu/x86/smm.h> #include <program_loading.h> #include <cpu/intel/smm_reloc.h> -#include "nehalem.h" +#include "ironlake.h" static uintptr_t smm_region_start(void) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c similarity index 97% rename from src/northbridge/intel/nehalem/northbridge.c rename to src/northbridge/intel/ironlake/northbridge.c index 1718307..fe8eed3 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -26,7 +26,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" #include <cpu/intel/smm_reloc.h> static int bridge_revision_id = -1; @@ -228,7 +228,7 @@ } /* Disable unused PEG devices based on devicetree before PCI enumeration */ -static void nehalem_init(void *const chip_info) +static void ironlake_init(void *const chip_info) { u32 deven_mask = UINT32_MAX; const struct device *dev; @@ -287,8 +287,8 @@ } } -struct chip_operations northbridge_intel_nehalem_ops = { +struct chip_operations northbridge_intel_ironlake_ops = { CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") .enable_dev = enable_dev, - .init = nehalem_init, + .init = ironlake_init, }; diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/ironlake/raminit.c similarity index 99% rename from src/northbridge/intel/nehalem/raminit.c rename to src/northbridge/intel/ironlake/raminit.c index 7735522..1bd7941 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -40,7 +40,7 @@ #include <types.h> #include "chip.h" -#include "nehalem.h" +#include "ironlake.h" #include "raminit.h" #include "raminit_tables.h" @@ -1367,7 +1367,7 @@ static unsigned int get_mmio_size(void) { const struct device *dev; - const struct northbridge_intel_nehalem_config *cfg = NULL; + const struct northbridge_intel_ironlake_config *cfg = NULL; dev = pcidev_path_on_root(HOST_BRIDGE); if (dev) diff --git a/src/northbridge/intel/nehalem/raminit.h b/src/northbridge/intel/ironlake/raminit.h similarity index 97% rename from src/northbridge/intel/nehalem/raminit.h rename to src/northbridge/intel/ironlake/raminit.h index 9a200d4..1a55407 100644 --- a/src/northbridge/intel/nehalem/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -16,7 +16,7 @@ #ifndef RAMINIT_H #define RAMINIT_H -#include "nehalem.h" +#include "ironlake.h" void chipset_init(const int s3resume); /* spd_addrmap is array of 4 elements: diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/ironlake/raminit_tables.c similarity index 100% rename from src/northbridge/intel/nehalem/raminit_tables.c rename to src/northbridge/intel/ironlake/raminit_tables.c diff --git a/src/northbridge/intel/nehalem/raminit_tables.h b/src/northbridge/intel/ironlake/raminit_tables.h similarity index 100% rename from src/northbridge/intel/nehalem/raminit_tables.h rename to src/northbridge/intel/ironlake/raminit_tables.h diff --git a/src/northbridge/intel/nehalem/romstage.c b/src/northbridge/intel/ironlake/romstage.c similarity index 92% rename from src/northbridge/intel/nehalem/romstage.c rename to src/northbridge/intel/ironlake/romstage.c index eceb8c2..fdd71b4 100644 --- a/src/northbridge/intel/nehalem/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -22,12 +22,12 @@ #include <cpu/x86/lapic.h> #include <timestamp.h> #include <romstage_handoff.h> -#include "nehalem.h" +#include "ironlake.h" #include <arch/romstage.h> #include <device/pci_def.h> #include <device/device.h> -#include <northbridge/intel/nehalem/chip.h> -#include <northbridge/intel/nehalem/raminit.h> +#include <northbridge/intel/ironlake/chip.h> +#include <northbridge/intel/ironlake/raminit.h> #include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> @@ -44,7 +44,7 @@ enable_lapic(); /* TODO, make this configurable */ - nehalem_early_initialization(NEHALEM_MOBILE); + ironlake_early_initialization(IRONLAKE_MOBILE); early_pch_init(); diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/ironlake/smi.c similarity index 96% rename from src/northbridge/intel/nehalem/smi.c rename to src/northbridge/intel/ironlake/smi.c index 8c19852..64c1fa5 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/ironlake/smi.c @@ -17,7 +17,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include "nehalem.h" +#include "ironlake.h" #include <cpu/intel/smm_reloc.h> diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index eb63d34..134f780 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -59,7 +59,7 @@ config CHECK_ME bool "Verify the integrity of the supplied ME/TXE firmware" default n - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ @@ -71,7 +71,7 @@ config USE_ME_CLEANER bool "Strip down the Intel ME/TXE firmware" - depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \ + depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ NORTHBRIDGE_INTEL_HASWELL || \ SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \ diff --git a/src/southbridge/intel/ibexpeak/early_cir.c b/src/southbridge/intel/ibexpeak/early_cir.c index 8d7a918..9aac07b 100644 --- a/src/southbridge/intel/ibexpeak/early_cir.c +++ b/src/southbridge/intel/ibexpeak/early_cir.c @@ -14,7 +14,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include "pch.h" /* This sets up magic Chipset Initialization Registers */ @@ -53,7 +53,7 @@ /* Intel 5 Series Chipset and Intel 3400 Series Chipset External Design Specification (EDS) 13.8.1.1 */ - if (chipset_type == NEHALEM_DESKTOP) + if (chipset_type == IRONLAKE_DESKTOP) pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3); pci_write_config8(PCH_LPC_DEV, CIR4, 0x45); diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index 56331cc..b455cef 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -19,7 +19,7 @@ #include <stdint.h> #include <device/pci_ops.h> #include <device/smbus_host.h> -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> @@ -47,7 +47,7 @@ early_gpio_init(); enable_smbus(); /* TODO, make this configurable */ - pch_setup_cir(NEHALEM_MOBILE); + pch_setup_cir(IRONLAKE_MOBILE); southbridge_configure_default_intmap(); pch_default_disable(); early_usb_init(mainboard_usb_ports); diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 3988188..e670c9a 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -34,7 +34,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/ironlake/ironlake.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmutil.h> @@ -185,6 +185,6 @@ { intel_me_finalize_smm(); intel_pch_finalize_smm(); - intel_nehalem_finalize_smm(); + intel_ironlake_finalize_smm(); intel_model_2065x_finalize_smm(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/38941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc Gerrit-Change-Number: 38941 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

8 20

Change in coreboot[master]: [WIP] nb/intel/haswell: Do some cosmetic fixes
by Angel Pons (Code Review) 15 Mar '20

15 Mar '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38434 ) Change subject: [WIP] nb/intel/haswell: Do some cosmetic fixes ...................................................................... [WIP] nb/intel/haswell: Do some cosmetic fixes - Reformat some lines of code - Put names to the MCHBAR registers - Rewrite a few comments - Rewrite some hex constants It does not change the binary of Asrock B85M Pro4. Change-Id: I926289304acb834f9b13cd7902801798f8ee478a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/haswell/early_init.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/haswell.h A src/northbridge/intel/haswell/mchbar_regs.h M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/raminit.c 10 files changed, 376 insertions(+), 353 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/38434/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index d92e858..c6aaa86 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -38,35 +38,35 @@ pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - // MMCFG not supported or not enabled. + /* MMCFG not supported or not enabled. */ if (!(pciexbar_reg & (1 << 0))) return current; mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB + case 0: /* 256MB */ pciexbar = pciexbar_reg & mask; max_buses = 256; break; - case 1: // 128M + case 1: /* 128M */ mask |= (1 << 27); pciexbar = pciexbar_reg & mask; max_buses = 128; break; - case 2: // 64M + case 2: /* 64M */ mask |= (1 << 27) | (1 << 26); pciexbar = pciexbar_reg & mask; max_buses = 64; break; - default: // RSVD + default: /* RSVD */ return current; } if (!pciexbar) return current; - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, - pciexbar, 0x0, 0x0, max_buses - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, + max_buses - 1); return current; } @@ -80,8 +80,8 @@ const bool vtvc0en = MCHBAR32(VTVC0BAR) & 0x1; /* iGFX has to be enabled; GFXVTBAR set, enabled, in 32-bit space */ - if (igfx_dev && igfx_dev->enabled && gfxvtbar - && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten && !MCHBAR32(GFXVTBAR + 4)) { + const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar); @@ -92,24 +92,23 @@ /* VTVC0BAR has to be set, enabled, and in 32-bit space */ if (vtvc0bar && vtvc0en && !MCHBAR32(VTVC0BAR + 4)) { + const unsigned long tmp = current; - current += acpi_create_dmar_drhd(current, - DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); + current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); + size_t i; for (i = 0; i < 8; ++i) - current += acpi_create_dmar_ds_msi_hpet(current, - 0, PCH_HPET_PCI_BUS, - PCH_HPET_PCI_SLOT, i); + current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, + PCH_HPET_PCI_SLOT, i); acpi_dmar_drhd_fixup(tmp, current); } return current; } -unsigned long northbridge_write_acpi_tables(struct device *const dev, - unsigned long current, +unsigned long northbridge_write_acpi_tables(struct device *const dev, unsigned long current, struct acpi_rsdp *const rsdp) { /* Create DMAR table only if we have VT-d capability. */ diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 666bda2..5caede5 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -28,21 +28,21 @@ { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0, 0), EPBAR, DEFAULT_EPBAR | 1); + pci_write_config32(PCI_DEV(0, 0, 0), EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0, 0), MCHBAR, DEFAULT_MCHBAR | 1); + pci_write_config32(PCI_DEV(0, 0, 0), MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); + pci_write_config32(PCI_DEV(0, 0, 0), DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0, 0), DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); - pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); + pci_write_config8(PCI_DEV(0, 0, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0, 0), PAM1, 0x33); + pci_write_config8(PCI_DEV(0, 0, 0), PAM2, 0x33); + pci_write_config8(PCI_DEV(0, 0, 0), PAM3, 0x33); + pci_write_config8(PCI_DEV(0, 0, 0), PAM4, 0x33); + pci_write_config8(PCI_DEV(0, 0, 0), PAM5, 0x33); + pci_write_config8(PCI_DEV(0, 0, 0), PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); } @@ -55,8 +55,7 @@ printk(BIOS_DEBUG, "Initializing IGD...\n"); - igd_enabled = !!(pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) - & DEVEN_D2EN); + igd_enabled = !!(pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) & DEVEN_D2EN); ggc = pci_read_config16(PCI_DEV(0, 0, 0), GGC); ggc &= ~0x3f8; @@ -64,8 +63,7 @@ ggc |= GGC_GTT_2MB | GGC_IGD_MEM_IN_32MB_UNITS(1); ggc &= ~GGC_DISABLE_VGA_IO_DECODE; } else { - ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | - GGC_DISABLE_VGA_IO_DECODE; + ggc |= GGC_GTT_0MB | GGC_IGD_MEM_IN_32MB_UNITS(0) | GGC_DISABLE_VGA_IO_DECODE; } pci_write_config16(PCI_DEV(0, 0, 0), GGC, ggc); @@ -104,10 +102,9 @@ printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev)); /* - * The PEG device is hidden while the MRC runs. This is because the - * MRC makes configurations that are not ideal if it sees a VGA - * device in a PEG slot, and it locks registers preventing changes - * to these configurations. + * Hide the PEG device while the MRC runs. This is because the MRC makes + * configurations that are not ideal if it sees a VGA device in a PEG slot, + * and it locks registers preventing changes to these configurations. */ pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0); peg_hidden[PCI_FUNC(dev)] = true; @@ -135,8 +132,10 @@ if (deven & DEVEN_D1F2EN) start_peg2_link_training(PCI_DEV(0, 1, 2)); + if (deven & DEVEN_D1F1EN) start_peg2_link_training(PCI_DEV(0, 1, 1)); + if (deven & DEVEN_D1F0EN) start_peg2_link_training(PCI_DEV(0, 1, 0)); } @@ -146,27 +145,27 @@ u32 reg32; /* Erratum workarounds */ - reg32 = MCHBAR32(0x5f00); - reg32 |= (1 << 9)|(1 << 10); - MCHBAR32(0x5f00) = reg32; + reg32 = MCHBAR32(SAPMCTL); + reg32 |= (1 << 9) | (1 << 10); + MCHBAR32(SAPMCTL) = reg32; /* Enable SA Clock Gating */ - reg32 = MCHBAR32(0x5f00); - MCHBAR32(0x5f00) = reg32 | 1; + reg32 = MCHBAR32(SAPMCTL); + MCHBAR32(SAPMCTL) = reg32 | 1; /* GPU RC6 workaround for sighting 366252 */ - reg32 = MCHBAR32(0x5d14); + reg32 = MCHBAR32(SSKPD + 4); reg32 |= (1UL << 31); - MCHBAR32(0x5d14) = reg32; + MCHBAR32(SSKPD + 4) = reg32; - /* VLW */ + /* VLW (Virtual Legacy Wire?) */ reg32 = MCHBAR32(0x6120); reg32 &= ~(1 << 0); MCHBAR32(0x6120) = reg32; - reg32 = MCHBAR32(0x5418); + reg32 = MCHBAR32(INTRDIRCTL); reg32 |= (1 << 4) | (1 << 5); - MCHBAR32(0x5418) = reg32; + MCHBAR32(INTRDIRCTL) = reg32; } static void haswell_setup_iommu(void) @@ -176,20 +175,21 @@ if (capid0_a & VTD_DISABLE) return; - /* setup BARs: zeroize top 32 bits; set enable bit */ + /* Setup BARs: zeroize top 32 bits; set enable bit */ MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32; - MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; + MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1; MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32; - MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; + MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1; - /* set L3HIT2PEND_DIS, lock GFXVTBAR policy cfg registers */ + /* Set L3HIT2PEND_DIS, lock GFXVTBAR policy cfg registers */ u32 reg32; reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS)); - write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), - reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); - /* clear SPCAPCTRL */ + write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS); + + /* Clear SPCAPCTRL */ reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL; - /* set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy cfg registers */ + + /* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy cfg registers */ write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV); } diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index ca36634..e147bcc 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -33,19 +33,19 @@ pci_or_config32(PCI_DEV_HSW, 0xb8, 1 << 0); /* TSEGMB */ pci_or_config32(PCI_DEV_HSW, 0xbc, 1 << 0); /* TOLUD */ - MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ - MCHBAR32_OR(0x5f00, 1UL << 31); /* SA PM */ - MCHBAR32_OR(0x6020, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(0x63fc, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(0x6800, 1UL << 31); - MCHBAR32_OR(0x7000, 1UL << 31); - MCHBAR32_OR(0x77fc, 1 << 0); + MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ + MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ + MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ + MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ + MCHBAR32_OR(REQLIM, 1UL << 31); + MCHBAR32_OR(DMIVCLIM, 1UL << 31); + MCHBAR32_OR(CRDTLCK, 1 << 0); /* Memory Controller Lockdown */ - MCHBAR8(0x50fc) = 0x8f; + MCHBAR8(MC_LOCK) = 0x8f; /* Read+write the following */ - MCHBAR32(0x6030) = MCHBAR32(0x6030); - MCHBAR32(0x6034) = MCHBAR32(0x6034); - MCHBAR32(0x6008) = MCHBAR32(0x6008); + MCHBAR32(VDMBDFBARKVM) = MCHBAR32(VDMBDFBARKVM); + MCHBAR32(VDMBDFBARPAVP) = MCHBAR32(VDMBDFBARPAVP); + MCHBAR32(HDAUDRID) = MCHBAR32(HDAUDRID); } diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 3132c20..b2dc880 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -97,9 +97,9 @@ { 0 }, }; -/* some vga option roms are used for several chipsets but they only have one - * PCI ID in their header. If we encounter such an option rom, we need to do - * the mapping ourselves +/* + * Some vga option roms are used for several chipsets but they only have one PCI ID in their + * header. If we encounter such an option rom, we need to do the mapping ourselves. */ u32 map_oprom_vendev(u32 vendev) @@ -129,39 +129,41 @@ return new_vendev; } -/* GTT is the Global Translation Table for the graphics pipeline. - * It is used to translate graphics addresses to physical - * memory addresses. As in the CPU, GTTs map 4K pages. - * The setgtt function adds a further bit of flexibility: - * it allows you to set a range (the first two parameters) to point - * to a physical address (third parameter);the physical address is - * incremented by a count (fourth parameter) for each GTT in the - * range. - * Why do it this way? For ultrafast startup, - * we can point all the GTT entries to point to one page, - * and set that page to 0s: - * memset(physbase, 0, 4096); - * setgtt(0, 4250, physbase, 0); - * this takes about 2 ms, and is a win because zeroing - * the page takes a up to 200 ms. - * This call sets the GTT to point to a linear range of pages - * starting at physbase. +/** FIXME: Seems to be outdated. */ +/* + * GTT is the Global Translation Table for the graphics pipeline. It is used to translate + * graphics addresses to physical memory addresses. As in the CPU, GTTs map 4K pages. + * + * The setgtt function adds a further bit of flexibility: it allows you to set a range (the + * first two parameters) to point to a physical address (third parameter); the physical address + * is incremented by a count (fourth parameter) for each GTT in the range. + * + * Why do it this way? For ultrafast startup, we can point all the GTT entries to point to one + * page, and set that page to 0s: + * + * memset(physbase, 0, 4096); + * setgtt(0, 4250, physbase, 0); + * + * this takes about 2 ms, and is a win because zeroing the page takes up to 200 ms. + * + * This call sets the GTT to point to a linear range of pages starting at physbase. */ #define GTT_PTE_BASE (2 << 20) -void -set_translation_table(int start, int end, u64 base, int inc) +void set_translation_table(int start, int end, u64 base, int inc) { int i; for (i = start; i < end; i++){ - u64 physical_address = base + i*inc; + u64 physical_address = base + i * inc; + /* swizzle the 32:39 bits to 4:11 */ u32 word = physical_address | ((physical_address >> 28) & 0xff0) | 1; - /* note: we've confirmed by checking - * the values that mrc does no - * useful setup before we run this. + + /* + * Note: we've confirmed by checking the values that mrc does no useful + * setup before we run this. */ gtt_write(GTT_PTE_BASE + i * 4, word); gtt_read(GTT_PTE_BASE + i * 4); @@ -211,6 +213,7 @@ data = gtt_read(reg); if ((data & mask) == value) return 1; + udelay(10); } @@ -261,10 +264,13 @@ /* Wait for Mailbox Ready */ gtt_poll(0x138124, (1UL << 31), (0UL << 31)); + /* Mailbox Data - RC6 VIDS */ gtt_write(0x138128, 0x00000000); + /* Mailbox Command */ gtt_write(0x138124, 0x80000004); + /* Wait for Mailbox Ready */ gtt_poll(0x138124, (1UL << 31), (0UL << 31)); @@ -291,7 +297,7 @@ gtt_write(CURBASE_IVB(pipe), 0x00000000); } - /* Disable primary plane and set surface base address*/ + /* Disable primary plane and set surface base address */ for (plane = PLANE_A; plane <= PLANE_C; plane++) { gtt_write(DSPCNTR(plane), DISPLAY_PLANE_DISABLE); gtt_write(DSPSURF(plane), 0x00000000); @@ -491,10 +497,9 @@ intel_gma_restore_opregion(); } -const struct i915_gpu_controller_info * -intel_gma_get_controller_info(void) +const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { - struct device *dev = pcidev_on_root(0x2, 0); + struct device *dev = pcidev_on_root(2, 0); if (!dev) { return NULL; } @@ -512,9 +517,8 @@ drivers_intel_gma_displays_ssdt_generate(gfx); } -static unsigned long -gma_write_acpi_tables(struct device *const dev, unsigned long current, - struct acpi_rsdp *const rsdp) +static unsigned long gma_write_acpi_tables(struct device *const dev, unsigned long current, + struct acpi_rsdp *const rsdp) { igd_opregion_t *opregion = (igd_opregion_t *)current; global_nvs_t *gnvs; @@ -538,19 +542,19 @@ } static struct pci_operations gma_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = gma_func0_init, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, .acpi_fill_ssdt_generator = gma_ssdt, - .scan_bus = 0, - .enable = 0, - .ops_pci = &gma_pci_ops, - .write_acpi_tables = gma_write_acpi_tables, + .scan_bus = NULL, + .enable = NULL, + .ops_pci = &gma_pci_ops, + .write_acpi_tables = gma_write_acpi_tables, }; static const unsigned short pci_device_ids[] = { @@ -570,7 +574,7 @@ }; static const struct pci_driver pch_lpc __pci_driver = { - .ops = &gma_func0_ops, - .vendor = PCI_VENDOR_ID_INTEL, + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index fce9416..bb20b35 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -26,13 +26,9 @@ #define IED_SIZE CONFIG_IED_REGION_SIZE /* Northbridge BARs */ -#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ -#ifndef __ACPI__ -#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */ -#else -#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ -#endif -#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ +#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */ +#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ +#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ #define GFXVT_BASE_ADDRESS 0xfed90000ULL #define GFXVT_BASE_SIZE 0x1000 @@ -85,11 +81,11 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define MESEG_BASE 0x70 /* Management Engine Base. */ -#define MESEG_LIMIT 0x78 /* Management Engine Limit. */ -#define REMAPBASE 0x90 /* Remap base. */ -#define REMAPLIMIT 0x98 /* Remap limit. */ -#define TOM 0xa0 /* Top of DRAM in memory controller space. */ +#define MESEG_BASE 0x70 /* Management Engine Base */ +#define MESEG_LIMIT 0x78 /* Management Engine Limit */ +#define REMAPBASE 0x90 /* Remap base */ +#define REMAPLIMIT 0x98 /* Remap limit */ +#define TOM 0xa0 /* Top of DRAM in memory controller space */ #define TOUUD 0xa8 /* Top of Upper Usable DRAM */ #define BDSM 0xb0 /* Base Data Stolen Memory */ #define BGSM 0xb4 /* Base GTT Stolen Memory */ @@ -117,26 +113,27 @@ * MCHBAR */ -#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) -#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or)) +#define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) +#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) +#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) +#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) +#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) +#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) +#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) +#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) +#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) +#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) -#define BIOS_RESET_CPL 0x5da8 /* 8bit */ -#define GFXVTBAR 0x5400 -#define VTVC0BAR 0x5410 - -/* Some power MSRs are also represented in MCHBAR */ -#define MCH_PKG_POWER_LIMIT_LO 0x59a0 -#define MCH_PKG_POWER_LIMIT_HI 0x59a4 -#define MCH_DDR_POWER_LIMIT_LO 0x58e0 -#define MCH_DDR_POWER_LIMIT_HI 0x58e4 +/* As there are many registers, define them on a separate file */ +#include "mchbar_regs.h" /* * EPBAR - Egress Port Root Complex Register Block */ -#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) @@ -167,7 +164,7 @@ * DMIBAR */ -#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) @@ -215,9 +212,9 @@ #include <device/device.h> struct acpi_rsdp; -unsigned long northbridge_write_acpi_tables(struct device *device, - unsigned long start, struct acpi_rsdp *rsdp); +unsigned long northbridge_write_acpi_tables(struct device *device, unsigned long start, + struct acpi_rsdp *rsdp); -#endif -#endif +#endif /* __ASSEMBLER__ */ +#endif /* __ACPI__ */ #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/mchbar_regs.h new file mode 100644 index 0000000..edddf9d --- /dev/null +++ b/src/northbridge/intel/haswell/mchbar_regs.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __HASWELL_MCHBAR_REGS_H__ +#define __HASWELL_MCHBAR_REGS_H__ + +/* Register definitions */ +#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ +#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */ +#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */ +#define MAD_DIMM_CH2 0x500c /* Address Decode Channel 2 (unused on HSW) */ +#define MC_INIT_STATE_G 0x5030 +#define MRC_REVISION 0x5034 /* MRC Revision */ + +#define MC_LOCK 0x50fc /* Memory Controlller Lock register */ + +#define GFXVTBAR 0x5400 /* Base address for IGD */ +#define EDRAMBAR 0x5408 /* Base address for eDRAM */ +#define VTVC0BAR 0x5410 /* Base address for PEG, USB, SATA, etc. */ +#define INTRDIRCTL 0x5418 /* Interrupt Redirection Control (PAIR) */ +#define GDXCBAR 0x5420 /* Generic Debug eXternal Connection */ + +/* PAVP message register. Bit 0 locks PAVP settings, and bits [31..20] are an offset. */ +#define MMIO_PAVP_MSG 0x5500 + +/* Some power MSRs are also represented in MCHBAR */ +#define MCH_PKG_POWER_LIMIT_LO 0x59a0 +#define MCH_PKG_POWER_LIMIT_HI 0x59a4 + +#define MCH_DDR_POWER_LIMIT_LO 0x58e0 +#define MCH_DDR_POWER_LIMIT_HI 0x58e4 + +#define SSKPD 0x5d10 /* 64-bit scratchpad register */ +#define BIOS_RESET_CPL 0x5da8 /* 8bit */ + +#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ +#define SAPMCTL 0x5f00 + +#define HDAUDRID 0x6008 +#define UMAGFXCTL 0x6020 +#define VDMBDFBARKVM 0x6030 +#define VDMBDFBARPAVP 0x6034 +#define VTDTRKLCK 0x63fc +#define REQLIM 0x6800 +#define DMIVCLIM 0x7000 +#define CRDTLCK 0x77fc + +#endif /* __HASWELL_MCHBAR_REGS_H__ */ diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 74d9292..bde7ecf 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -// Use simple device model for this file even in ramstage +/* Use simple device model for this file even in ramstage */ #define __SIMPLE_DEVICE__ #include <arch/romstage.h> @@ -30,7 +30,7 @@ * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignment. */ - uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + uintptr_t tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEG); return tom & ~((1 << 20) - 1); } @@ -53,7 +53,6 @@ * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); - postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, - MTRR_TYPE_WRBACK); + top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 52b158e..c59d02e 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -25,30 +25,30 @@ static const u32 minihd_verb_table[] = { /* coreboot specific header */ - 0x80862807, // Codec Vendor / Device ID: Intel Haswell Mini-HD - 0x80860101, // Subsystem ID - 0x00000004, // Number of jacks + 0x80862807, /* Codec Vendor / Device ID: Intel Haswell Mini-HD */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of jacks */ /* Enable 3rd Pin and Converter Widget */ 0x00878101, /* Pin Widget 5 - PORT B */ - 0x00571C10, - 0x00571D00, - 0x00571E56, - 0x00571F18, + 0x00571c10, + 0x00571d00, + 0x00571e56, + 0x00571f18, /* Pin Widget 6 - PORT C */ - 0x00671C20, - 0x00671D00, - 0x00671E56, - 0x00671F18, + 0x00671c20, + 0x00671d00, + 0x00671e56, + 0x00671f18, /* Pin Widget 7 - PORT D */ - 0x00771C30, - 0x00771D00, - 0x00771E56, - 0x00771F18, + 0x00771c30, + 0x00771d00, + 0x00771e56, + 0x00771f18, /* Disable 3rd Pin and Converter Widget */ 0x00878100, @@ -94,15 +94,14 @@ if (codec_mask) { for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) - hda_codec_init(base, i, - sizeof(minihd_verb_table), + hda_codec_init(base, i, sizeof(minihd_verb_table), minihd_verb_table); } } } static struct pci_operations minihd_pci_ops = { - .set_subsystem = pci_dev_set_subsystem, + .set_subsystem = pci_dev_set_subsystem, }; static struct device_operations minihd_ops = { @@ -110,7 +109,7 @@ .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = minihd_init, - .scan_bus = 0, + .scan_bus = NULL, .ops_pci = &minihd_pci_ops, }; diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 79ab747..a688e1c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -31,11 +31,9 @@ #include "chip.h" #include "haswell.h" -static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, - u32 *len) +static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 pciexbar_reg; - u32 mask; + u32 pciexbar_reg, mask; *base = 0; *len = 0; @@ -46,18 +44,18 @@ return 0; switch ((pciexbar_reg >> 1) & 3) { - case 0: // 256MB + case 0: /* 256MB */ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); *base = pciexbar_reg & mask; *len = 256 * 1024 * 1024; return 1; - case 1: // 128M + case 1: /* 128M */ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27); *base = pciexbar_reg & mask; *len = 128 * 1024 * 1024; return 1; - case 2: // 64M + case 2: /* 64M */ mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); mask |= (1 << 27) | (1 << 26); *base = pciexbar_reg & mask; @@ -89,50 +87,47 @@ return NULL; } - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - */ +/* + * TODO: We could determine how many PCIe busses we need in the bar. + * For now, that number is hardcoded to a max of 64. + */ static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = NULL, - .init = NULL, - .scan_bus = pci_domain_scan_bus, - .acpi_name = northbridge_acpi_name, + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .acpi_name = northbridge_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, }; static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = pci_read_config32(dev, index); - bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; } -/* There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. */ -static int get_bar_in_mchbar(struct device *dev, unsigned int index, - u32 *base, u32 *len) +/* + * There are special BARs that actually are programmed in the MCHBAR. These Intel special + * features, but they do consume resources that need to be accounted for. + */ +static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) { - u32 bar; + u32 bar = MCHBAR32(index); - bar = MCHBAR32(index); - - /* If not enabled don't report it. */ + /* If not enabled don't report it */ if (!(bar & 0x1)) return 0; - /* Knock down the enable bit. */ + /* Knock down the enable bit */ *base = bar & ~1; return 1; @@ -141,26 +136,22 @@ struct fixed_mmio_descriptor { unsigned int index; u32 size; - int (*get_resource)(struct device *dev, unsigned int index, - u32 *base, u32 *size); + int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); const char *description; }; -#define SIZE_KB(x) ((x)*1024) +#define SIZE_KB(x) ((x) * 1024) struct fixed_mmio_descriptor mc_fixed_resources[] = { { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, - { 0x5420, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, - { 0x5408, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, + { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, + { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, }; #undef SIZE_KB -/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ +/* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ static void mc_add_fixed_mmio_resources(struct device *dev) { int i; @@ -173,14 +164,13 @@ size = mc_fixed_resources[i].size; index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) + if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) continue; resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + resource->base = base; resource->size = size; printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", @@ -205,10 +195,10 @@ * | Usage DRAM | * +--------------------------+ 0 * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. + * Some of the base registers above can be equal, making the size of the regions within 0. + * This is because the memory controller internally subtracts the base registers from each + * other to determine sizes of the regions. In other words, the memory map regions are always + * in a fixed order, no matter what sizes they have. */ struct map_entry { @@ -218,14 +208,13 @@ const char *description; }; -static void read_map_entry(struct device *dev, struct map_entry *entry, - uint64_t *result) +static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) { uint64_t value; uint64_t mask; - /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); + /* All registers have a 1MiB granularity */ + mask = ((1ULL << 20) - 1); mask = ~mask; value = 0; @@ -252,12 +241,9 @@ .description = desc_, \ } -#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) +#define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) +#define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) enum { TOM_REG, @@ -270,21 +256,21 @@ BGSM_REG, BDSM_REG, TSEG_REG, - // Must be last. - NUM_MAP_ENTRIES + /* Must be last */ + NUM_MAP_ENTRIES, }; static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), + [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), + [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), + [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; static void mc_read_map_entries(struct device *dev, uint64_t *values) @@ -302,51 +288,45 @@ printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", memory_map[i].description, values[i]); } - /* One can validate the BDSM and BGSM against the GGC. */ + /* One can validate the BDSM and BGSM against the GGC */ printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); } static void mc_add_dram_resources(struct device *dev, int *resource_cnt) { - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; + unsigned long base_k, size_k, touud_k, index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; - /* Read in the MAP registers and report their values. */ + /* Read in the MAP registers and report their values */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); /* * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable + * - 0 -> 0xa0000: cacheable + * - 0xc0000 -> TSEG: cacheable + * - TSEG -> BGSM: cacheable with standard MTRRs and reserved + * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved + * - 4GiB -> TOUUD: cacheable * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. + * The default SMRAM space is reserved so that the range doesn't have to be saved + * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a + * bit of an odd place to reserve the region, but the CPU devices don't have + * dev_ops->read_resources() called on them. * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. + * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to + * handle legacy VGA memory. If this range is not omitted the mtrr code will setup + * the area as cacheable, causing VGA access to not work. * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. + * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation + * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing + * MTRRs covering this region. * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. + * It should be noted that cacheable entry types need to be added in order. The reason + * is that the current MTRR code assumes this and falls over itself if it isn't. * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. + * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. */ index = *resource_cnt; @@ -364,18 +344,16 @@ resource = new_resource(dev, index++); resource->base = mc_values[TSEG_REG]; resource->size = mc_values[BGSM_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; - /* BGSM -> TOLUD. If the IGD is disabled, BGSM can equal TOLUD */ + /* BGSM -> TOLUD. If the IGD is disabled, BGSM can equal TOLUD. */ if (mc_values[BGSM_REG] != mc_values[TOLUD_REG]) { resource = new_resource(dev, index++); resource->base = mc_values[BGSM_REG]; resource->size = mc_values[TOLUD_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; } /* 4GiB -> TOUUD */ @@ -391,12 +369,12 @@ * 0xc0000 - 0xfffff: RAM */ mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); + #if CONFIG(CHROMEOS_RAMOOPS) reserved_ram_resource(dev, index++, CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, - CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif *resource_cnt = index; } @@ -404,31 +382,27 @@ static void mc_read_resources(struct device *dev) { int index = 0; - const bool vtd_capable = - !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); + const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); - /* Read standard PCI resources. */ + /* Read standard PCI resources */ pci_dev_read_resources(dev); - /* Add all fixed MMIO resources. */ + /* Add all fixed MMIO resources */ mc_add_fixed_mmio_resources(dev); - /* Add VT-d MMIO resources if capable */ + /* Add VT-d MMIO resources, if capable */ if (vtd_capable) { - mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, - GFXVT_BASE_SIZE / KiB); - mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, - VTVC0_BASE_SIZE / KiB); + mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); + mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); } - /* Calculate and add DRAM resources. */ + /* Calculate and add DRAM resources */ mc_add_dram_resources(dev, &index); } /* - * The Mini-HD audio device is disabled whenever the IGD is. This is - * because it provides audio over the integrated graphics port(s), which - * requires the IGD to be functional. + * The Mini-HD audio device is disabled whenever the IGD is. This is because it provides + * audio over the integrated graphics port(s), which requires the IGD to be functional. */ static void disable_devices(void) { @@ -446,7 +420,7 @@ { PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" }, }; - struct device *host_dev = pcidev_on_root(0x0, 0); + struct device *host_dev = pcidev_on_root(0, 0); u32 deven; size_t i; @@ -470,29 +444,29 @@ { u8 bios_reset_cpl, pair; - /* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(0x5418); + /* Enable Power Aware Interrupt Routing. */ + pair = MCHBAR8(INTRDIRCTL); pair &= ~0x7; /* Clear 2:0 */ pair |= 0x4; /* Fixed Priority */ - MCHBAR8(0x5418) = pair; + MCHBAR8(INTRDIRCTL) = pair; disable_devices(); /* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management + * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU + * that BIOS has initialized memory and power management. */ bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); bios_reset_cpl |= 3; MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); - /* Configure turbo power limits 1ms after reset complete bit */ + /* Configure turbo power limits 1ms after reset complete bit. */ mdelay(1); set_power_limits(28); - /* Set here before graphics PM init */ - MCHBAR32(0x5500) = 0x00100001; + /* Set here before graphics PM init. */ + MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; } static struct pci_operations intel_pci_ops = { @@ -500,13 +474,13 @@ }; static struct device_operations mc_ops = { - .read_resources = mc_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, + .read_resources = mc_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, .acpi_fill_ssdt_generator = generate_cpu_entries, - .scan_bus = 0, - .ops_pci = &intel_pci_ops, + .scan_bus = NULL, + .ops_pci = &intel_pci_ops, }; static const unsigned short mc_pci_device_ids[] = { @@ -528,12 +502,12 @@ .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = mp_cpu_bus_init, - .scan_bus = 0, + .scan_bus = NULL, }; static void enable_dev(struct device *dev) { - /* Set the operations if it is a special bus type */ + /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 8267833..86dfb88 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -28,6 +28,7 @@ #include <spd.h> #include <security/vboot/vboot_common.h> #include <commonlib/region.h> + #include "raminit.h" #include "pei_data.h" #include "haswell.h" @@ -37,27 +38,27 @@ void save_mrc_data(struct pei_data *pei_data) { /* Save the MRC S3 restore data to cbmem */ - mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, - pei_data->mrc_output, pei_data->mrc_output_len); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, pei_data->mrc_output, + pei_data->mrc_output_len); } static void prepare_mrc_cache(struct pei_data *pei_data) { struct region_device rdev; - // preset just in case there is an error + /* Preset just in case there is an error */ pei_data->mrc_input = NULL; pei_data->mrc_input_len = 0; if (mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, &rdev)) - /* error message printed in find_current_mrc_cache */ + /* Error message printed in find_current_mrc_cache */ return; pei_data->mrc_input = rdev_mmap_full(&rdev); pei_data->mrc_input_len = region_device_sz(&rdev); - printk(BIOS_DEBUG, "%s: at %p, size %x\n", - __func__, pei_data->mrc_input, pei_data->mrc_input_len); + printk(BIOS_DEBUG, "%s: at %p, size %x\n", __func__, pei_data->mrc_input, + pei_data->mrc_input_len); } static const char *ecc_decoder[] = { @@ -67,41 +68,41 @@ "active" }; -/* - * Dump in the log memory controller configuration as read from the memory - * controller registers. - */ +/* Print out the memory controller configuration, as per the values in its registers. */ static void report_memory_config(void) { - u32 addr_decoder_common, addr_decode_ch[2]; + u32 addr_decoder_common, addr_decode_chan[2]; int i; - addr_decoder_common = MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + addr_decoder_common = MCHBAR32(MAD_CHNL); + addr_decode_chan[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_chan[1] = MCHBAR32(MAD_DIMM_CH1); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100); + (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", - addr_decoder_common & 3, + (addr_decoder_common >> 0) & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", - i, ch_conf); - printk(BIOS_DEBUG, " ECC %s\n", - ecc_decoder[(ch_conf >> 24) & 3]); + for (i = 0; i < ARRAY_SIZE(addr_decode_chan); i++) { + u32 ch_conf = addr_decode_chan[i]; + + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, ch_conf); + printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", ((ch_conf >> 22) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " rank interleave %s\n", ((ch_conf >> 21) & 1) ? "on" : "off"); + printk(BIOS_DEBUG, " DIMMA %d MB width %s %s rank%s\n", ((ch_conf >> 0) & 0xff) * 256, ((ch_conf >> 19) & 1) ? "x16" : "x8 or x32", ((ch_conf >> 17) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? "" : ", selected"); + printk(BIOS_DEBUG, " DIMMB %d MB width %s %s rank%s\n", ((ch_conf >> 8) & 0xff) * 256, ((ch_conf >> 20) & 1) ? "x16" : "x8 or x32", @@ -123,18 +124,14 @@ printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n"); - /* - * Do not pass MRC data in for recovery mode boot, - * Always pass it in for S3 resume. - */ + /* Do not pass MRC data in for recovery mode boot, always pass it in for S3 resume */ if (!vboot_recovery_mode_enabled() || pei_data->boot_mode == 2) prepare_mrc_cache(pei_data); - /* If MRC data is not found we cannot continue S3 resume. */ + /* If MRC data is not found, we cannot continue S3 resume */ if (pei_data->boot_mode == 2 && !pei_data->mrc_input) { post_code(POST_RESUME_FAILURE); - printk(BIOS_DEBUG, "Giving up in sdram_initialize: " - "No MRC data\n"); + printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n"); system_reset(); } @@ -142,21 +139,20 @@ pei_data->tx_byte = do_putchar; /* - * Locate and call UEFI System Agent binary. The binary needs to be at - * a fixed offset in the flash and can therefore only reside in the - * COREBOOT fmap region + * Locate and call UEFI System Agent binary. The binary needs to be at a fixed offset + * in the flash and can therefore only reside in the COREBOOT fmap region. */ if (cbfs_locate_file_in_region(&f, "COREBOOT", "mrc.bin", &type) < 0) die("mrc.bin not found!"); + /* We don't care about leaking the mapping */ entry = (unsigned long)rdev_mmap_full(&f.data); if (entry) { int rv; - asm volatile ( - "call *%%ecx\n\t" + asm volatile ("call *%%ecx\n\t" :"=a" (rv) : "c" (entry), "a" (pei_data)); - /* mrc.bin reconfigures USB, so reinit it to have debug */ + /* The mrc.bin reconfigures USB, so usbdebug needs to be reinitialized */ if (CONFIG(USBDEBUG_IN_PRE_RAM)) usbdebug_hw_init(true); @@ -178,13 +174,11 @@ die("UEFI PEI System Agent not found.\n"); } - /* For reference print the System Agent version - * after executing the UEFI PEI stage. - */ - u32 version = MCHBAR32(0x5034); + /* For reference, print the System Agent version after executing the UEFI PEI stage */ + u32 version = MCHBAR32(MRC_REVISION); printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n", - version >> 24, (version >> 16) & 0xff, - (version >> 8) & 0xff, version & 0xff); + (version >> 24) & 0xff, (version >> 16) & 0xff, + (version >> 8) & 0xff, (version >> 0) & 0xff); report_memory_config(); } @@ -194,22 +188,21 @@ u32 addr_decode_ch[2]; struct memory_info* mem_info; struct dimm_info *dimm; - int ddr_frequency; - int dimm_size; - int ch, d_num; + int ddr_frequency, dimm_size, ch, d_num; int dimm_cnt = 0; mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); if (!mem_info) die("Failed to add memory info to CBMEM.\n"); + memset(mem_info, 0, sizeof(struct memory_info)); - /* FIXME: Do we need to read MCHBAR32(0x5000) ? */ - MCHBAR32(0x5000); - addr_decode_ch[0] = MCHBAR32(0x5004); - addr_decode_ch[1] = MCHBAR32(0x5008); + /* FIXME: Do we need to read MCHBAR32(MAD_CHNL) ? (Answer: Nope) */ + MCHBAR32(MAD_CHNL); + addr_decode_ch[0] = MCHBAR32(MAD_DIMM_CH0); + addr_decode_ch[1] = MCHBAR32(MAD_DIMM_CH1); - ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100; + ddr_frequency = (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100; for (ch = 0; ch < ARRAY_SIZE(addr_decode_ch); ch++) { u32 ch_conf = addr_decode_ch[ch]; @@ -233,7 +226,7 @@ SPD_DIMM_PART_LEN); dimm->mod_id = (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID2] << 8) | - (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xFF); + (pei_data->spd_data[dimm_cnt][SPD_DIMM_MOD_ID1] & 0xff); dimm->mod_type = SPD_SODIMM; dimm->bus_width = 0x3; /* 64-bit */ dimm_cnt++; -- To view, visit https://review.coreboot.org/c/coreboot/+/38434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I926289304acb834f9b13cd7902801798f8ee478a Gerrit-Change-Number: 38434 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

5 23

Change in coreboot[master]: mb/google/palkia: Create palkia variant
by Kane Chen (Code Review) 15 Mar '20

15 Mar '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38860 ) Change subject: mb/google/palkia: Create palkia variant ...................................................................... mb/google/palkia: Create palkia variant Add Palkia as a variant of Hatch. BUG=b:none BRANCH=none TEST=none Signed-off-by: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193 --- A src/mainboard/google/hatch/variants/palkia/Makefile.inc A src/mainboard/google/hatch/variants/palkia/gpio.c A src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/palkia/include/variant/ec.h A src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h A src/mainboard/google/hatch/variants/palkia/memory.c A src/mainboard/google/hatch/variants/palkia/overridetree.cb A src/mainboard/google/hatch/variants/palkia/ramstage.c 8 files changed, 747 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/38860/1 diff --git a/src/mainboard/google/hatch/variants/palkia/Makefile.inc b/src/mainboard/google/hatch/variants/palkia/Makefile.inc new file mode 100644 index 0000000..be074b7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/Makefile.inc @@ -0,0 +1,22 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = LP_8G_2133 # 0b0000 +SPD_SOURCES += LP_16G_2133 # 0b0001 + +romstage-y += memory.c +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/palkia/gpio.c b/src/mainboard/google/hatch/variants/palkia/gpio.c new file mode 100644 index 0000000..a9a17e5 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/gpio.c @@ -0,0 +1,190 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* A8 : PEN_GARAGE_DET_L (wake) */ + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, EDGE_SINGLE, NONE), + /* A10 : FPMCU_PCH_BOOT1 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* A11 : GSPI1_CS1# ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : ISH_GP6 ==> NC */ + PAD_NC(GPP_A12, NONE), + /* A18 : ISH_GP0 ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : ISH_GP1 ==> NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : ISH_GP2 ==> NC */ + PAD_NC(GPP_A20, NONE), + /* A22 : ISH_GP4 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : ISH_GP5 ==> NC */ + PAD_NC(GPP_A23, NONE), + /* B19 : GSPI1_CS0# ==> NC */ + PAD_NC(GPP_B19, NONE), + /* B20 : GSPI1_CLK ==> NC */ + PAD_NC(GPP_B20, NONE), + /* B21 : GSPI1_MISO ==> NC */ + PAD_NC(GPP_B21, NONE), + /* B22 : GSPI1_MOSI ==> NC */ + PAD_NC(GPP_B22, NONE), + /* C1 : SMBDATA ==> NC */ + PAD_NC(GPP_C1, NONE), + /* C4 : TOUCHSCREEN_DIS_L */ + PAD_CFG_GPO(GPP_C4, 0, DEEP), + /* C6 : GPP_C6 ==> NC */ + PAD_NC(GPP_C6, NONE), + /* C7 : GPP_C7 ==> Touchscreen_INT_L */ + PAD_CFG_GPI_APIC(GPP_C7, NONE, PLTRST, LEVEL, INVERT), + /* C23 : UART2_CTS# ==> NC */ + PAD_NC(GPP_C23, NONE), + /* D5 : ISH_I2C0_SDA ==> NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : ISH_I2C0_SCL ==> NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : ISH_I2C1_SDA ==> NC */ + PAD_NC(GPP_D7, NONE), + /* D8 : ISH_I2C1_SCL ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D10 : ISH_SPI_CLK ==> NC */ + PAD_NC(GPP_D10, NONE), + /* D16 : USI_INT_L */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + /* D21 : SPI1_IO2 ==> NC */ + PAD_NC(GPP_D21, NONE), + /* F0 : GPP_F0 ==> NC */ + /* E12 : USB_A_OC_OD USB_OC3 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* F0 : GPP_F0 ==> NC */ + PAD_NC(GPP_F0, NONE), + /* F1 : GPP_F1 ==> NC */ + PAD_NC(GPP_F1, NONE), + /* F3 : GPP_F3 ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_F3, NONE, PLTRST), + /* F10 : GPP_F10 ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_F10, NONE, PLTRST), + /* F11 : EMMC_CMD ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F20 : EMMC_RCLK ==> NC */ + PAD_NC(GPP_F20, NONE), + /* F21 : EMMC_CLK ==> NC */ + PAD_NC(GPP_F21, NONE), + /* F22 : EMMC_RESET# ==> NC */ + PAD_NC(GPP_F22, NONE), + /* G0 : GPP_G0 ==> NC */ + PAD_NC(GPP_G0, NONE), + /* G1 : GPP_G1 ==> NC */ + PAD_NC(GPP_G1, NONE), + /* G2 : GPP_G2 ==> NC */ + PAD_NC(GPP_G2, NONE), + /* G3 : GPP_G3 ==> NC */ + PAD_NC(GPP_G3, NONE), + /* G4 : GPP_G4 ==> NC */ + PAD_NC(GPP_G4, NONE), + /* G5 : GPP_G5 ==> NC */ + PAD_NC(GPP_G5, NONE), + /* G6 : GPP_G6 ==> NC */ + PAD_NC(GPP_G6, NONE), + /* H3 : SPKR_PA_EN */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : Touchscreen I2C2_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : Touchscreen I2C2_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H13 : M2_SKT2_CFG1 ==> SPKR_RST_L */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), + /* H14 : M2_SKT2_CFG2 ==> TOUCHSCREEN_STOP_L */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), + /* H19 : TIMESYNC[0] ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_H19, NONE, PLTRST), + /* H22 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_H22, NONE, PLTRST), +}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* + * Default GPIO settings before entering non-S5 sleep states. + * Configure A12: FPMCU_RST_ODL as GPO before entering sleep. + * This guarantees that A12's native3 function is disabled. + * See https://review.coreboot.org/c/coreboot/+/32111 . + */ +static const struct pad_config default_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */ +}; + +/* + * GPIO settings before entering S5, which are same as + * default_sleep_gpio_table but also, turn off FPMCU. + */ +static const struct pad_config s5_sleep_gpio_table[] = { + PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */ +}; + +const struct pad_config *variant_sleep_gpio_table(u8 slp_typ, size_t *num) +{ + if (slp_typ == ACPI_S5) { + *num = ARRAY_SIZE(s5_sleep_gpio_table); + return s5_sleep_gpio_table; + } + *num = ARRAY_SIZE(default_sleep_gpio_table); + return default_sleep_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..a02ce04 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/acpi/dptf.asl @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 0 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery Charger" +#define DPTF_TSR0_PASSIVE 59 +#define DPTF_TSR0_CRITICAL 80 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "5V Regulator" +#define DPTF_TSR1_PASSIVE 0 +#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_ACTIVE_AC0 42 +#define DPTF_TSR1_ACTIVE_AC1 41 +#define DPTF_TSR1_ACTIVE_AC2 39 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 0 +#define DPTF_TSR2_CRITICAL 65 + +#define DPTF_TSR3_SENSOR_ID 3 +#define DPTF_TSR3_SENSOR_NAME "CPU" +#define DPTF_TSR3_PASSIVE 44 +#define DPTF_TSR3_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER +#define DPTF_ENABLE_FAN_CONTROL + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ +}) + +/* DFPS: Fan Performance States */ +Name (DFPS, Package () { + 0, // Revision + /* + * TODO : Need to update this Table after characterization. + * These are initial reference values. + */ + /* Control, Trip Point, Speed, NoiseLevel, Power */ + Package () {90, 0xFFFFFFFF, 6700, 220, 2200}, + Package () {80, 0xFFFFFFFF, 5800, 180, 1800}, + Package () {70, 0xFFFFFFFF, 5000, 145, 1450}, + Package () {60, 0xFFFFFFFF, 4900, 115, 1150}, + Package () {50, 0xFFFFFFFF, 3838, 90, 900}, + Package () {40, 0xFFFFFFFF, 2904, 55, 550}, + Package () {30, 0xFFFFFFFF, 2337, 30, 300}, + Package () {20, 0xFFFFFFFF, 1608, 15, 150}, + Package () {10, 0xFFFFFFFF, 800, 10, 100}, + Package () {0, 0xFFFFFFFF, 0, 0, 50} +}) + +Name (DART, Package () { + /* Fan effect on CPU */ + 0, // Revision + Package () { + /* + * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, + * AC7, AC8, AC9 + */ + \_SB.DPTF.TFN1, \_SB.PCI0.TCPU, 100, 90, 70, 50, 50, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 70, 50, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR3, 100, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0 + } +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on TSR0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, + + /* Charger Throttle Effect on TSR0 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 64000, /* PowerLimitMinimum */ + 64000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h new file mode 100644 index 0000000..92f9d41 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +#endif diff --git a/src/mainboard/google/hatch/variants/palkia/memory.c b/src/mainboard/google/hatch/variants/palkia/memory.c new file mode 100644 index 0000000..a3cd813 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/memory.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <boardid.h> +#include <gpio.h> +#include <soc/cnl_memcfg_init.h> +#include <string.h> +#include <variant/gpio.h> + +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the SoC pins to the lpddr3 pins + * for both channels. + * + * "The index of the array is CPU byte number, the values are DRAM byte + * numbers." - doc #573387 + * + * the index = pin number on SoC + * the value = pin number on lpddr3 part + */ + .dqs_map[DDR_CH0] = {4, 7, 5, 6, 0, 3, 2, 1}, + .dqs_map[DDR_CH1] = {0, 3, 2, 1, 4, 7, 6, 5}, + + .dq_map[DDR_CH0] = { + {0xf0, 0xf}, + {0x0, 0xf}, + {0xf0, 0xf}, + {0xf0, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0x0, 0xf0}, + {0xf, 0xf0}, + {0xf, 0x0}, + {0xff, 0x0}, + {0xff, 0x0} + }, + + /* Helios uses 200, 80.6 and 162 rcomp resistors */ + .rcomp_resistor = {200, 81, 162}, + + /* Helios Rcomp target values */ + .rcomp_targets = {100, 40, 40, 23, 40}, + + /* Set CaVref config to 0 for LPDDR3 */ + .vref_ca_config = 0, + + /* Disable Early Command Training */ + .ect = 0, +}; + +void variant_memory_params(struct cnl_mb_cfg *bcfg) +{ + memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); +} + +int variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + int val = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + + if ((board_id() != 0) && (board_id() != BOARD_ID_UNKNOWN)) + return val; + + /* + * For boards with id 0 or unknown, memory straps 3 and 4 are + * incorrectly stuffed in hardware. This is a workaround for these + * boards to override memory strap 3 to 0 and 4 to 1. + */ + switch (val) { + case 3: + val = 0; + break; + case 4: + val = 1; + break; + } + + return val; +} diff --git a/src/mainboard/google/hatch/variants/palkia/overridetree.cb b/src/mainboard/google/hatch/variants/palkia/overridetree.cb new file mode 100644 index 0000000..140b9d3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/overridetree.cb @@ -0,0 +1,225 @@ +chip soc/intel/cannonlake + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "64" + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + register "usb2_ports[3]" = "USB2_PORT_LONG(OC3)" # Type A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type A + + # No PCIe WiFi + register "PcieRpEnable[13]" = "0" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | FP MCU | + #| I2C0 | Trackpad | + #| I2C1 | Touchscreen | + #| I2C2 | 2nd Touchscreen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + .data_hold_time_ns = 330, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + }" + + device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + # No Type-A port + device usb 2.2 off end + end + chip drivers/usb/acpi + # No Type-A Port + device usb 2.3 off end + end + chip drivers/usb/acpi + # No WWAN + device usb 2.5 off end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""Left Type-A Port"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.4 on end + end + end + end + end + + # Native SD Card interface unused + device pci 14.5 off end + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end + + device pci 15.1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9008"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_ASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C 1 + + device pci 15.2 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9009"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = + "ACPI_IRQ_EDGE_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.enable_off_delay_ms" = "10" + register "generic.has_power_resource" = "1" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "generic.stop_delay_ms" = "15" + register "generic.stop_off_delay_ms" = "5" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end #I2C 2 + + # I2C #3 unused + device pci 15.3 off end + + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Left Speaker Amp"" + register "uid" = "0" + register "name" = ""TL"" + device i2c 38 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1011"" + register "desc" = ""RT1011 Tweeter Right Speaker Amp"" + register "uid" = "1" + register "name" = ""TR"" + device i2c 39 on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H3)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HDA + end +end diff --git a/src/mainboard/google/hatch/variants/palkia/ramstage.c b/src/mainboard/google/hatch/variants/palkia/ramstage.c new file mode 100644 index 0000000..9b919fc --- /dev/null +++ b/src/mainboard/google/hatch/variants/palkia/ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <delay.h> +#include <gpio.h> +#include <baseboard/variants.h> +#include <soc/gpio.h> + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a303d9fc2be9ea358ad66cd648738187c974193 Gerrit-Change-Number: 38860 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-MessageType: newchange

10 77

Change in coreboot[master]: soc/intel/common: Log CSE's RO and RW versions
by Sridhar Siricilla (Code Review) 15 Mar '20

15 Mar '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39023 ) Change subject: soc/intel/common: Log CSE's RO and RW versions ...................................................................... soc/intel/common: Log CSE's RO and RW versions Since CSE FW Custom SKU has RO and RW partitions and each can have different versions, so skip sending GET_FW_VERSION command which fetches version of CSE RW. Instead call cse_print_boot_partition_info() which logs CSE's RO(BP1) and RW(BP2) versions. The cse_print_boot_partition_info() function sends GET_BOOT_PARTITION_INFO HECI command to CSE. TEST=Verified on hatch Change-Id: Iffd2986adaecf24590e635deaa9794ad85a24115 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> --- M src/soc/intel/common/block/cse/cse.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39023/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index bf2ae3f..e0f42d4 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -834,8 +834,10 @@ * Ignore if ME Firmware SKU type is custom since * print_boot_partition_info() logs RO(BP1) and RW(BP2) versions. */ - if (cse_is_hfs3_fw_sku_custom()) + if (cse_is_hfs3_fw_sku_custom()) { + cse_print_boot_partition_info(); return; + } /* * Prerequisites: -- To view, visit https://review.coreboot.org/c/coreboot/+/39023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffd2986adaecf24590e635deaa9794ad85a24115 Gerrit-Change-Number: 39023 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

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