coreboot-gerrit February 2020

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Change in coreboot[master]: drivers/elog,pc80: Move cmos_post_log()
by Kyösti Mälkki (Code Review) 20 Apr '20

20 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38189 ) Change subject: drivers/elog,pc80: Move cmos_post_log() ...................................................................... drivers/elog,pc80: Move cmos_post_log() Change-Id: I98044a28c29a2b1756fb25fb593f505e914a71c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/elog/elog.c M src/drivers/pc80/rtc/post.c M src/include/console/console.h M src/include/pc80/mc146818rtc.h 4 files changed, 36 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/38189/1 diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 5f11c0c..9bd2a61 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -758,16 +758,37 @@ #endif } +/* Check and log POST codes from previous boot */ +static void log_last_boot_post(void) +{ +#if CONFIG(ARCH_X86) + u8 code; + u32 extra; + + if (!CONFIG(CMOS_POST)) + return; + + if (cmos_post_previous(&code, &extra) == 0) + return; + + printk(BIOS_WARNING, "POST: Unexpected post code/extra " + "in previous boot: 0x%02x/0x%04x\n", code, extra); + + if (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) { + elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); + /* Always zero with !CMOS_POST_EXTRA. */ + if (extra) + elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); + } +#endif +} + static void elog_add_boot_count(void) { if (elog_do_add_boot_count()) { elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); -#if CONFIG(ARCH_X86) - /* Check and log POST codes from previous boot */ - if (CONFIG(CMOS_POST)) - cmos_post_log(); -#endif + log_last_boot_post(); } } diff --git a/src/drivers/pc80/rtc/post.c b/src/drivers/pc80/rtc/post.c index 0d5d0e1..2893a41 100644 --- a/src/drivers/pc80/rtc/post.c +++ b/src/drivers/pc80/rtc/post.c @@ -13,7 +13,6 @@ */ #include <stdint.h> -#include <elog.h> #include <console/console.h> #include <device/device.h> #include <pc80/mc146818rtc.h> @@ -21,45 +20,38 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -void cmos_post_log(void) +int cmos_post_previous(u8 *code, u32 *extra) { - u8 code = 0; - u32 extra = 0; - spin_lock(&cmos_post_lock); /* Get post code from other bank */ switch (cmos_read(CMOS_POST_BANK_OFFSET)) { case CMOS_POST_BANK_0_MAGIC: - code = cmos_read(CMOS_POST_BANK_1_OFFSET); + *code = cmos_read(CMOS_POST_BANK_1_OFFSET); if (CONFIG(CMOS_POST_EXTRA)) - extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_1_EXTRA); break; case CMOS_POST_BANK_1_MAGIC: - code = cmos_read(CMOS_POST_BANK_0_OFFSET); + *code = cmos_read(CMOS_POST_BANK_0_OFFSET); if (CONFIG(CMOS_POST_EXTRA)) - extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); + *extra = cmos_read32(CMOS_POST_BANK_0_EXTRA); break; } spin_unlock(&cmos_post_lock); /* Check last post code in previous boot against normal list */ - switch (code) { + switch (*code) { case POST_OS_BOOT: case POST_OS_RESUME: case POST_ENTER_ELF_BOOT: case 0: break; default: - printk(BIOS_WARNING, "POST: Unexpected post code " - "in previous boot: 0x%02x\n", code); -#if CONFIG(ELOG) && (ENV_RAMSTAGE || CONFIG(ELOG_PRERAM)) - elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code); - if (CONFIG(CMOS_POST_EXTRA) && extra) - elog_add_event_dword(ELOG_TYPE_POST_EXTRA, extra); -#endif + return -1; } + + return 0; } void cmos_post_init(void) diff --git a/src/include/console/console.h b/src/include/console/console.h index 9983cef..9e6c76e 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -31,6 +31,7 @@ void post_code(u8 value); void arch_post_code(u8 value); void cmos_post_code(u8 value); +int cmos_post_previous(u8 *code, u32 *extra); #if CONFIG(CMOS_POST_EXTRA) struct device; void post_log_path(const struct device *dev); diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index b064461..94d5ef5 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -209,9 +209,6 @@ #define CMOS_POST_EXTRA_DEV_PATH 0x01 -void cmos_post_log(void); -#else -static inline void cmos_post_log(void) {} #endif /* CONFIG_CMOS_POST */ #endif /* CONFIG_ARCH_X86 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98044a28c29a2b1756fb25fb593f505e914a71c0 Gerrit-Change-Number: 38189 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: NOT_FOR_MERGE: Make FSP driver tolerate Picasso
by Marshall Dawson (Code Review) 19 Apr '20

19 Apr '20

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34427 to review the following change. Change subject: NOT_FOR_MERGE: Make FSP driver tolerate Picasso ...................................................................... NOT_FOR_MERGE: Make FSP driver tolerate Picasso Change-Id: I24a47a10482486e4755ba8ef18aebc767533905e Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/drivers/intel/fsp2_0/notify.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/34427/1 diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c index 34d7e89..26258dee 100644 --- a/src/drivers/intel/fsp2_0/notify.c +++ b/src/drivers/intel/fsp2_0/notify.c @@ -69,6 +69,13 @@ { enum fsp_notify_phase phase = (uint32_t)arg; + /* Hack for Picasso - we don't currently call fsp-s, and mignt not have + * entry points. W/O this hack, the notification steps find null ptrs + * for the entry point. + */ + if (CONFIG(SOC_AMD_PICASSO)) + return; + display_mtrrs(); fsp_notify(phase); -- To view, visit https://review.coreboot.org/c/coreboot/+/34427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a47a10482486e4755ba8ef18aebc767533905e Gerrit-Change-Number: 34427 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: soc/amd/picasso: Move BERT region to cbmem
by Marshall Dawson (Code Review) 19 Apr '20

19 Apr '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38694 ) Change subject: soc/amd/picasso: Move BERT region to cbmem ...................................................................... soc/amd/picasso: Move BERT region to cbmem Allocate storage for the BERT reserved memory in cbmem, and add it in response to a romstage hook. Add a Kconfig option for adjusting the size reserved. This is different from the Stoney Ridge implementation where it was intentionally oversized to ease MTRR use and to keep TSEG aligned. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/mca.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/38694/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4a0fa56..7be9d94 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -185,6 +185,13 @@ ACPI Boot Error Record Table. This option reserves an 8MB region for building the error structures. +config ACPI_BERT_SIZE + hex + default 0x4000 + help + Specify the amount of DRAM reserved for gathering the data used to + generate the ACPI table. + config RO_REGION_ONLY string depends on CHROMEOS diff --git a/src/soc/amd/picasso/mca.c b/src/soc/amd/picasso/mca.c index 57fa9c6..8621efb 100644 --- a/src/soc/amd/picasso/mca.c +++ b/src/soc/amd/picasso/mca.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <arch/bert_storage.h> #include <cper.h> +#include <cbmem.h> struct mca_bank { int bank; @@ -205,3 +206,33 @@ for (i = 0 ; i < num_banks ; i++) wrmsr(IA32_MC0_STATUS + (i * 4), mci.sts); } + +#define BERT_REGION_MAX_SIZE 0x100000 + +void bert_reserved_region(void **start, size_t *size) +{ + const struct cbmem_entry *bert; + + *start = 0; + *size = 0; + + bert = cbmem_entry_find(CBMEM_ID_BERT_RAW_DATA); + if (!bert) + return; + + *start = cbmem_entry_start(bert); + *size = cbmem_entry_size(bert); +} + +static void alloc_bert_in_cbmem(int unused) +{ + void *p; + + if (CONFIG(ACPI_BERT)) { + p = cbmem_add(CBMEM_ID_BERT_RAW_DATA, CONFIG_ACPI_BERT_SIZE); + if (!p) + printk(BIOS_ERR, "Error: BERT region was not added\n"); + } +} + +ROMSTAGE_CBMEM_INIT_HOOK(alloc_bert_in_cbmem) -- To view, visit https://review.coreboot.org/c/coreboot/+/38694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4759154d394a8f5b35c0ef0a15994bbef25492e5 Gerrit-Change-Number: 38694 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/harcuvar: Fix board_id() return type
by Jacob Garber (Code Review) 18 Apr '20

18 Apr '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39015 ) Change subject: mb/intel/harcuvar: Fix board_id() return type ...................................................................... mb/intel/harcuvar: Fix board_id() return type The weak definition of board_id() in coreboot_table.c returns a uint32_t, so update this function to match. This fixes a compiler error when using LTO. Change-Id: I6ad03ecedcf4a4d9f0c917cdc760f81ddde06d11 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/mainboard/intel/harcuvar/boardid.c M src/mainboard/intel/harcuvar/harcuvar_boardid.h M src/mainboard/intel/harcuvar/hsio.c M src/mainboard/intel/harcuvar/romstage.c 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39015/1 diff --git a/src/mainboard/intel/harcuvar/boardid.c b/src/mainboard/intel/harcuvar/boardid.c index 7edf364..5044f1a 100644 --- a/src/mainboard/intel/harcuvar/boardid.c +++ b/src/mainboard/intel/harcuvar/boardid.c @@ -18,7 +18,7 @@ #include "harcuvar_boardid.h" -uint8_t board_id(void) +uint32_t board_id(void) { int id = BoardIdHarcuvar; diff --git a/src/mainboard/intel/harcuvar/harcuvar_boardid.h b/src/mainboard/intel/harcuvar/harcuvar_boardid.h index 3bcd60c..10e03d9 100644 --- a/src/mainboard/intel/harcuvar/harcuvar_boardid.h +++ b/src/mainboard/intel/harcuvar/harcuvar_boardid.h @@ -21,6 +21,6 @@ #define BoardIdHarcuvar 0x52 -uint8_t board_id(void); +uint32_t board_id(void); #endif /* MAINBOARD_BOARD_H */ diff --git a/src/mainboard/intel/harcuvar/hsio.c b/src/mainboard/intel/harcuvar/hsio.c index fa17130..a7b8811 100644 --- a/src/mainboard/intel/harcuvar/hsio.c +++ b/src/mainboard/intel/harcuvar/hsio.c @@ -20,7 +20,7 @@ size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) { - uint8_t boardid = board_id(); + uint32_t boardid = board_id(); size_t num; switch (boardid) { case BoardIdHarcuvar: diff --git a/src/mainboard/intel/harcuvar/romstage.c b/src/mainboard/intel/harcuvar/romstage.c index 53ecdec..179ff23 100644 --- a/src/mainboard/intel/harcuvar/romstage.c +++ b/src/mainboard/intel/harcuvar/romstage.c @@ -89,7 +89,7 @@ { size_t num; const struct dnv_pad_config *table; - uint8_t boardid = board_id(); + uint32_t boardid = board_id(); /* Configure pads prior to SiliconInit() in case there's any * dependencies during hardware initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/39015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ad03ecedcf4a4d9f0c917cdc760f81ddde06d11 Gerrit-Change-Number: 39015 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: i82371eb: Drop KB/Mouse/FDC declarations
by Keith Hui (Code Review) 18 Apr '20

18 Apr '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38600 ) Change subject: i82371eb: Drop KB/Mouse/FDC declarations ...................................................................... i82371eb: Drop KB/Mouse/FDC declarations These are declared by superio. Change-Id: I1db4aca7d682ec298b8f53cfab6ffe661e8ff6e0 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/i82371eb/acpi/isabridge.asl 1 file changed, 0 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38600/1 diff --git a/src/southbridge/intel/i82371eb/acpi/isabridge.asl b/src/southbridge/intel/i82371eb/acpi/isabridge.asl index 2f842d6..6a0cd45 100644 --- a/src/southbridge/intel/i82371eb/acpi/isabridge.asl +++ b/src/southbridge/intel/i82371eb/acpi/isabridge.asl @@ -14,74 +14,6 @@ * GNU General Public License for more details. */ -/* - * ISA portions taken from QEMU acpi-dsdt.dsl. - */ - -// Intel LPC Bus Device - 0:4.0 -Device (LPCB) -{ - Name(_ADR, 0x00040000) - - OperationRegion(PCIC, PCI_Config, 0x00, 0x100) - - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - - /* PS/2 floppy controller */ - Device (FDC0) - { - Name (_HID, EisaId ("PNP0700")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, NotSerialized) - { - Name (BUF0, ResourceTemplate () { - IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04) - IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01) - IRQNoFlags () {6} - DMA (Compatibility, NotBusMaster, Transfer8) {2} - }) - Return (BUF0) - } - } -} - Device(MBRS) { Name (_HID, EisaId ("PNP0C02")) Name (_UID, 0x01) -- To view, visit https://review.coreboot.org/c/coreboot/+/38600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1db4aca7d682ec298b8f53cfab6ffe661e8ff6e0 Gerrit-Change-Number: 38600 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/agesa/f14: Fix array length
by Jacob Garber (Code Review) 18 Apr '20

18 Apr '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39014 ) Change subject: vc/amd/agesa/f14: Fix array length ...................................................................... vc/amd/agesa/f14: Fix array length This array is declared to have length MAX_FF_TYPES (aka 6) in several other places, so update it here so the length matches. This fixes a compiler error when using LTO. Extending the length is harmless, since the only code that uses this array will stop once it reaches the NULL pointer. Change-Id: Ie00e969fa8cda88a934bf416c8775f7ae0b2747e Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/39014/1 diff --git a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h index 57dc0c8..d75445b 100644 --- a/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f14/Config/OptionMemoryInstall.h @@ -569,7 +569,7 @@ #define PLAT_SP_ON_FF_SDIMM3 MemPConstructPsUDef, #define PLAT_SP_ON_FF_UDIMM3 MemPConstructPsUDef, #endif - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[] = { + MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { PLAT_SP_ON_FF_SDIMM3 PLAT_SP_ON_FF_UDIMM3 NULL -- To view, visit https://review.coreboot.org/c/coreboot/+/39014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie00e969fa8cda88a934bf416c8775f7ae0b2747e Gerrit-Change-Number: 39014 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/agesa/f14: Fix function return type
by Jacob Garber (Code Review) 18 Apr '20

18 Apr '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39013 ) Change subject: vc/amd/agesa/f14: Fix function return type ...................................................................... vc/amd/agesa/f14: Fix function return type F14GetNbCofVidUpdate() is declared elsewhere to be of type F_CPU_IS_NBCOF_INIT_NEEDED, which is supposed to return a boolean value (not an AGESA status). This is fixed in the corresponding f15tn and f16kb code, so apply the same change here. This fixes a compiler error when using LTO. Change-Id: Ifc44e2c0467f8bd1f537b5a69c501ba51053d3d9 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c M src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/39013/1 diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c index e7614a6..9f0c4d2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.c @@ -384,7 +384,7 @@ * * @retval AGESA_SUCCESS Always succeeds. */ -AGESA_STATUS +BOOLEAN F14GetNbCofVidUpdate ( IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PCI_ADDR *PciAddress, @@ -393,7 +393,7 @@ ) { *NbCofVidUpdateRequired = FALSE; - return (AGESA_SUCCESS); + return FALSE; } /*---------------------------------------------------------------------------------------*/ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h index 8bf3dc3..8b9f31c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/cpuF14Utilities.h @@ -99,7 +99,7 @@ IN AMD_CONFIG_PARAMS *StdHeader ); -AGESA_STATUS +BOOLEAN F14GetNbCofVidUpdate ( IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN PCI_ADDR *PciAddress, -- To view, visit https://review.coreboot.org/c/coreboot/+/39013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc44e2c0467f8bd1f537b5a69c501ba51053d3d9 Gerrit-Change-Number: 39013 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: asus/p2b,asus/p2b-ls: Declare \_SB.PCI0.MBRS in DSDT
by Keith Hui (Code Review) 18 Apr '20

18 Apr '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38601 ) Change subject: asus/p2b,asus/p2b-ls: Declare \_SB.PCI0.MBRS in DSDT ...................................................................... asus/p2b,asus/p2b-ls: Declare \_SB.PCI0.MBRS in DSDT sb/intel/i82371eb/isa.c has code that fills this path with CPU info, which was triggering errors in Linux because it was not declared in the DSDT. Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b-ls/dsdt.asl M src/mainboard/asus/p2b/dsdt.asl 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38601/1 diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 83e1df6..b350bc9 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -175,6 +175,7 @@ }) #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> + #include <southbridge/intel/i82371eb/acpi/isabridge.asl> /* Begin southbridge block */ Device (PX40) @@ -193,6 +194,7 @@ Device (SYSR) { Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 279f772..3fc531a 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -161,6 +161,7 @@ }) #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl> + #include <southbridge/intel/i82371eb/acpi/isabridge.asl> /* Begin southbridge block */ Device (PX40) @@ -179,6 +180,7 @@ Device (SYSR) { Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x02) Method (_CRS, 0, NotSerialized) { Name (BUF1, ResourceTemplate () -- To view, visit https://review.coreboot.org/c/coreboot/+/38601 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a Gerrit-Change-Number: 38601 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: asus/p2b-*: Move serial init to mainboard bootblock
by Keith Hui (Code Review) 18 Apr '20

18 Apr '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38670 ) Change subject: asus/p2b-*: Move serial init to mainboard bootblock ...................................................................... asus/p2b-*: Move serial init to mainboard bootblock Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b/Makefile.inc R src/mainboard/asus/p2b/early_init.c M src/northbridge/intel/i440bx/romstage.c 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/38670/1 diff --git a/src/mainboard/asus/p2b/Makefile.inc b/src/mainboard/asus/p2b/Makefile.inc index 620b000..68cd7e7 100644 --- a/src/mainboard/asus/p2b/Makefile.inc +++ b/src/mainboard/asus/p2b/Makefile.inc @@ -1,4 +1,4 @@ -romstage-y += romstage.c +bootblock-y += early_init.c # If not building for the "main variant" of p2b, remove p2b's irq_tables.c from list # of files to compile, and replace with irq_tables.c for the variant only if diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/early_init.c similarity index 90% rename from src/mainboard/asus/p2b/romstage.c rename to src/mainboard/asus/p2b/early_init.c index fbd7124..725e614 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/early_init.c @@ -14,13 +14,13 @@ * GNU General Public License for more details. */ -#include <northbridge/intel/i440bx/raminit.h> +#include <bootblock_common.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) -void mainboard_enable_serial(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/intel/i440bx/romstage.c b/src/northbridge/intel/i440bx/romstage.c index 1dee03a..8109c37 100644 --- a/src/northbridge/intel/i440bx/romstage.c +++ b/src/northbridge/intel/i440bx/romstage.c @@ -20,9 +20,6 @@ void mainboard_romstage_entry(void) { - mainboard_enable_serial(); - console_init(); - i82371eb_early_init(); sdram_initialize(); -- To view, visit https://review.coreboot.org/c/coreboot/+/38670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850 Gerrit-Change-Number: 38670 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lenovo/g505s/Kconfig: Set framebuffer graphics mode to VESA 118h mode
by mikeb mikeb (Code Review) 17 Apr '20

17 Apr '20

Hello Mike Banon, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31325 to review the following change. Change subject: lenovo/g505s/Kconfig: Set framebuffer graphics mode to VESA 118h mode ...................................................................... lenovo/g505s/Kconfig: Set framebuffer graphics mode to VESA 118h mode Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console) to 118h VESA (1024x768 16.8M-color (8:8:8)) mode because it's the closest to this laptop's 1366x768 screen resolution. This provides console output even if e.g. GRUB is the payload. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0b4eacf61d905f1160531a988e192c3b626dca68 --- M src/mainboard/lenovo/g505s/Kconfig 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31325/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..2d1eac7 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -55,4 +55,12 @@ string default "1002,990b" +config FRAMEBUFFER_SET_VESA_MODE + bool + default y + +config FRAMEBUFFER_VESA_DEFAULT_118 + bool + default y + endif # BOARD_LENOVO_G505S -- To view, visit https://review.coreboot.org/c/coreboot/+/31325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b4eacf61d905f1160531a988e192c3b626dca68 Gerrit-Change-Number: 31325 Gerrit-PatchSet: 1 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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