coreboot-gerrit February 2020

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Change in coreboot[master]: arch/x86: Fix S3 resume without stage cache
by Kyösti Mälkki (Code Review) 27 Apr '20

27 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37683 ) Change subject: arch/x86: Fix S3 resume without stage cache ...................................................................... arch/x86: Fix S3 resume without stage cache It is possible to have NO_STAGE_CACHE=n and at the same time have TSEG_STAGE_CACHE=n and CBMEB_STAGE_CACHE=n. This resulted with a failing attempt to load STAGE_POSTCAR from the stage cache, but not loading it from CBFS either. Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/postcar_loader.c 1 file changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/37683/1 diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b53cbf8..46a62e8 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> #include <program_loading.h> +#include <reset.h> #include <rmodule.h> #include <romstage_handoff.h> #include <stage_cache.h> @@ -208,6 +209,15 @@ MTRR_TYPE_WRBACK); } +static void postcar_cache_invalid(void) +{ + if (!CONFIG(TSEG_STAGE_CACHE) && !CONFIG(CBMEM_STAGE_CACHE)) + return; + + printk(BIOS_ERR, "postcar cache invalid.\n"); + board_reset(); +} + void run_postcar_phase(struct postcar_frame *pcf) { struct prog prog = @@ -215,14 +225,19 @@ postcar_commit_mtrrs(pcf); - if (!CONFIG(NO_STAGE_CACHE) && - romstage_handoff_is_resume()) { + if (romstage_handoff_is_resume()) { stage_cache_load_stage(STAGE_POSTCAR, &prog); + /* This is here to allow platforms to pass different stack parameters between S3 resume and normal boot. On the platforms where the values are the same it's a nop. */ - finalize_load(prog.arg, pcf->stack); - } else + if (prog_entry(&prog) != NULL) + finalize_load(prog.arg, pcf->stack); + else + postcar_cache_invalid(); + } + + if (prog_entry(&prog) == NULL) load_postcar_cbfs(&prog, pcf); /* As postcar exist, it's end of romstage here */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37683 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0da3e1cf4c92817ffabbb02eda3476ecdfdfa278 Gerrit-Change-Number: 37683 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: Documentation: Add VBOOT on Lenovo devices
by Patrick Rudolph (Code Review) 27 Apr '20

27 Apr '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39151 ) Change subject: Documentation: Add VBOOT on Lenovo devices ...................................................................... Documentation: Add VBOOT on Lenovo devices Describe VBOOT implementation details for retrofitted Lenovo devices. Change-Id: Ibabcc939d9d01f00a93fd42adc48057966ad877e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/vboot.md 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/39151/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 126a8fb..6e833cf 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -70,6 +70,7 @@ - [R60](lenovo/r60.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [VBOOT](lenovo/vboot.md) ### Nehalem series diff --git a/Documentation/mainboard/lenovo/vboot.md b/Documentation/mainboard/lenovo/vboot.md new file mode 100644 index 0000000..559ea53 --- /dev/null +++ b/Documentation/mainboard/lenovo/vboot.md @@ -0,0 +1,35 @@ +# Using coreboot's verified boot on Lenovo devices + +By default a single instance of coreboot is present in the firmware flash, +no verification is done and it doesn't write protect the flash to allow +firmware updates from the OS. +The verified boot mechanism also called [VBOOT] allows secure firmware +updates using an A/B partitioning scheme once enabled. + +## Enabling VBOOT +You can enable [VBOOT] in the *security menu*. Besides a verified boot you +can also enable a measured boot by setting `CONFIG_VBOOT_MEASURED_BOOT`. +Both options need a working TPM, which is present on all recent Lenovo +devices. + +## Updating and recovery +As the A/B partition is writeable you can still update them from the OS. +By using the [VBOOT] mechanism you store a copy of coreboot in the `RO` +partition that acts as failsaife in case the regular firmware update, that +goes the `A` or `B` partition fails. + +On *Lenovo* devices you can enable the *Fn* key as recovery mode switch, by +enabling `CONFIG_H8_FN_KEY_AS_VBOOT_RECOVERY_SW`. +Holding the *Fn* at boot will then switch to the recovery image, allowing +to boot and flash a working image to the A/B partition. + +## 8MiB ROM limitation +*Lenovo* devices with 8MiB ROM only have a `RO`+`A` partition enabled in the +default FMAP. They are missing the `B` partition, due to size contrains. +You can still provide your own FMAP if you need `RO`+`A`+`B` partitions. + +## CMOS +[VBOOT] on *Lenovo* devices uses the CMOS to store configuration data, like +boot failures and the last successfully booted partition. + +[VBOOT]: ../../security/vboot/index.md -- To view, visit https://review.coreboot.org/c/coreboot/+/39151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibabcc939d9d01f00a93fd42adc48057966ad877e Gerrit-Change-Number: 39151 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: asus/p2b-ls: Replicate OEM GPO/PM configurations
by Keith Hui (Code Review) 25 Apr '20

25 Apr '20

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38354 ) Change subject: asus/p2b-ls: Replicate OEM GPO/PM configurations ...................................................................... asus/p2b-ls: Replicate OEM GPO/PM configurations Replicate the entire GPO/lid/thermal configuration from OEM BIOS. Among the GPOs are termination controls for the onboard SCSI buses. Requires /c/38352 to function. Change-Id: I86183acd8e1a830d7639c21ec179fbdbe937f8ee Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/mainboard/asus/p2b-ls/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/38354/1 diff --git a/src/mainboard/asus/p2b-ls/devicetree.cb b/src/mainboard/asus/p2b-ls/devicetree.cb index a9901b4..5e55278 100644 --- a/src/mainboard/asus/p2b-ls/devicetree.cb +++ b/src/mainboard/asus/p2b-ls/devicetree.cb @@ -8,6 +8,10 @@ device pci 0.0 on end # Host bridge device pci 1.0 on end # PCI/AGP bridge chip southbridge/intel/i82371eb # Southbridge + register "gpo" = "0x7fbfb9ff" + register "gpo22_enable" = "1" + register "lid_polarity" = "1" + register "thrm_polarity" = "1" device pci 4.0 on # ISA bridge chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!) device pnp 3f0.0 on # Floppy -- To view, visit https://review.coreboot.org/c/coreboot/+/38354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86183acd8e1a830d7639c21ec179fbdbe937f8ee Gerrit-Change-Number: 38354 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-MessageType: newchange

5 22

Change in coreboot[master]: mb/google/hatch: Change baseboard EC wake & SCI masks to match kohaku
by Tim Wawrzynczak (Code Review) 24 Apr '20

24 Apr '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38735 ) Change subject: mb/google/hatch: Change baseboard EC wake & SCI masks to match kohaku ...................................................................... mb/google/hatch: Change baseboard EC wake & SCI masks to match kohaku 1) Allows MKBP events from the EC to wake the system from suspend states. 2) Remove EC_HOST_EVENT_MKBP from the EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:148976961 BRANCH=firmware-hatch-12672.B TEST=Verify MKBP events wake system TEST=Verify MKBP IRQs are run Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h 2 files changed, 2 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/38735/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h index 3aa9414..d6a4a97 100644 --- a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/ec.h @@ -32,8 +32,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_SMI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) @@ -50,6 +49,7 @@ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS \ diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index 377b703..cfe954f 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -20,29 +20,4 @@ #define EC_ENABLE_MULTIPLE_DPTF_PROFILES -/* Add EC_HOST_EVENT_MKBP from baseboard */ -#undef MAINBOARD_EC_S3_WAKE_EVENTS -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -/* Removing EC_HOST_EVENT_MKBP from baseboard mask */ -#undef MAINBOARD_EC_SCI_EVENTS -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - #endif /* VARIANT_EC_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8420a996cb1975007cbbbefe9e2f8f1fca91b666 Gerrit-Change-Number: 38735 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8183: Force retraining memory if requested
by Hung-Te Lin (Code Review) 23 Apr '20

23 Apr '20

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36251 ) Change subject: soc/mediatek/mt8183: Force retraining memory if requested ...................................................................... soc/mediatek/mt8183: Force retraining memory if requested To allow retraining memory without hotkey (for example in manufacturing process), we want to enforce re-training when the recovery reason is set to VB2_RECOVERY_TRAIN_AND_REBOOT (which can be done by running "crossystem recovery_request=0xc4"). On x86 (MRC cache) this is primarily used for ensuring RO calibration data is filled; and on MT8183 we have only RW calibration, but it seems totally fine to extend that to RW. BRANCH=kukui BUG=None TEST=boots; crossystem recovery_reason=0xc4; reboot Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/36251/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 2a4ebbd..b9ed619 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -169,7 +169,8 @@ /* Load calibration params from flash and run fast calibration */ if (recovery_mode) { printk(BIOS_WARNING, "Skip loading cached calibration data\n"); - if (vboot_recovery_mode_memory_retrain()) { + if (vboot_recovery_mode_memory_retrain() || + vboot_check_recovery_request() == VB2_RECOVERY_TRAIN_AND_REBOOT) { printk(BIOS_WARNING, "Retrain memory in next boot\n"); /* Use 0xFF as erased flash data. */ memset(dparam, 0xff, sizeof(*dparam)); -- To view, visit https://review.coreboot.org/c/coreboot/+/36251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa5275f0e0eb90f6ab3a7d4579977a6655d59bd9 Gerrit-Change-Number: 36251 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/agesa: Make BottomIo position configurable
by Mike Banon (Code Review) 22 Apr '20

22 Apr '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38472 ) Change subject: amd/agesa: Make BottomIo position configurable ...................................................................... amd/agesa: Make BottomIo position configurable Some PCI peripherals, such as discrete VGA adapters, require a great amount of memory mapped IO. This patch allows the user to select at build time the bottom IO to leave enough space for such devices. We cannot calculate this value at runtime because it has to be set before the PCI devices are enumerated. 0x40000000 has been successfully boot-tested on A88XM-E (fam15tn), G505S (fam15tn) and AM1I-A (fam16kb). Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0 --- M src/northbridge/amd/agesa/Kconfig M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/amd/agesa/family15tn/state_machine.c M src/northbridge/amd/agesa/family16kb/state_machine.c 4 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/38472/1 diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index e1e129a..346e2c3 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -20,6 +20,18 @@ if NORTHBRIDGE_AMD_AGESA +config BOTTOMIO_POSITION + hex "Bottom of 32-bit IO space" + default 0x40000000 + help + If PCI peripherals with big BARs are connected to the system + the bottom of the IO must be decreased to allocate such + devices. + + Declare the beginning of the 128MB-aligned MMIO region. This + option is useful when PCI peripherals requesting large address + ranges are present. + config CONSOLE_VGA_MULTI bool default n diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index b49dac0..345f36a 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -60,6 +60,7 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { + Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24); } void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) diff --git a/src/northbridge/amd/agesa/family15tn/state_machine.c b/src/northbridge/amd/agesa/family15tn/state_machine.c index dafb64c..092c781 100644 --- a/src/northbridge/amd/agesa/family15tn/state_machine.c +++ b/src/northbridge/amd/agesa/family15tn/state_machine.c @@ -30,6 +30,7 @@ void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) { + Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24); } void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) diff --git a/src/northbridge/amd/agesa/family16kb/state_machine.c b/src/northbridge/amd/agesa/family16kb/state_machine.c index 7794f2d..0ffa5d5 100644 --- a/src/northbridge/amd/agesa/family16kb/state_machine.c +++ b/src/northbridge/amd/agesa/family16kb/state_machine.c @@ -32,6 +32,8 @@ { AGESA_STATUS status; + Post->MemConfig.BottomIo = (UINT16)(CONFIG_BOTTOMIO_POSITION >> 24); + if (CONFIG(ENABLE_MRC_CACHE)) { status = OemInitResume(&Post->MemConfig.MemContext); if (status == AGESA_SUCCESS) -- To view, visit https://review.coreboot.org/c/coreboot/+/38472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie235631231bcb4aeebaff2e0026da2ea9d82f9d0 Gerrit-Change-Number: 38472 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/apl: Add chip.h setting for PCIe ASPM
by Thomas Heijligen (Code Review) 22 Apr '20

22 Apr '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31351 to review the following change. Change subject: soc/intel/apl: Add chip.h setting for PCIe ASPM ...................................................................... soc/intel/apl: Add chip.h setting for PCIe ASPM We don't use a direct mapping to the UPD values so we don't have to set it to the default `auto` in all devicetrees. Change-Id: I169722c3c63be66772cb57a429ec7b83230fa234 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/31351/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 3634509..cfe8d4a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -669,6 +669,7 @@ { FSP_S_CONFIG *silconfig = &silupd->FspsConfig; static struct soc_intel_apollolake_config *cfg; + int i; /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); @@ -693,6 +694,11 @@ memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, sizeof(silconfig->PcieRpHotPlug)); + for (i = 0; i < ARRAY_SIZE(silconfig->PcieRpAspm); ++i) { + if (cfg->pcie_rp_aspm[i] != ASPM_IGNORE) + silconfig->PcieRpAspm[i] = cfg->pcie_rp_aspm[i] - 1; + } + switch (cfg->serirq_mode) { case SERIRQ_QUIET: silconfig->SirqEnable = 1; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b9e368c..b8f9f8c 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -57,6 +57,18 @@ /* De-emphasis enable configuration for each PCIe root port */ uint8_t pcie_rp_deemphasis_enable[MAX_PCIE_PORTS]; + /* ASPM enable setting for each PCIe root port */ + enum { + ASPM_IGNORE = 0, + /* Enumeration values below are off-by-one compared to the + UPD to have the default 0 ignore the devicetree setting: */ + ASPM_DISABLED, + ASPM_L0S, + ASPM_L1, + ASPM_L0SL1, + ASPM_AUTO, + } pcie_rp_aspm[MAX_PCIE_PORTS]; + /* [14:8] DDR mode Number of dealy elements.Each = 125pSec. * [6:0] SDR mode Number of dealy elements.Each = 125pSec. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I169722c3c63be66772cb57a429ec7b83230fa234 Gerrit-Change-Number: 31351 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: sc7180: Add SPI QUP driver
by mturney mturney (Code Review) 21 Apr '20

21 Apr '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36517 ) Change subject: sc7180: Add SPI QUP driver ...................................................................... sc7180: Add SPI QUP driver This implements the SPI driver for the QUP core. Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/mainboard/google/trogdor/bootblock.c M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h M src/soc/qualcomm/sc7180/qcom_qup_se.c M src/soc/qualcomm/sc7180/spi.c A src/soc/qualcomm/sc7180/spi_qup.c 6 files changed, 310 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/36517/1 diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c index c658093..a109a08 100644 --- a/src/mainboard/google/trogdor/bootblock.c +++ b/src/mainboard/google/trogdor/bootblock.c @@ -15,8 +15,12 @@ #include <bootblock_common.h> #include "board.h" +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> void bootblock_mainboard_init(void) { setup_chromeos_gpios(); + qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* H1 SPI */ + qup_spi_init(QUPV3_1_SE4, 1010 * KHz); /* EC SPI */ } diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 18f8ada..66cb35c 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -6,6 +6,7 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-y += spi_qup.c bootblock-y += gpio.c bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c bootblock-y += clock.c @@ -17,6 +18,7 @@ ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-y += spi_qup.c verstage-y += gpio.c verstage-y += clock.c verstage-y += qcom_qup_se.c @@ -32,6 +34,7 @@ romstage-y += mmu.c romstage-y += usb.c romstage-y += spi.c +romstage-y += spi_qup.c romstage-y += gpio.c romstage-y += clock.c romstage-y += qcom_qup_se.c @@ -43,6 +46,7 @@ ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += spi.c +ramstage-y += spi_qup.c ramstage-y += gpio.c ramstage-y += clock.c ramstage-y += qupv3_fw_config.c diff --git a/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h b/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h new file mode 100644 index 0000000..4999422 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/spi_qup_qcom.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2018-2019 Qualcomm Technologies + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SPI_QUP_QCOM_HEADER___ +#define __SPI_QUP_QCOM_HEADER___ + +#include <spi-generic.h> + +int qup_spi_claim_bus(const struct spi_slave *slave); +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in); +void qup_spi_release_bus(const struct spi_slave *slave); +void qup_spi_init(unsigned int bus, unsigned int speed_hz); + +#endif /*__SPI_QUP_QCOM_HEADER___*/ diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c index 1774a2c..d14a852 100644 --- a/src/soc/qualcomm/sc7180/qcom_qup_se.c +++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c @@ -92,7 +92,6 @@ if (m_irq) break; } - write32(&regs->geni_m_irq_clear, m_irq); return m_irq; } @@ -147,17 +146,38 @@ void qup_handle_error(unsigned int bus) { struct qup_regs *regs = qup[bus].regs; + struct stopwatch sw; + unsigned int m_irq; write32(&regs->geni_tx_watermark_reg, 0); write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL); - if (!wait_us(100, qup_wait_for_irq(bus) & M_CMD_CANCEL_EN)) { + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(bus); + if (m_irq & M_CMD_CANCEL_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_CANCEL_EN)) { printk(BIOS_INFO, "%s:Cancel failed" ",Abort the operation\n", __func__); - write32(&regs->geni_m_cmd_ctrl_reg, - M_GENI_CMD_ABORT); - if (!wait_us(100, qup_wait_for_irq(bus) & M_CMD_ABORT_EN)) + write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT); + stopwatch_init_msecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(bus); + if (m_irq & M_CMD_ABORT_EN) { + write32(&regs->geni_m_irq_clear, m_irq); + break; + } + write32(&regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_ABORT_EN)) printk(BIOS_INFO, "%s:Abort failed\n", __func__); } } @@ -168,6 +188,7 @@ struct stopwatch sw; unsigned int rx_rem_bytes = din ? size : 0; unsigned int tx_rem_bytes = dout ? size : 0; + struct qup_regs *regs = qup[bus].regs; stopwatch_init_msecs_expire(&sw, 1000); do { @@ -179,8 +200,11 @@ if (m_irq & M_TX_FIFO_WATERMARK_EN) tx_rem_bytes -= handle_tx(bus, dout + size - tx_rem_bytes, tx_rem_bytes); - if (m_irq & M_CMD_DONE_EN) + if (m_irq & M_CMD_DONE_EN) { + write32(&regs->geni_m_irq_clear, m_irq); break; + } + write32(&regs->geni_m_irq_clear, m_irq); } while (!stopwatch_expired(&sw)); if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) { diff --git a/src/soc/qualcomm/sc7180/spi.c b/src/soc/qualcomm/sc7180/spi.c index c6d4cb1..4146032 100644 --- a/src/soc/qualcomm/sc7180/spi.c +++ b/src/soc/qualcomm/sc7180/spi.c @@ -16,6 +16,7 @@ #include <spi-generic.h> #include <spi_flash.h> #include <soc/qspi.h> +#include <soc/spi_qup_qcom.h> static const struct spi_ctrlr qspi_ctrlr = { .claim_bus = sc7180_claim_bus, @@ -25,12 +26,24 @@ .max_xfer_size = QSPI_MAX_PACKET_COUNT, }; +const struct spi_ctrlr spi_qup_ctrlr = { + .claim_bus = qup_spi_claim_bus, + .release_bus = qup_spi_release_bus, + .xfer = qup_spi_xfer, + .max_xfer_size = 65535, +}; + const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, + { + .ctrlr = &spi_qup_ctrlr, + .bus_start = 0, + .bus_end = 11, + }, }; const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); diff --git a/src/soc/qualcomm/sc7180/spi_qup.c b/src/soc/qualcomm/sc7180/spi_qup.c new file mode 100644 index 0000000..6953c6a --- /dev/null +++ b/src/soc/qualcomm/sc7180/spi_qup.c @@ -0,0 +1,232 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018-2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <delay.h> +#include <lib.h> +#include <soc/clock.h> +#include <soc/gpio.h> +#include <soc/qcom_qup_se.h> +#include <soc/spi_qup_qcom.h> + +/* SE_SPI_LOOPBACK register fields */ +#define LOOPBACK_ENABLE 0x1 + +/* SE_SPI_WORD_LEN register fields */ +#define WORD_LEN_MSK GENMASK(9, 0) +#define MIN_WORD_LEN 4 + +/* SPI_TX/SPI_RX_TRANS_LEN fields */ +#define TRANS_LEN_MSK GENMASK(23, 0) + +/* M_CMD OP codes for SPI */ +#define SPI_TX_ONLY 1 +#define SPI_RX_ONLY 2 +#define SPI_FULL_DUPLEX 3 +#define SPI_TX_RX 7 +#define SPI_CS_ASSERT 8 +#define SPI_CS_DEASSERT 9 +#define SPI_SCK_ONLY 10 + +/* M_CMD params for SPI */ +/* If fragmentation bit is set then CS will not toggle after each transfer */ +#define M_CMD_FRAGMENTATION BIT(2) + +#define BITS_PER_BYTE 8 +#define BITS_PER_WORD 8 +#define TX_WATERMARK 1 + +#define IRQ_TRIGGER (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN | \ + M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN | \ + M_CMD_CANCEL_EN | M_CMD_ABORT_EN) + +static void setup_fifo_params(const struct spi_slave *slave) +{ + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + u32 word_len = 0; + + /* Disable loopback mode */ + write32(&regs->proto_loopback_cfg, 0); + + write32(&regs->spi_demux_sel, slave->cs); + word_len = ((BITS_PER_WORD - MIN_WORD_LEN) & WORD_LEN_MSK); + write32(&regs->word_len.spi_word_len, word_len); + + /* FIFO PACKING CONFIGURATION */ + write32(&regs->geni_tx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_tx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_rx_packing_cfg0, PACK_VECTOR0 + | (PACK_VECTOR1 << 10)); + write32(&regs->geni_rx_packing_cfg1, PACK_VECTOR2 + | (PACK_VECTOR3 << 10)); + write32(&regs->geni_byte_granularity, (log2(BITS_PER_WORD) - 3)); +} + +static void qup_setup_m_cmd(unsigned int se_bus, u32 cmd, u32 params) +{ + struct qup_regs *regs = qup[se_bus].regs; + u32 m_cmd = (cmd << M_OPCODE_SHFT); + + m_cmd |= (params & M_PARAMS_MSK); + write32(&regs->geni_m_cmd0, m_cmd); +} + +int qup_spi_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) +{ + u32 m_cmd = 0; + u32 m_param = M_CMD_FRAGMENTATION; + int size; + unsigned int se_bus = slave->bus; + struct qup_regs *regs = qup[se_bus].regs; + + if ((bytes_in == 0) && (bytes_out == 0)) + return 0; + + setup_fifo_params(slave); + + if (!bytes_out) { + size = bytes_in; + m_cmd = SPI_RX_ONLY; + dout = NULL; + } else if (!bytes_in) { + size = bytes_out; + m_cmd = SPI_TX_ONLY; + din = NULL; + } else { + size = MIN(bytes_in, bytes_out); + m_cmd = SPI_FULL_DUPLEX; + } + + /* Check for maximum permissible transfer length */ + assert(!(size & ~TRANS_LEN_MSK)); + + if (bytes_out) { + write32(&regs->tx_trans_len.spi_tx_trans_len, size); + write32(&regs->geni_tx_watermark_reg, TX_WATERMARK); + } + if (bytes_in) + write32(&regs->rx_trans_len.spi_rx_trans_len, size); + + qup_setup_m_cmd(se_bus, m_cmd, m_param); + + if (qup_handle_transfer(se_bus, dout, din, size)) + return -1; + + qup_spi_xfer(slave, dout + size, MAX((int)bytes_out - size, 0), + din + size, MAX((int)bytes_in - size, 0)); + + return 0; +} + +static int spi_qup_set_cs(const struct spi_slave *slave, bool enable) +{ + u32 m_cmd = 0; + u32 m_irq = 0; + unsigned int se_bus = slave->bus; + struct stopwatch sw; + + m_cmd = (enable) ? SPI_CS_ASSERT : SPI_CS_DEASSERT; + qup_setup_m_cmd(se_bus, m_cmd, 0); + + stopwatch_init_usecs_expire(&sw, 100); + do { + m_irq = qup_wait_for_irq(se_bus); + if (m_irq & M_CMD_DONE_EN) { + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + break; + } + write32(&qup[se_bus].regs->geni_m_irq_clear, m_irq); + } while (!stopwatch_expired(&sw)); + + if (!(m_irq & M_CMD_DONE_EN)) { + printk(BIOS_INFO, "%s:Failed to %s chip\n", __func__, + (enable) ? "Assert" : "Deassert"); + qup_handle_error(se_bus); + return -1; + } + return 0; +} + +void qup_spi_init(unsigned int bus, unsigned int speed_hz) +{ + u32 m_clk_cfg = 0, div = DEFAULT_SE_CLK / speed_hz; + struct qup_regs *regs = qup[bus].regs; + + /* Make sure div can hit target frequency within +/- 1KHz range */ + assert(((DEFAULT_SE_CLK - speed_hz * div) <= div * KHz) && (div > 0)); + clock_enable_qup(bus); + m_clk_cfg |= ((div << CLK_DIV_SHFT) | SER_CLK_EN); + write32(&regs->geni_ser_m_clk_cfg, m_clk_cfg); + /* Mode:0, cpha=0, cpol=0 */ + write32(&regs->spi_cpha, 0); + write32(&regs->spi_cpol, 0); + /* Disable DFS */ + clrbits_le32(&regs->geni_dfs_if_cfg, + GENI_DFS_IF_CFG_DFS_IF_EN_BMSK); + + /* Serial engine IO initialization */ + write32(&regs->geni_cgc_ctrl, DEFAULT_CGC_EN); + write32(&regs->dma_general_cfg, + (AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON + | DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON)); + write32(&regs->geni_output_ctrl, + DEFAULT_IO_OUTPUT_CTRL_MSK); + write32(&regs->geni_force_default_reg, FORCE_DEFAULT); + + /* Serial engine IO set mode */ + write32(&regs->se_irq_en, (GENI_M_IRQ_EN | + GENI_S_IRQ_EN | DMA_TX_IRQ_EN | DMA_RX_IRQ_EN)); + write32(&regs->se_gsi_event_en, 0); + + /* Set RX and RFR watermark */ + write32(&regs->geni_rx_watermark_reg, 0); + write32(&regs->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2); + + /* GPIO Configuration */ + gpio_configure(qup[bus].pin[0], qup[bus].func[0], GPIO_NO_PULL, + GPIO_6MA, GPIO_INPUT); /* MISO */ + gpio_configure(qup[bus].pin[1], qup[bus].func[1], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* MOSI */ + gpio_configure(qup[bus].pin[2], qup[bus].func[2], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CLK */ + gpio_configure(qup[bus].pin[3], qup[bus].func[3], GPIO_NO_PULL, + GPIO_6MA, GPIO_OUTPUT); /* CS */ + + /* Select and setup FIFO mode */ + write32(&regs->geni_m_irq_clear, 0xFFFFFFFF); + write32(&regs->geni_s_irq_clear, 0xFFFFFFFF); + write32(&regs->dma_tx_irq_clr, 0xFFFFFFFF); + write32(&regs->dma_rx_irq_clr, 0xFFFFFFFF); + write32(&regs->geni_m_irq_enable, (M_COMMON_GENI_M_IRQ_EN | + M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | + M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)); + write32(&regs->geni_s_irq_enable, (S_COMMON_GENI_S_IRQ_EN + | S_CMD_DONE_EN)); + clrbits_le32(&regs->geni_dma_mode_en, GENI_DMA_MODE_EN); +} + +int qup_spi_claim_bus(const struct spi_slave *slave) +{ + return spi_qup_set_cs(slave, 1); +} + +void qup_spi_release_bus(const struct spi_slave *slave) +{ + spi_qup_set_cs(slave, 0); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/36517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86f4fcff6f9537373f70a43711130d7f28bd5e09 Gerrit-Change-Number: 36517 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: [TESTONLY] binaryPI: Re-enable boards to build
by Kyösti Mälkki (Code Review) 20 Apr '20

20 Apr '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37176 ) Change subject: [TESTONLY] binaryPI: Re-enable boards to build ...................................................................... [TESTONLY] binaryPI: Re-enable boards to build This reverts commit 9847152c831fe206d47bc6858389a5425e2d778c. Change-Id: Ifa07ba9df80488135c7d7cbc8be20e36655f7a65 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/amd/bettong/Kconfig M src/mainboard/amd/bettong/Kconfig.name M src/mainboard/amd/db-ft3b-lc/Kconfig M src/mainboard/amd/db-ft3b-lc/Kconfig.name M src/mainboard/amd/lamar/Kconfig M src/mainboard/amd/lamar/Kconfig.name M src/mainboard/amd/olivehillplus/Kconfig M src/mainboard/amd/olivehillplus/Kconfig.name M src/mainboard/bap/ode_e21XX/Kconfig M src/mainboard/bap/ode_e21XX/Kconfig.name 10 files changed, 10 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37176/1 diff --git a/src/mainboard/amd/bettong/Kconfig b/src/mainboard/amd/bettong/Kconfig index 5d55679..46f0cfe 100644 --- a/src/mainboard/amd/bettong/Kconfig +++ b/src/mainboard/amd/bettong/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_BETTONG - def_bool n - if BOARD_AMD_BETTONG config BOARD_SPECIFIC_OPTIONS def_bool y - #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00660F01 select NORTHBRIDGE_AMD_PI_00660F01 select SOUTHBRIDGE_AMD_PI_KERN diff --git a/src/mainboard/amd/bettong/Kconfig.name b/src/mainboard/amd/bettong/Kconfig.name index 4bd1329..09201b5 100644 --- a/src/mainboard/amd/bettong/Kconfig.name +++ b/src/mainboard/amd/bettong/Kconfig.name @@ -1,3 +1,2 @@ -# Disabled -#config BOARD_AMD_BETTONG -# bool "Bettong" +config BOARD_AMD_BETTONG + bool "Bettong" diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index 6a7ca87..2aecaa1 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_DB_FT3B_LC - def_bool n - if BOARD_AMD_DB_FT3B_LC config BOARD_SPECIFIC_OPTIONS def_bool y - #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig.name b/src/mainboard/amd/db-ft3b-lc/Kconfig.name index 3197a70..7caf95d 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig.name +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig.name @@ -1,3 +1,2 @@ -# Disabled -#config BOARD_AMD_DB_FT3B_LC -# bool "DB-FT3b-LC" +config BOARD_AMD_DB_FT3B_LC + bool "DB-FT3b-LC" diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig index bc3859d..26d6c33 100644 --- a/src/mainboard/amd/lamar/Kconfig +++ b/src/mainboard/amd/lamar/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_LAMAR - def_bool n - if BOARD_AMD_LAMAR config BOARD_SPECIFIC_OPTIONS def_bool y - #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00630F01 select NORTHBRIDGE_AMD_PI_00630F01 select SOUTHBRIDGE_AMD_PI_BOLTON diff --git a/src/mainboard/amd/lamar/Kconfig.name b/src/mainboard/amd/lamar/Kconfig.name index 75eec04..1831b9a 100644 --- a/src/mainboard/amd/lamar/Kconfig.name +++ b/src/mainboard/amd/lamar/Kconfig.name @@ -1,3 +1,2 @@ -# Disabled -#config BOARD_AMD_LAMAR -# bool "Lamar" +config BOARD_AMD_LAMAR + bool "Lamar" diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 490e0a6..9bfd83a 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_AMD_OLIVEHILLPLUS - def_bool n - if BOARD_AMD_OLIVEHILLPLUS config BOARD_SPECIFIC_OPTIONS def_bool y - #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/amd/olivehillplus/Kconfig.name b/src/mainboard/amd/olivehillplus/Kconfig.name index 1ce4a20..85a3e86 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig.name +++ b/src/mainboard/amd/olivehillplus/Kconfig.name @@ -1,3 +1,2 @@ -# Disabled -#config BOARD_AMD_OLIVEHILLPLUS -# bool "Olive Hill Plus" +config BOARD_AMD_OLIVEHILLPLUS + bool "Olive Hill Plus" diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index c371631..77ec98a 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -13,14 +13,10 @@ # GNU General Public License for more details. # -config BOARD_ODE_E21XX - def_bool n - if BOARD_ODE_E21XX config BOARD_SPECIFIC_OPTIONS def_bool y - #select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/bap/ode_e21XX/Kconfig.name b/src/mainboard/bap/ode_e21XX/Kconfig.name index 64665da..5ef8804 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig.name +++ b/src/mainboard/bap/ode_e21XX/Kconfig.name @@ -1,3 +1,2 @@ -# Disabled -#config BOARD_ODE_E21XX -# bool "ODE_e21xx" +config BOARD_ODE_E21XX + bool "ODE_e21xx" -- To view, visit https://review.coreboot.org/c/coreboot/+/37176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa07ba9df80488135c7d7cbc8be20e36655f7a65 Gerrit-Change-Number: 37176 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: libpayload: Make 8250 UART driver relocation safe
by Nico Huber (Code Review) 20 Apr '20

20 Apr '20

Hello Julius Werner, Reto Buerki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/37513 to review the following change. Change subject: libpayload: Make 8250 UART driver relocation safe ...................................................................... libpayload: Make 8250 UART driver relocation safe `lib_sysinfo->serial` is a virtual pointer into coreboot tables. It's not valid across relocation. Work around that by caching the whole table entry locally. The better alternative would be to revise `sysinfo`, to contain no virtual pointers to anything outside the payload. Change-Id: I03adaf57b83a177316d7778f7e06df8eb6f9158e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/drivers/serial/8250.c 1 file changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/37513/1 diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c index 9502d4b..4a7cc01 100644 --- a/payloads/libpayload/drivers/serial/8250.c +++ b/payloads/libpayload/drivers/serial/8250.c @@ -31,7 +31,9 @@ #include <libpayload-config.h> #include <libpayload.h> -#define IOBASE lib_sysinfo.serial->baseaddr +static struct cb_serial cb_serial; + +#define IOBASE cb_serial.baseaddr #define MEMBASE (phys_to_virt(IOBASE)) static int serial_hardware_is_present = 0; @@ -39,14 +41,14 @@ static uint8_t serial_read_reg(int offset) { - offset *= lib_sysinfo.serial->regwidth; + offset *= cb_serial.regwidth; #if CONFIG(LP_IO_ADDRESS_SPACE) if (!serial_is_mem_mapped) return inb(IOBASE + offset); else #endif - if (lib_sysinfo.serial->regwidth == 4) + if (cb_serial.regwidth == 4) return readl(MEMBASE + offset) & 0xff; else return readb(MEMBASE + offset); @@ -54,14 +56,14 @@ static void serial_write_reg(uint8_t val, int offset) { - offset *= lib_sysinfo.serial->regwidth; + offset *= cb_serial.regwidth; #if CONFIG(LP_IO_ADDRESS_SPACE) if (!serial_is_mem_mapped) outb(val, IOBASE + offset); else #endif - if (lib_sysinfo.serial->regwidth == 4) + if (cb_serial.regwidth == 4) writel(val & 0xff, MEMBASE + offset); else writeb(val, MEMBASE + offset); @@ -108,11 +110,7 @@ void serial_init(void) { - if (!lib_sysinfo.serial) - return; - - serial_is_mem_mapped = - (lib_sysinfo.serial->type == CB_SERIAL_TYPE_MEMORY_MAPPED); + serial_is_mem_mapped = (cb_serial.type == CB_SERIAL_TYPE_MEMORY_MAPPED); if (!serial_is_mem_mapped) { #if CONFIG(LP_IO_ADDRESS_SPACE) @@ -130,15 +128,16 @@ #if CONFIG(LP_SERIAL_SET_SPEED) serial_hardware_init(CONFIG_LP_SERIAL_BAUD_RATE, 8, 0, 1); #endif + serial_hardware_is_present = 1; } void serial_console_init(void) { if (!lib_sysinfo.serial) return; + cb_serial = *lib_sysinfo.serial; serial_init(); - serial_hardware_is_present = 1; console_add_input_driver(&consin); console_add_output_driver(&consout); -- To view, visit https://review.coreboot.org/c/coreboot/+/37513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03adaf57b83a177316d7778f7e06df8eb6f9158e Gerrit-Change-Number: 37513 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020