coreboot-gerrit February 2020

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Change in ...coreboot[master]: src/cpu/x86: Check pointer processor_name_start before dereference
by John Zhao (Code Review) 20 May '20

20 May '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33232 Change subject: src/cpu/x86: Check pointer processor_name_start before dereference ...................................................................... src/cpu/x86: Check pointer processor_name_start before dereference Clang Static Analyzer version 8.0.0 detects the left operand of '==' is a garbage value if pointer processor_name_start is NULL. Add sanity check for processor_name_start before dereference. TEST=Built and boot up to kernel. Change-Id: I1f831a8661a4686d306b8217655942934102ea16 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/cpu/x86/name/name.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/33232/1 diff --git a/src/cpu/x86/name/name.c b/src/cpu/x86/name/name.c index fc360cd..44a1cf0 100644 --- a/src/cpu/x86/name/name.c +++ b/src/cpu/x86/name/name.c @@ -37,6 +37,9 @@ /* Skip leading spaces. */ processor_name_start = (char *)name_as_ints; + if (!processor_name_start) + return; + while (*processor_name_start == ' ') processor_name_start++; -- To view, visit https://review.coreboot.org/c/coreboot/+/33232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f831a8661a4686d306b8217655942934102ea16 Gerrit-Change-Number: 33232 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in vboot[master]: vboot: Avoid insecure data handling
by John Zhao (Code Review) 20 May '20

20 May '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/vboot/+/35021 ) Change subject: vboot: Avoid insecure data handling ...................................................................... vboot: Avoid insecure data handling Coverity detects the overflowed value "rev" used as return value. Cast the value "rev" to integer after strtol invocation. BUG=CID 1401793 TEST=Built and boot up to kernel. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Idcb48d9a8f7c89744c66f50affb5f9acc6aa4c12 --- M futility/updater.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/vboot refs/changes/21/35021/1 diff --git a/futility/updater.c b/futility/updater.c index ef142b8..14dd469 100644 --- a/futility/updater.c +++ b/futility/updater.c @@ -234,7 +234,7 @@ /* Result should be 'revN' */ if (strncmp(result, STR_REV, strlen(STR_REV)) == 0) - rev = strtol(result + strlen(STR_REV), NULL, 0); + rev = (int)strtol(result + strlen(STR_REV), NULL, 0); VB2_DEBUG("Raw data = [%s], parsed version is %d\n", result, rev); free(result); -- To view, visit https://review.coreboot.org/c/vboot/+/35021 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: vboot Gerrit-Branch: master Gerrit-Change-Id: Idcb48d9a8f7c89744c66f50affb5f9acc6aa4c12 Gerrit-Change-Number: 35021 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: [TESTME]AGESA: Try to fix S3 resume on CONFIG_NO_STAGE_CACHE
by Arthur Heymans (Code Review) 20 May '20

20 May '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37180 ) Change subject: [TESTME]AGESA: Try to fix S3 resume on CONFIG_NO_STAGE_CACHE ...................................................................... [TESTME]AGESA: Try to fix S3 resume on CONFIG_NO_STAGE_CACHE TODO: What MTRR's does AGESA set up on the s3 resume path? Change-Id: I8f9d9d4c0116c965570e289a0b0df7d5f739acde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/agesa/Kconfig M src/drivers/amd/agesa/mtrr_fixme.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/37180/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index ddfe707..84fcaef 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -26,7 +26,6 @@ select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select CBMEM_STAGE_CACHE if HAVE_ACPI_RESUME select SMM_ASEG select NO_FIXED_XIP_ROM_SIZE diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index bbb9eb0..37795e9 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -48,7 +48,7 @@ void fixup_cbmem_to_UC(int s3resume) { - if (s3resume) + if (s3resume && !CONFIG(NO_STAGE_CACHE)) return; /* For normal path, INIT_POST has returned with all -- To view, visit https://review.coreboot.org/c/coreboot/+/37180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f9d9d4c0116c965570e289a0b0df7d5f739acde Gerrit-Change-Number: 37180 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: lib/fmap.c: Properly handle cache for !C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 20 May '20

20 May '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36908 ) Change subject: lib/fmap.c: Properly handle cache for !C_ENVIRONMENT_BOOTBLOCK ...................................................................... lib/fmap.c: Properly handle cache for !C_ENVIRONMENT_BOOTBLOCK On platforms without C_ENVIRONMENT_BOOTBLOCK the first stage accessing FMAP is romstage. As on these platforms only romstage is expected to call setup_preram_cache() no further handling is needed. Change-Id: I7d70585b0c076707e73e20c2ed3f11e4c9ffdf37 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/lib/fmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/36908/1 diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 4b4179c..f0fae55 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -78,7 +78,7 @@ } struct fmap *fmap = (struct fmap *)_fmap_cache; - if (!ENV_BOOTBLOCK) { + if (!ENV_BOOTBLOCK && CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { /* NOTE: This assumes that for all platforms running this code, the bootblock is the first stage and the bootblock will make at least one FMAP access (usually from finding CBFS). */ -- To view, visit https://review.coreboot.org/c/coreboot/+/36908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d70585b0c076707e73e20c2ed3f11e4c9ffdf37 Gerrit-Change-Number: 36908 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 19

Change in coreboot[master]: kill CAR_GLOBAL_MIGRATION leftovers
by Arthur Heymans (Code Review) 19 May '20

19 May '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37055 ) Change subject: kill CAR_GLOBAL_MIGRATION leftovers ...................................................................... kill CAR_GLOBAL_MIGRATION leftovers Change-Id: Ia3b2c10af63cd0cab42dc39f479cb69bc4df9124 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/console/printk.c M src/include/rules.h 3 files changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37055/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index b063cd1..6835d86 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -20,7 +20,6 @@ #define CBMEM_ID_AFTER_CAR 0xc4787a93 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_AMDMCT_MEMINFO 0x494D454E -#define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_CBTABLE 0x43425442 #define CBMEM_ID_CBTABLE_FWD 0x43425443 #define CBMEM_ID_CONSOLE 0x434f4e53 @@ -88,7 +87,6 @@ { CBMEM_ID_AGESA_RUNTIME, "AGESA RSVD " }, \ { CBMEM_ID_AFTER_CAR, "AFTER CAR " }, \ { CBMEM_ID_AMDMCT_MEMINFO, "AMDMEM INFO" }, \ - { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ { CBMEM_ID_CBTABLE, "COREBOOT " }, \ { CBMEM_ID_CBTABLE_FWD, "COREBOOTFWD" }, \ { CBMEM_ID_CONSOLE, "CONSOLE " }, \ diff --git a/src/console/printk.c b/src/console/printk.c index 4f9f547..dc3077d 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -27,8 +27,7 @@ DECLARE_SPIN_LOCK(console_lock) #endif -#define TRACK_CONSOLE_TIME (CONFIG(HAVE_MONOTONIC_TIMER) && \ - (ENV_RAMSTAGE || !CONFIG(CAR_GLOBAL_MIGRATION))) +#define TRACK_CONSOLE_TIME (CONFIG(HAVE_MONOTONIC_TIMER)) static struct mono_time mt_start, mt_stop; static long console_usecs; diff --git a/src/include/rules.h b/src/include/rules.h index 9e13ee6..fa60ede 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -258,7 +258,7 @@ /* No .data sections with execute-in-place from ROM. */ #define ENV_STAGE_HAS_DATA_SECTION !ENV_CACHE_AS_RAM /* No .bss sections for stage with CAR teardown. */ -#define ENV_STAGE_HAS_BSS_SECTION !(ENV_ROMSTAGE && CONFIG(CAR_GLOBAL_MIGRATION)) +#define ENV_STAGE_HAS_BSS_SECTION 1 #else /* Both .data and .bss, sometimes SRAM not DRAM. */ #define ENV_STAGE_HAS_DATA_SECTION 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/37055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia3b2c10af63cd0cab42dc39f479cb69bc4df9124 Gerrit-Change-Number: 37055 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: Add force memory retraining
by Jamie Chen (Code Review) 19 May '20

19 May '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39139 ) Change subject: drivers/intel/fsp2_0: Add force memory retraining ...................................................................... drivers/intel/fsp2_0: Add force memory retraining Add two weak functions: mainboard_prepare_dimm_info and is_the_same_memory_dimm. mainboard_preoare_dimm_info: for mainboard to provide its memory specific information. is_the_same_memory_dimm: identify the memory DIMMs are the same or not by compare spd cache and fspm_upd. It will trigger memory re-train if is_the_same_memory_dimm returns FALSE. BUG=b:146457985 BRANCH=None TEST=1. build puff and boot up OS 2. power off and swap DDR4 memory dimm 3. power up and check log of coreboot to confirm that device re-train the DDR4 memory. Change-Id: Id123191d478b0ec53b4c3fae5dd8b738487458fb Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/39139/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 60adb98..016a9d5 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -83,6 +83,11 @@ void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); +/* Provide specific DIMM information for recording in SPD cache. */ +void mainboard_prepare_dimm_info(FSPM_UPD *upd, void *data, size_t *data_sz); +/* Check if memory DIMMs are the same with previous time. */ +bool is_the_same_memory_dimm(FSPM_UPD *upd, const void *data, size_t *data_sz); + /* * # DOCUMENTATION: * diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 455dfa5..ea868ed 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -42,6 +42,20 @@ CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "for TPM MRC hash functionality, vboot must start in bootblock"); +static void save_memory_identify_info(FSPM_UPD *fspm_upd, uint32_t fsp_version) +{ + size_t spd_dimm_info_sz; + uint8_t spd_dimm_info[128]; + + spd_dimm_info_sz = sizeof(spd_dimm_info); + + mainboard_prepare_dimm_info(fspm_upd, spd_dimm_info, &spd_dimm_info_sz); + + if (mrc_cache_stash_data(MRC_SPD_DATA, fsp_version, spd_dimm_info, spd_dimm_info_sz) < 0) { + printk(BIOS_ERR, "Failed to stash SPD cache data\n"); + } +} + static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -265,6 +279,60 @@ return ver; } +__weak +bool is_the_same_memory_dimm(FSPM_UPD *upd, const void *data, size_t *data_sz) +{ + return TRUE; +} + +__weak +void mainboard_prepare_dimm_info(FSPM_UPD *upd, void *data, size_t *data_sz) +{ + data = NULL; + *data_sz = 0; +} + +static void check_memory_dimm_identify_info(FSPM_UPD *fspm_upd, uint32_t fsp_version) +{ + size_t spd_cache_sz; + const void *spd_cache; + struct region_device rdev; + + if (mrc_cache_get_current(MRC_SPD_DATA, fsp_version, &rdev) < 0) { + printk(BIOS_ERR, "Cannt read dimm info from SPD_CACHE\n"); + return; + } + + /* Assume boot device is memory mapped. */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + spd_cache = rdev_mmap_full(&rdev); + + if (spd_cache == NULL) + return; + + if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) && + !mrc_cache_verify_hash(spd_cache, region_device_sz(&rdev))) + return; + + /* SPD cache found */ + printk(BIOS_SPEW, "SPD cache found, size %zx\n", + region_device_sz(&rdev)); + + spd_cache = rdev_mmap_full(&rdev); + spd_cache_sz = region_device_sz(&rdev); + + printk(BIOS_ERR, "MRC_SPD_DATA at %p size=%ld\n", spd_cache, spd_cache_sz); + + // compare spd cache and spd info read from smbus + if (is_the_same_memory_dimm(fspm_upd, spd_cache, &spd_cache_sz)) + printk(BIOS_INFO, "jm: is the same dimm\n"); + else { + printk(BIOS_INFO, "jm: not the same dimm, set MRC cache to invalid\n"); + // invalid mrc cache + fspm_upd->FspmArchUpd.NvsBufferPtr = NULL; + } +} + static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, const struct memranges *memmap) { @@ -304,6 +372,9 @@ if (CONFIG(MMA)) setup_mma(&fspm_upd.FspmConfig); + if (CONFIG(ROMSTAGE_SPD_SMBUS) && !s3wake) + check_memory_dimm_identify_info(&fspm_upd, fsp_version); + post_code(POST_MEM_PREINIT_PREP_END); /* Call FspMemoryInit */ @@ -325,6 +396,8 @@ } do_fsp_post_memory_init(s3wake, fsp_version); + if(CONFIG(ROMSTAGE_SPD_SMBUS) && !s3wake) + save_memory_identify_info(&fspm_upd, fsp_version); /* * fsp_debug_after_memory_init() checks whether the end of the tolum -- To view, visit https://review.coreboot.org/c/coreboot/+/39139 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id123191d478b0ec53b4c3fae5dd8b738487458fb Gerrit-Change-Number: 39139 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff: enable retraining memory support
by Jamie Chen (Code Review) 19 May '20

19 May '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39140 ) Change subject: mb/google/puff: enable retraining memory support ...................................................................... mb/google/puff: enable retraining memory support Add chromeos-puff.fmd for Puff and insert a region for spd cache. Implement mainboard_prepare_dimm_info and is_the_same_memory_dimm. BUG=b:146457985 BRANCH=None TEST=1. build puff and boot up OS 2. power off and swap DDR4 memory dimm 3. power up and check log of coreboot to confirm that device re-train the DDR4 memory. Change-Id: I4eff8bc546c2728ff2de875e0e05da446f73c704 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/include/spd_bin.h M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/chromeos-puff.fmd M src/mainboard/google/hatch/romstage_spd_smbus.c 5 files changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/39140/1 diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index f144b14..cf6c723 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -40,6 +40,8 @@ #define LPDDR3_SPD_PART_LEN 18 #define DDR4_SPD_PART_OFF 329 #define DDR4_SPD_PART_LEN 20 +#define DDR4_SPD_SN_OFF 325 +#define DDR4_SPD_SN_LEN 4 #define LPDDR4_SPD_PART_OFF 329 #define LPDDR4_SPD_PART_LEN 20 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 783ec73..8cd4d8f 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -76,6 +76,7 @@ config FMDFILE string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-puff.fmd" if BOARD_GOOGLE_PUFF default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768 diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index 2427b12..6e973fa 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -49,6 +49,7 @@ select BOARD_ROMSIZE_KB_32768 select ROMSTAGE_SPD_SMBUS select SPD_READ_BY_WORD + select MRC_SETTINGS_SPD_DATA config BOARD_GOOGLE_HELIOS_DISKSWAP bool "-> Helios_Diskswap" diff --git a/src/mainboard/google/hatch/chromeos-puff.fmd b/src/mainboard/google/hatch/chromeos-puff.fmd new file mode 100644 index 0000000..30ff68f --- /dev/null +++ b/src/mainboard/google/hatch/chromeos-puff.fmd @@ -0,0 +1,48 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0x1c00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0x1000000 + RW_SECTION_A@0x1000000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x13e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x17c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x1F800 + RW_SPD_MRC_CACHE @0x2F800 0x800 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/hatch/romstage_spd_smbus.c b/src/mainboard/google/hatch/romstage_spd_smbus.c index 9073744..b76b450 100644 --- a/src/mainboard/google/hatch/romstage_spd_smbus.c +++ b/src/mainboard/google/hatch/romstage_spd_smbus.c @@ -14,6 +14,7 @@ */ #include <baseboard/variants.h> +#include <fsp/api.h> #include <soc/cnl_memcfg_init.h> #include <soc/romstage.h> #include <spd_bin.h> @@ -49,3 +50,59 @@ cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } + +struct dimm_info_str { + char part[DDR4_SPD_PART_LEN]; + uint8_t serial_no[DDR4_SPD_SN_LEN]; +}; + +void mainboard_prepare_dimm_info(FSPM_UPD *upd, void* data, size_t *data_sz) +{ + uint8_t *spd1_ptr, *spd2_ptr; + struct dimm_info_str *dimm_data = data; + + memset(dimm_data, 0, sizeof(struct dimm_info_str) * 2); + + spd1_ptr = (uint8_t*) upd->FspmConfig.MemorySpdPtr00; + spd2_ptr = (uint8_t*) upd->FspmConfig.MemorySpdPtr10; + + if (spd1_ptr != NULL) { + memcpy(&dimm_data[0].part, spd1_ptr + DDR4_SPD_PART_OFF, DDR4_SPD_PART_LEN); + memcpy(&dimm_data[0].serial_no, spd1_ptr + DDR4_SPD_SN_OFF, DDR4_SPD_SN_LEN); + } + + if (spd2_ptr != NULL) { + memcpy(&dimm_data[1].part, spd2_ptr + DDR4_SPD_PART_OFF, DDR4_SPD_PART_LEN); + memcpy(&dimm_data[1].serial_no, spd2_ptr + DDR4_SPD_SN_OFF, DDR4_SPD_SN_LEN); + } + + *data_sz = sizeof(struct dimm_info_str) * 2; +} + +bool is_the_same_memory_dimm(FSPM_UPD *upd, const void *data, size_t *data_sz) +{ + uint8_t *spd1_ptr, *spd2_ptr; + const struct dimm_info_str *dimm_data = data; + + spd1_ptr = (uint8_t*) upd->FspmConfig.MemorySpdPtr00; + spd2_ptr = (uint8_t*) upd->FspmConfig.MemorySpdPtr10; + + if (spd1_ptr == NULL) { + if (strlen(dimm_data[0].part) != 0) + return FALSE; + } else { + if ((memcmp(&dimm_data[0].part, spd1_ptr + DDR4_SPD_PART_OFF, DDR4_SPD_PART_LEN) != 0) && + (memcmp(&dimm_data[0].serial_no, spd1_ptr + DDR4_SPD_SN_OFF, DDR4_SPD_SN_LEN) != 0)) + return FALSE; + } + + if (spd2_ptr == NULL) { + if (strlen(dimm_data[1].part) != 0) + return FALSE; + } else { + if ((memcmp(&dimm_data[1].part, spd2_ptr + DDR4_SPD_PART_OFF, DDR4_SPD_PART_LEN) != 0) && + (memcmp(&dimm_data[1].serial_no, spd2_ptr + DDR4_SPD_SN_OFF, DDR4_SPD_SN_LEN) != 0)) + return FALSE; + } + return TRUE; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/39140 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eff8bc546c2728ff2de875e0e05da446f73c704 Gerrit-Change-Number: 39140 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: drivers/mrc_cache: Add SPD cache to MRC region
by Jamie Chen (Code Review) 19 May '20

19 May '20

Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39138 ) Change subject: drivers/mrc_cache: Add SPD cache to MRC region ...................................................................... drivers/mrc_cache: Add SPD cache to MRC region Add a new region for store memory SPD specific data BUG=b:146457985 BRANCH=None TEST=Build puff pass. Change-Id: If5d315cc9021161472567c18e6f36aed7f3e4e96 Signed-off-by: Jamie Chen <jamie.chen(a)intel.com> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/mrc_cache/Kconfig M src/drivers/mrc_cache/mrc_cache.c M src/include/elog.h M src/include/mrc_cache.h 5 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39138/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 93d1464..5d31573 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -41,6 +41,7 @@ #define CBMEM_ID_MPTABLE 0x534d5054 #define CBMEM_ID_MRCDATA 0x4d524344 #define CBMEM_ID_VAR_MRCDATA 0x4d524345 +#define CBMEM_ID_SPD_MRCDATA 0x4d524346 #define CBMEM_ID_MTC 0xcb31d31c #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_PIRQ 0x49525154 @@ -108,6 +109,7 @@ { CBMEM_ID_MPTABLE, "SMP TABLE " }, \ { CBMEM_ID_MRCDATA, "MRC DATA " }, \ { CBMEM_ID_VAR_MRCDATA, "VARMRC DATA" }, \ + { CBMEM_ID_SPD_MRCDATA, "SPDMRC_DATA" }, \ { CBMEM_ID_MTC, "MTC " }, \ { CBMEM_ID_PIRQ, "IRQ TABLE " }, \ { CBMEM_ID_POWER_STATE, "POWER STATE" }, \ diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 543f310..ad95680 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -25,6 +25,10 @@ bool default n +config MRC_SETTINGS_SPD_DATA + bool + default n + config MRC_WRITE_NV_LATE bool default n diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index d4a4aab..ce7379c 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -28,6 +28,7 @@ #define DEFAULT_MRC_CACHE "RW_MRC_CACHE" #define VARIABLE_MRC_CACHE "RW_VAR_MRC_CACHE" +#define SPD_MRC_CACHE "RW_SPD_MRC_CACHE" #define RECOVERY_MRC_CACHE "RECOVERY_MRC_CACHE" #define UNIFIED_MRC_CACHE "UNIFIED_MRC_CACHE" @@ -86,10 +87,19 @@ .flags = NORMAL_FLAG | RECOVERY_FLAG, }; +static const struct cache_region spd_data = { + .name = SPD_MRC_CACHE, + .cbmem_id = CBMEM_ID_SPD_MRCDATA, + .type = MRC_SPD_DATA, + .elog_slot = ELOG_MEM_CACHE_UPDATE_SLOT_SPD, + .flags = NORMAL_FLAG | RECOVERY_FLAG, +}; + /* Order matters here for priority in matching. */ static const struct cache_region *cache_regions[] = { &recovery_training, &normal_training, + &spd_data, &variable_data, }; @@ -549,6 +559,9 @@ if (CONFIG(MRC_SETTINGS_VARIABLE_DATA)) update_mrc_cache_by_type(MRC_VARIABLE_DATA); + if (CONFIG(MRC_SETTINGS_SPD_DATA)) + update_mrc_cache_by_type(MRC_SPD_DATA); + if (CONFIG(MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN)) invalidate_normal_cache(); diff --git a/src/include/elog.h b/src/include/elog.h index 8d1b3ba..72e000a 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -173,6 +173,7 @@ #define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 #define ELOG_MEM_CACHE_UPDATE_SLOT_RECOVERY 1 #define ELOG_MEM_CACHE_UPDATE_SLOT_VARIABLE 2 +#define ELOG_MEM_CACHE_UPDATE_SLOT_SPD 3 #define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 #define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 struct elog_event_mem_cache_update { diff --git a/src/include/mrc_cache.h b/src/include/mrc_cache.h index 498ecbf..534ea10 100644 --- a/src/include/mrc_cache.h +++ b/src/include/mrc_cache.h @@ -23,6 +23,7 @@ enum { MRC_TRAINING_DATA, MRC_VARIABLE_DATA, + MRC_SPD_DATA, }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/39138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5d315cc9021161472567c18e6f36aed7f3e4e96 Gerrit-Change-Number: 39138 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Chen <jamie.chen(a)intel.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: sc7180: GPIO: Add I2S configuration for sc7180
by mturney mturney (Code Review) 15 May '20

15 May '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38593 ) Change subject: sc7180: GPIO: Add I2S configuration for sc7180 ...................................................................... sc7180: GPIO: Add I2S configuration for sc7180 Configuring GPIO Pins as I2S mode for Audio speaker. Change-Id: I681aa6d0d57671b0fd9b7bc88de6f2cc202a7af0 Signed-off-by: vsujithk <vsujithk(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/Makefile.inc M src/soc/qualcomm/sc7180/bootblock.c A src/soc/qualcomm/sc7180/include/soc/qi2s.h A src/soc/qualcomm/sc7180/qi2s.c 4 files changed, 80 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/38593/1 diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index ba1f675..6d6222b 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += qupv3_fw_config.c bootblock-y += qupv3_config.c bootblock-y += qcom_qup_se.c +bootblock-y += qi2s.c ################################################################################ verstage-y += timer.c @@ -27,7 +28,7 @@ verstage-y += qcom_qup_se.c verstage-y += qupv3_config.c verstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c - +verstage-y += qi2s.c ################################################################################ romstage-y += cbmem.c romstage-y += timer.c @@ -45,7 +46,7 @@ romstage-y += qcom_qup_se.c romstage-y += qupv3_config.c romstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c - +romstage-y += qi2s.c ################################################################################ ramstage-y += soc.c ramstage-y += timer.c @@ -61,7 +62,7 @@ ramstage-y += qupv3_config.c ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += qupv3_uart.c - +romstage-y += qi2s.c ################################################################################ CPPFLAGS_common += -Isrc/soc/qualcomm/sc7180/include diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c index b247d2d..83b22ba 100644 --- a/src/soc/qualcomm/sc7180/bootblock.c +++ b/src/soc/qualcomm/sc7180/bootblock.c @@ -18,6 +18,7 @@ #include <soc/mmu.h> #include <soc/qspi.h> #include <soc/qupv3_fw_config.h> +#include <soc/qi2s.h> void bootblock_soc_init(void) { @@ -25,4 +26,5 @@ clock_init(); quadspi_init(25 * MHz); qupv3_fw_init(); + qi2s_init(); } diff --git a/src/soc/qualcomm/sc7180/include/soc/qi2s.h b/src/soc/qualcomm/sc7180/include/soc/qi2s.h new file mode 100644 index 0000000..ee02094a --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/qi2s.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019-2020 Qualcomm Technologies. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_QUALCOMM_SC7180_QI2S_H__ +#define __SOC_QUALCOMM_SC7180_QI2S_H__ + +void qi2s_init(void); + + +#endif /* __SOC_QUALCOMM_SC7180_QI2S_H__ */ diff --git a/src/soc/qualcomm/sc7180/qi2s.c b/src/soc/qualcomm/sc7180/qi2s.c new file mode 100644 index 0000000..9661e55 --- /dev/null +++ b/src/soc/qualcomm/sc7180/qi2s.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019-2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/clock.h> +#include <symbols.h> +#include <assert.h> +#include <gpio.h> +#include <string.h> +#include <soc/qi2s.h> + + +static void configure_gpios(void) +{ + + gpio_output(GPIO(49), 1); + gpio_output(GPIO(50), 1); + gpio_output(GPIO(51), 1); + gpio_output(GPIO(23), 1); + + gpio_configure(GPIO(23), 0, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + gpio_configure(GPIO(49), 1, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + gpio_configure(GPIO(50), 1, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + gpio_configure(GPIO(51), 1, GPIO_PULL_UP, + GPIO_8MA, GPIO_OUTPUT); + +} + + +void qi2s_init() +{ + configure_gpios(); +} + -- To view, visit https://review.coreboot.org/c/coreboot/+/38593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I681aa6d0d57671b0fd9b7bc88de6f2cc202a7af0 Gerrit-Change-Number: 38593 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

8 27

Change in coreboot[master]: trogdor: Add support for rev1
by Julius Werner (Code Review) 12 May '20

12 May '20

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38773 ) Change subject: trogdor: Add support for rev1 ...................................................................... trogdor: Add support for rev1 This patch implements the pin changes needed for Trogdor rev1. Unfortunately, coreboot has to get the EC and TPM SPI busses compiled into Kconfig, so we cannot really build a single image that runs on both revisions. Introducing a Kconfig to handle this instead. Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/trogdor/Kconfig M src/mainboard/google/trogdor/board.h M src/mainboard/google/trogdor/bootblock.c M src/mainboard/google/trogdor/chromeos.c 4 files changed, 15 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/38773/1 diff --git a/src/mainboard/google/trogdor/Kconfig b/src/mainboard/google/trogdor/Kconfig index 8d5bced..cb9f361 100644 --- a/src/mainboard/google/trogdor/Kconfig +++ b/src/mainboard/google/trogdor/Kconfig @@ -4,6 +4,9 @@ if BOARD_GOOGLE_TROGDOR_COMMON +config TROGDOR_REV0 + def_bool y + config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 @@ -32,11 +35,13 @@ config DRIVER_TPM_SPI_BUS hex - default 0x6 + default 0x6 if TROGDOR_REV0 + default 0x0 config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0x0 + default 0x0 if TROGDOR_REV0 + default 0x6 ########################################################## #### Update below when adding a new derivative board. #### diff --git a/src/mainboard/google/trogdor/board.h b/src/mainboard/google/trogdor/board.h index e43f7cc..9c727b3 100644 --- a/src/mainboard/google/trogdor/board.h +++ b/src/mainboard/google/trogdor/board.h @@ -16,6 +16,7 @@ #ifndef _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ #define _COREBOOT_SRC_MAINBOARD_GOOGLE_TROGDOR_BOARD_H_ +#include <boardid.h> #include <gpio.h> #include <soc/gpio.h> @@ -23,7 +24,8 @@ #define GPIO_AP_EC_INT GPIO(94) #define GPIO_AP_SUSPEND GPIO(20) #define GPIO_WP_STATE GPIO(42) -#define GPIO_H1_AP_INT GPIO(21) +#define GPIO_H1_AP_INT (board_id() < 1 ? GPIO(21) : GPIO(42)) +#define GPIO_SD_CD_L GPIO(69) enum gpio_pull { GPIO_PULLNONE = 0, diff --git a/src/mainboard/google/trogdor/bootblock.c b/src/mainboard/google/trogdor/bootblock.c index e9a8ffe..2f83c6c 100644 --- a/src/mainboard/google/trogdor/bootblock.c +++ b/src/mainboard/google/trogdor/bootblock.c @@ -15,14 +15,12 @@ #include <bootblock_common.h> #include "board.h" -#include <soc/qcom_qup_se.h> #include <soc/qupv3_spi.h> #include <soc/gpio.h> void bootblock_mainboard_init(void) { setup_chromeos_gpios(); - qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */ - qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */ - gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULLUP); + qup_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1010 * KHz); + qup_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 1010 * KHz); } diff --git a/src/mainboard/google/trogdor/chromeos.c b/src/mainboard/google/trogdor/chromeos.c index 4a78c85..94c62ff 100644 --- a/src/mainboard/google/trogdor/chromeos.c +++ b/src/mainboard/google/trogdor/chromeos.c @@ -29,7 +29,7 @@ gpio_input_pullup(GPIO_AP_EC_INT); gpio_output(GPIO_AP_SUSPEND, 1); gpio_input(GPIO_WP_STATE); - gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input_irq(GPIO_H1_AP_INT, IRQ_TYPE_RISING_EDGE, GPIO_PULL_UP); } void fill_lb_gpios(struct lb_gpios *gpios) @@ -43,6 +43,8 @@ "write protect"}, {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, + {GPIO_SD_CD_L.addr, ACTIVE_LOW, gpio_get(GPIO_SD_CD_L), + "SD card detect"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); @@ -52,4 +54,3 @@ { return gpio_irq_status(GPIO_H1_AP_INT); } - -- To view, visit https://review.coreboot.org/c/coreboot/+/38773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8 Gerrit-Change-Number: 38773 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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