coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: [WIP] mb/intel/cannonlake_rvp,coffeelake_rvp: Add LPC_TPM
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35103 ) Change subject: [WIP] mb/intel/cannonlake_rvp,coffeelake_rvp: Add LPC_TPM ...................................................................... [WIP] mb/intel/cannonlake_rvp,coffeelake_rvp: Add LPC_TPM Board devicetrees requests for drivers7pc80/tpm but that was not included for the build. Change-Id: Ia959ae9072e3fc709b779b1fc778eb82e10c2ee3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/cannonlake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35103/1 diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig index d86e485..6d686c3 100644 --- a/src/mainboard/intel/cannonlake_rvp/Kconfig +++ b/src/mainboard/intel/cannonlake_rvp/Kconfig @@ -13,6 +13,7 @@ select SOC_INTEL_CANNONLAKE select MAINBOARD_USES_IFD_EC_REGION select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 13e55b3..8bd2881 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -16,6 +16,7 @@ select SOC_INTEL_COMMON_BLOCK_HDA if BOARD_INTEL_WHISKEYLAKE_RVP || BOARD_INTEL_COMETLAKE_RVP select MAINBOARD_USES_IFD_EC_REGION select MAINBOARD_USES_IFD_GBE_REGION if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVP8 + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/35103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia959ae9072e3fc709b779b1fc778eb82e10c2ee3 Gerrit-Change-Number: 35103 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

8 21

Change in coreboot[master]: soc/amd/picasso: Cache ramstage load
by Marshall Dawson (Code Review) 08 Jun '20

08 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37492 ) Change subject: soc/amd/picasso: Cache ramstage load ...................................................................... soc/amd/picasso: Cache ramstage load Set a variable MTRR to WB for the region where ramstage will be loaded. Only a single one is required now that SMM memory is in cbmem. Change-Id: I0a31802052ac7b20871f41c80d0416ee09f8f87c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/romstage.c 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/37492/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index 9af4c0c..338e871 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -18,9 +18,6 @@ #include <device/device.h> -#define SOC_EARLY_VMTRR_FLASH 1 -#define SOC_EARLY_VMTRR_TEMPRAM 2 - #define CSTATE_BASE_REG 0xc0010073 void picasso_init_cpus(struct device *dev); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 22b717d..f2e3375 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -16,6 +16,7 @@ #include <arch/acpi.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <arch/exception.h> #include <delay.h> @@ -34,6 +35,25 @@ /* By default, don't do anything */ } +static void set_mtrrs_for_ramstage(void) +{ + uintptr_t mem_top; + int mtrr; + + mem_top = (uintptr_t)cbmem_top(); + + /* Cache anticipated ramstage location through the top of cbmem. + * Unlike some other implementations, TSEG is in cbmem so it will + * be cached as well. + */ + mtrr = get_free_var_mtrr(); + if (mtrr < 0) { + printk(BIOS_WARNING, "Warning: Unable to make ramstage cacheable\n"); + return; + } + set_var_mtrr(mtrr, mem_top - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); +} + static void soc_romstage(uint32_t bist) { uintptr_t top_of_mem; @@ -68,6 +88,8 @@ printk(BIOS_ERR, "Failed to set romstage handoff data\n"); post_code(0x45); + set_mtrrs_for_ramstage(); + post_code(0x46); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a31802052ac7b20871f41c80d0416ee09f8f87c Gerrit-Change-Number: 37492 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/amd/picasso: Cache romstage in RAM
by Marshall Dawson (Code Review) 08 Jun '20

08 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38692 ) Change subject: soc/amd/picasso: Cache romstage in RAM ...................................................................... soc/amd/picasso: Cache romstage in RAM Picasso's romstage is non-XIP and therefore is not automatically cached by the WP type applied to the flash storage. Determine its location in RAM and type it with an MTRR. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I431c63553c6eabafc4f3512a2484f350cd07003b --- M src/soc/amd/picasso/romstage.c 1 file changed, 19 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/38692/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 8b8d329..4655d95 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <program_loading.h> #include <romstage_handoff.h> +#include <symbols.h> #include <elog.h> #include <soc/romstage.h> @@ -29,34 +30,47 @@ /* By default, don't do anything */ } +static void cache_romstage(void) +{ + int mtrr; + + mtrr = get_free_var_mtrr(); + if (mtrr < 0) + return; + set_var_mtrr(mtrr, (unsigned int)_romstage, _eromstage - _romstage, MTRR_TYPE_WRBACK); +} + asmlinkage void car_stage_entry(void) { uintptr_t top_of_mem; int s3_resume; post_code(0x40); - console_init(); + cache_romstage(); post_code(0x41); + console_init(); + + post_code(0x42); s3_resume = acpi_s3_resume_allowed() && acpi_is_wakeup_s3(); mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume); - post_code(0x42); + post_code(0x43); u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); - post_code(0x43); + post_code(0x44); top_of_mem = ALIGN_DOWN(rdmsr(TOP_MEM).lo, 8 * MiB); backup_top_of_low_cacheable(top_of_mem); - post_code(0x44); + post_code(0x45); if (cbmem_recovery(s3_resume)) printk(BIOS_CRIT, "Failed to recover cbmem\n"); if (romstage_handoff_init(s3_resume)) printk(BIOS_ERR, "Failed to set romstage handoff data\n"); - post_code(0x45); + post_code(0x46); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I431c63553c6eabafc4f3512a2484f350cd07003b Gerrit-Change-Number: 38692 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: [WIP] drivers/pc80/rtc: Drop ARCH_X86 guard in header
by Kyösti Mälkki (Code Review) 07 Jun '20

07 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38197 ) Change subject: [WIP] drivers/pc80/rtc: Drop ARCH_X86 guard in header ...................................................................... [WIP] drivers/pc80/rtc: Drop ARCH_X86 guard in header Change-Id: I03c25ad5d9864406e1a021e39a5736ac72c8825a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/elog/boot_count.c M src/drivers/elog/elog.c M src/include/pc80/mc146818rtc.h M src/lib/bootblock.c 4 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/38197/1 diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c index a6efb01..6823a93 100644 --- a/src/drivers/elog/boot_count.c +++ b/src/drivers/elog/boot_count.c @@ -13,7 +13,6 @@ #include <console/console.h> #include <ip_checksum.h> -#include <pc80/mc146818rtc.h> #include <stddef.h> #include <stdint.h> #include <elog.h> diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index 11cbfba..7f6c75b 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -17,9 +17,6 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#if CONFIG(ARCH_X86) -#include <pc80/mc146818rtc.h> -#endif #include <bcd.h> #include <boot_device.h> #include <commonlib/region.h> diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 8cc2ed4..f6359f1 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -1,14 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #ifndef PC80_MC146818RTC_H #define PC80_MC146818RTC_H -#if CONFIG(ARCH_X86) - #include <arch/io.h> #include <types.h> -#ifndef RTC_BASE_PORT #define RTC_BASE_PORT 0x70 -#endif #define RTC_PORT(x) (RTC_BASE_PORT + (x)) @@ -181,8 +190,4 @@ int cmos_checksum_valid(int range_start, int range_end, int cks_loc); void cmos_set_checksum(int range_start, int range_end, int cks_loc); -#endif /* CONFIG_ARCH_X86 */ - -void cmos_post_init(void); - #endif /* PC80_MC146818RTC_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 386f4e3..166b3fe 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <delay.h> #include <option.h> -#include <pc80/mc146818rtc.h> #include <program_loading.h> #include <symbols.h> #include <timestamp.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/38197 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I03c25ad5d9864406e1a021e39a5736ac72c8825a Gerrit-Change-Number: 38197 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: Maintainers: Remove Martin as maintainer
by Martin Roth (Code Review) 06 Jun '20

06 Jun '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38584 ) Change subject: Maintainers: Remove Martin as maintainer ...................................................................... Maintainers: Remove Martin as maintainer Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: Ibb0446958e27c9c4cc6b8408b162e7ada48e291a --- M MAINTAINERS 1 file changed, 3 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/38584/1 diff --git a/MAINTAINERS b/MAINTAINERS index 6c565f7..ab78b9d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -358,7 +358,6 @@ ABUILD M: Patrick Georgi <patrick(a)georgi-clan.de> -M: Martin Roth <gaumless(a)gmail.com> S: Supported F: util/abuild/ @@ -424,7 +423,6 @@ LINT SCRIPTS M: Patrick Georgi <patrick(a)georgi-clan.de> -M: Martin Roth <gaumless(a)gmail.com> S: Supported F: util/lint/ @@ -448,7 +446,6 @@ BUILD SYSTEM M: Patrick Georgi <patrick(a)georgi-clan.de> -M: Martin Roth <gaumless(a)gmail.com> S: Supported F: Makefile F: *.inc @@ -509,7 +506,6 @@ EXTERNAL PAYLOADS INTEGRATION M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> -M: Martin Roth <gaumless(a)gmail.com> F: payloads/external LINUXBOOT PAYLOAD INTEGRATION @@ -530,7 +526,6 @@ F: src/security/tpm DOCKER -M: Martin Roth <gaumless(a)gmail.com> S: Supported F: util/docker/ @@ -586,7 +581,7 @@ # Backups: # Website -# Owners: Martin, Philipp +# Owners: Philipp # Backups: Patrick, Stefan # Documentation Website @@ -597,7 +592,6 @@ M: Stefan Reinauer <stefan.reinauer(a)coreboot.org> M: Patrick Georgi <patrick(a)coreboot.org> M: Ronald Minnich <rminnich(a)coreboot.org> -M: Martin Roth <martin(a)coreboot.org> S: Maintained F: Documentation/community/code_of_conduct.md @@ -607,20 +601,17 @@ # Gerrit # Owners: Stefan, Patrick -# Backups: Martin # Jenkins -# Owners: Patrick, Martin +# Owners: Patrick # Backups: # Bug Tracker # Owners: Lynxis, -# Backups: Martin, # Mailing List # Owners: Stefan, Patrick -# Backups: Martin, + # Software Freedom Conservancy -# Main contact: Martin # “Official” contact: Stefan -- To view, visit https://review.coreboot.org/c/coreboot/+/38584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb0446958e27c9c4cc6b8408b162e7ada48e291a Gerrit-Change-Number: 38584 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: [WIP] asrock/e350m1: Switch away from ROMCC_BOOTBLOCK
by Denis 'GNUtoo' Carikli (Code Review) 30 May '20

30 May '20

Denis 'GNUtoo' Carikli has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37703 ) Change subject: [WIP] asrock/e350m1: Switch away from ROMCC_BOOTBLOCK ...................................................................... [WIP] asrock/e350m1: Switch away from ROMCC_BOOTBLOCK Change-Id: Ie14db10b6a72e19ac67254ca8f95bcf6ac8af8d3 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> --- M src/mainboard/asrock/e350m1/Kconfig M src/mainboard/asrock/e350m1/Makefile.inc R src/mainboard/asrock/e350m1/bootblock.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/37703/1 diff --git a/src/mainboard/asrock/e350m1/Kconfig b/src/mainboard/asrock/e350m1/Kconfig index 86eaac8..3bbc2a5 100644 --- a/src/mainboard/asrock/e350m1/Kconfig +++ b/src/mainboard/asrock/e350m1/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/asrock/e350m1/Makefile.inc b/src/mainboard/asrock/e350m1/Makefile.inc index 440744c..ffea060 100644 --- a/src/mainboard/asrock/e350m1/Makefile.inc +++ b/src/mainboard/asrock/e350m1/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/bootblock.c similarity index 89% rename from src/mainboard/asrock/e350m1/romstage.c rename to src/mainboard/asrock/e350m1/bootblock.c index 27a1fac..bdc8c6c 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/bootblock.c @@ -13,15 +13,14 @@ * GNU General Public License for more details. */ -#include <northbridge/amd/agesa/state_machine.h> +#include <bootblock_common.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> #include <sb_cimx.h> #define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) - -void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { sb_Poweron_Init(); nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -- To view, visit https://review.coreboot.org/c/coreboot/+/37703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie14db10b6a72e19ac67254ca8f95bcf6ac8af8d3 Gerrit-Change-Number: 37703 Gerrit-PatchSet: 1 Gerrit-Owner: Denis 'GNUtoo' Carikli <GNUtoo(a)cyberdimension.org> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: arch/x86: Remove more romcc leftovers
by Kyösti Mälkki (Code Review) 28 May '20

28 May '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37955 ) Change subject: arch/x86: Remove more romcc leftovers ...................................................................... arch/x86: Remove more romcc leftovers The sections .rom.* were for romcc and no longer used. Some romcc comments were left behind when guards were removed. Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock_crt0.S M src/arch/x86/include/arch/cpu.h D src/arch/x86/prologue.inc M src/cpu/intel/fit/fit.S M src/include/stdint.h M src/lib/program.ld 6 files changed, 5 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/37955/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..2227c7f 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -21,11 +21,12 @@ #include <cpu/x86/cr.h> +.section .text + /* * Include the old code for reset vector and protected mode entry. That code has * withstood the test of time. */ -#include <arch/x86/prologue.inc> #include <cpu/x86/16bit/entry16.inc> #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index c8cf8c7..59eb9ad 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -261,7 +261,6 @@ return ci; } -/* romcc is segfaulting in some cases. */ struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ @@ -281,7 +280,6 @@ } -/* romcc does not understand regparm. */ #define asmlinkage __attribute__((regparm(0))) /* diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc deleted file mode 100644 index 4036ff9..0000000 --- a/src/arch/x86/prologue.inc +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/post_code.h> - -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits diff --git a/src/cpu/intel/fit/fit.S b/src/cpu/intel/fit/fit.S index aa715eb..bfeffaa 100644 --- a/src/cpu/intel/fit/fit.S +++ b/src/cpu/intel/fit/fit.S @@ -19,7 +19,7 @@ .long 0 .previous -.section ".rom.data", "a", @progbits +.section .text .align 16 .global fit_table .global fit_table_end diff --git a/src/include/stdint.h b/src/include/stdint.h index b534add..9e94513 100644 --- a/src/include/stdint.h +++ b/src/include/stdint.h @@ -14,9 +14,8 @@ #ifndef STDINT_H #define STDINT_H -/* romcc does not support long long, _Static_assert, or _Bool, so we must ifdef that code out. - Also, GCC can provide its own implementation of stdint.h, so in theory we could use that - instead of this custom file once romcc is no more. */ +/* GCC can provide its own implementation of stdint.h, so in theory we could use that + instead of this custom file. */ /* Fixed width integer types */ typedef signed char int8_t; diff --git a/src/lib/program.ld b/src/lib/program.ld index a9d4e48..3802278 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -26,12 +26,6 @@ .text . : { _program = .; _text = .; - /* - * The .rom.* sections are to acommodate x86 romstage. romcc as well - * as the assembly files put their text and data in these sections. - */ - *(.rom.text); - *(.rom.data); *(.text._start); *(.text.stage_entry); #if (ENV_DECOMPRESSOR || ENV_BOOTBLOCK && \ -- To view, visit https://review.coreboot.org/c/coreboot/+/37955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I060ad7af2f03c67946f9796e625c072b887280c1 Gerrit-Change-Number: 37955 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

9 25

Change in coreboot[master]: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT
by Patrick Rudolph (Code Review) 28 May '20

28 May '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34453 ) Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ...................................................................... sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT Both fields are ignored if WBINVD is set, which is true for all processors since i486. Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 2 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34453/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8794602..e656a37 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -766,8 +766,9 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; fadt->duty_offset = 1; if (chip->p_cnt_throttling_supported) { fadt->duty_width = 3; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fa1ca92..c829707 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -678,8 +678,9 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; fadt->duty_offset = 1; if (chip->p_cnt_throttling_supported) { fadt->duty_width = 3; -- To view, visit https://review.coreboot.org/c/coreboot/+/34453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Gerrit-Change-Number: 34453 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: vboot: Turn vboot_logic_executed() into a static inline
by Julius Werner (Code Review) 27 May '20

27 May '20

Hello Aaron Durbin, Frans Hendriks, Philipp Deppenwiese, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32716 to review the following change. Change subject: vboot: Turn vboot_logic_executed() into a static inline ...................................................................... vboot: Turn vboot_logic_executed() into a static inline This patch moves vboot_logic_executed() (and its dependencies) into a header and turns it into a static inline function. The function is used to guard larger amounts of code in several places, so this should allow us to safe some more space through compile-time elimination (and also makes it easier to avoid undefined reference issues in some cases). Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/security/vboot/misc.h M src/security/vboot/vboot_loader.c 2 files changed, 58 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32716/1 diff --git a/src/security/vboot/misc.h b/src/security/vboot/misc.h index b4fae19..2a0523d 100644 --- a/src/security/vboot/misc.h +++ b/src/security/vboot/misc.h @@ -16,6 +16,8 @@ #ifndef __VBOOT_MISC_H__ #define __VBOOT_MISC_H__ +#include <assert.h> +#include <arch/early_variables.h> #include <security/vboot/vboot_common.h> struct vb2_context; @@ -66,13 +68,63 @@ void vboot_fill_handoff(void); /* - * Source: security/vboot/vboot_loader.c - */ -int vboot_logic_executed(void); - -/* * Source: security/vboot/bootmode.c */ void vboot_save_recovery_reason_vbnv(void); +/* + * The stage loading code is compiled and entered from multiple stages. The + * helper functions below attempt to provide more clarity on when certain + * code should be called. They are implemented inline for better compile-time + * code elimination. + */ + +static inline int verification_should_run(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_VERSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) + return ENV_ROMSTAGE; + else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) + return ENV_BOOTBLOCK; + else + dead_code(); +} + +static inline int verstage_should_load(void) +{ + if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) + return ENV_BOOTBLOCK; + else + return 0; +} + +/* Only for use by functions in this header, do not access directly! */ +extern int vboot_executed; + +static inline int vboot_logic_executed(void) +{ + /* If we are in the stage that runs verification, or in the stage that + both loads the verstage and is returned to from it afterwards, we + need to check a global to see if verfication has run. */ + if (verification_should_run() || + (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) + return car_get_var(vboot_executed); + + if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { + /* All other stages are "after the bootblock" */ + return !ENV_BOOTBLOCK; + } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { + /* Post-RAM stages are "after the romstage" */ +#ifdef __PRE_RAM__ + return 0; +#else + return 1; +#endif + } else { + dead_code(); + } +} + + #endif /* __VBOOT_MISC_H__ */ diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index 3bbb3da..1350307 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -36,55 +36,7 @@ CONFIG(VBOOT_SEPARATE_VERSTAGE), "return from verstage only makes sense for separate verstages"); -/* The stage loading code is compiled and entered from multiple stages. The - * helper functions below attempt to provide more clarity on when certain - * code should be called. */ - -static int verification_should_run(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_VERSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) - return ENV_ROMSTAGE; - else if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - return ENV_BOOTBLOCK; - else - die("impossible!"); -} - -static int verstage_should_load(void) -{ - if (CONFIG(VBOOT_SEPARATE_VERSTAGE)) - return ENV_BOOTBLOCK; - else - return 0; -} - -static int vboot_executed CAR_GLOBAL; - -int vboot_logic_executed(void) -{ - /* If we are in the stage that runs verification, or in the stage that - both loads the verstage and is returned to from it afterwards, we - need to check a global to see if verfication has run. */ - if (verification_should_run() || - (verstage_should_load() && CONFIG(VBOOT_RETURN_FROM_VERSTAGE))) - return car_get_var(vboot_executed); - - if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) { - /* All other stages are "after the bootblock" */ - return !ENV_BOOTBLOCK; - } else if (CONFIG(VBOOT_STARTS_IN_ROMSTAGE)) { - /* Post-RAM stages are "after the romstage" */ -#ifdef __PRE_RAM__ - return 0; -#else - return 1; -#endif - } else { - die("impossible!"); - } -} +int vboot_executed CAR_GLOBAL; static void vboot_prepare(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Gerrit-Change-Number: 32716 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: mb/biostar/a68n_5200: Remove unused 'usb_oc.asl'
by HAOUAS Elyes (Code Review) 26 May '20

26 May '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39077 ) Change subject: mb/biostar/a68n_5200: Remove unused 'usb_oc.asl' ...................................................................... mb/biostar/a68n_5200: Remove unused 'usb_oc.asl' Also remove old reference in comment to Olivehill. Change-Id: Id4711cd1b7fdf49207d5e7c3abd4e077a921ee98 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl M src/mainboard/biostar/a68n_5200/dsdt.asl 2 files changed, 0 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/39077/1 diff --git a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl b/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl deleted file mode 100644 index 513d66d..0000000 --- a/src/mainboard/biostar/a68n_5200/acpi/usb_oc.asl +++ /dev/null @@ -1,129 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* simple name description */ -/* -#include <arch/acpi.h> -DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 - ) - { - #include "usb.asl" - } -*/ - -/* USB overcurrent mapping pins. */ -Name(UOM0, 0) -Name(UOM1, 2) -Name(UOM2, 0) -Name(UOM3, 7) -Name(UOM4, 2) -Name(UOM5, 2) -Name(UOM6, 6) -Name(UOM7, 2) -Name(UOM8, 6) -Name(UOM9, 6) - -/* USB Overcurrent GPEs */ - -#if 0 /* TODO: Update for Olivehill */ -Method(UCOC, 0) { - Sleep(20) - Store(0x13,CMTI) - Store(0,GPSL) -} - -/* USB Port 0 overcurrent uses Gpm 0 */ -If(LLessEqual(UOM0,9)) { - Scope (\_GPE) { - Method (_L13) { - } - } -} - -/* USB Port 1 overcurrent uses Gpm 1 */ -If (LLessEqual(UOM1,9)) { - Scope (\_GPE) { - Method (_L14) { - } - } -} - -/* USB Port 2 overcurrent uses Gpm 2 */ -If (LLessEqual(UOM2,9)) { - Scope (\_GPE) { - Method (_L15) { - } - } -} - -/* USB Port 3 overcurrent uses Gpm 3 */ -If (LLessEqual(UOM3,9)) { - Scope (\_GPE) { - Method (_L16) { - } - } -} - -/* USB Port 4 overcurrent uses Gpm 4 */ -If (LLessEqual(UOM4,9)) { - Scope (\_GPE) { - Method (_L19) { - } - } -} - -/* USB Port 5 overcurrent uses Gpm 5 */ -If (LLessEqual(UOM5,9)) { - Scope (\_GPE) { - Method (_L1A) { - } - } -} - -/* USB Port 6 overcurrent uses Gpm 6 */ -If (LLessEqual(UOM6,9)) { - Scope (\_GPE) { - /* Method (_L1C) { */ - Method (_L06) { - } - } -} - -/* USB Port 7 overcurrent uses Gpm 7 */ -If (LLessEqual(UOM7,9)) { - Scope (\_GPE) { - /* Method (_L1D) { */ - Method (_L07) { - } - } -} - -/* USB Port 8 overcurrent uses Gpm 8 */ -If (LLessEqual(UOM8,9)) { - Scope (\_GPE) { - Method (_L17) { - } - } -} - -/* USB Port 9 overcurrent uses Gpm 9 */ -If (LLessEqual(UOM9,9)) { - Scope (\_GPE) { - Method (_L0E) { - } - } -} -#endif diff --git a/src/mainboard/biostar/a68n_5200/dsdt.asl b/src/mainboard/biostar/a68n_5200/dsdt.asl index c4fc934..06a2dee 100644 --- a/src/mainboard/biostar/a68n_5200/dsdt.asl +++ b/src/mainboard/biostar/a68n_5200/dsdt.asl @@ -30,9 +30,6 @@ /* Globals for the platform */ #include "acpi/mainboard.asl" - /* Describe the USB Overcurrent pins */ - #include "acpi/usb_oc.asl" - /* PCI IRQ mapping for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/pcie.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/39077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4711cd1b7fdf49207d5e7c3abd4e077a921ee98 Gerrit-Change-Number: 39077 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 6

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020