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Change in coreboot[master]: mb/intel/jasperlake_rvp: Add memory initialization parameters
by Maulik V Vaghela (Code Review) 23 Jul '20

23 Jul '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38507 ) Change subject: mb/intel/jasperlake_rvp: Add memory initialization parameters ...................................................................... mb/intel/jasperlake_rvp: Add memory initialization parameters JasperLake RVP has 2 different memory support: DDR4 and LPDDR4x Since there are no major difference except for memory configuration, we're not creating variants for this. We'll handle memory parameters based on board id. Board Id for DDR4 board is 1 and LPDDR4 board is 4. BUG=NONE BRANCH=NONE TEST=Build jslrvp board and check compilation Change-Id: Ia59b37900a7f3dba66f47c8f7333aa3503847fff Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c M src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc A src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex M src/mainboard/intel/jasperlake_rvp/spd/spd_util.c 4 files changed, 113 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38507/1 diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c index 0ab1f48..f63f1b3 100644 --- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -13,10 +13,71 @@ * GNU General Public License for more details. */ +#include <arch/byteorder.h> +#include <console/console.h> #include <fsp/api.h> #include <soc/romstage.h> +#include <spd_bin.h> +#include "board_id.h" +#include "spd/spd.h" + +#define BOARD_ID_JSL_DDR4 0x01 void mainboard_memory_init_params(FSPM_UPD *mupd) { - /* ToDo : Fill FSP-M memory params */ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + + u8 board_id = (get_board_id() & 0x1F) & 0x7; + printk(BIOS_DEBUG, "Board Id is 0x%x\n", board_id); + + struct region_device spd_rdev; + + if(board_id == BOARD_ID_JSL_DDR4) { + /* Set Board type for and SmBus Addresses for DDR4 */ + mem_cfg->UserBd = BOARD_TYPE_MOBILE; + + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; + + } else { + + mem_cfg->UserBd = BOARD_TYPE_ULT_ULX; + + /* + * Currently only one SPD is required so keeping spd_index = 0 + * In future if we have more variants, we can change it to be based + * on board id. + */ + uint8_t spd_index = 0; + + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); + + /* set smbus addresses to 0 for Lp4x board */ + + mem_cfg->SpdAddressTable[0] = 0x00; + mem_cfg->SpdAddressTable[1] = 0x00; + mem_cfg->SpdAddressTable[2] = 0x00; + mem_cfg->SpdAddressTable[3] = 0x00; + + mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + } + + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0x2; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + mem_cfg->RefClk = 0; /* Auto Select CLK freq */ + + mainboard_fill_dq_map_ch0(mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_ch1(mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_ch0(mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_ch1(mem_cfg->DqsMapCpu2DramCh1); + mainboard_fill_rcomp_res_data(mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(mem_cfg->RcompTarget); } diff --git a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc index b8b059a..afe855a 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc +++ b/src/mainboard/intel/jasperlake_rvp/spd/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2019 Intel Corporation. +## Copyright (C) 2020 Intel Corporation. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,4 +17,4 @@ SPD_BIN = $(obj)/spd.bin -SPD_SOURCES = empty # 0b000 +SPD_SOURCES = micron16Gb # 0b000 diff --git a/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex b/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex new file mode 100644 index 0000000..a27c249 --- /dev/null +++ b/src/mainboard/intel/jasperlake_rvp/spd/micron16Gb.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 B0 08 00 40 00 00 0A 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c index bdf8ede..afccaf1 100644 --- a/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/jasperlake_rvp/spd/spd_util.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,10 +21,8 @@ #include "spd.h" enum jsl_dimm_type { - jsl_u_ddr4 = 0, - jsl_u_lpddr4 = 1, - jsl_u_lpddr4_type_3 = 4, - jsl_y_lpddr4 = 6 + jsl_u_ddr4 = 1, + jsl_u_lpddr4 = 4, }; void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr) @@ -37,7 +35,7 @@ memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -static uint8_t get_spd_index(void) +static uint8_t get_board_type(void) { return get_board_id() & 0x7; } @@ -54,24 +52,15 @@ void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 }; - const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 }; - const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; + const u8 dqs_map_u_ddr4[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + const u8 dqs_map_u_lpddr4[8] = { 0, 3, 2, 1, 7, 5, 4, 6 }; - switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + memcpy(dqs_map_ptr, dqs_map_u_ddr4, sizeof(dqs_map_u_ddr4)); break; case jsl_u_lpddr4: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3, - sizeof(dqs_map_u_lpddr_type_3)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + memcpy(dqs_map_ptr, dqs_map_u_lpddr4, sizeof(dqs_map_u_lpddr4)); break; default: break; @@ -81,20 +70,15 @@ void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 }; - const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6 }; - const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 }; + const u8 dqs_map_u_ddr4[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; + const u8 dqs_map_u_lpddr4[8] = { 3, 1, 2, 0, 4, 7, 6, 5 }; - switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: - memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr)); + memcpy(dqs_map_ptr, dqs_map_u_ddr4, sizeof(dqs_map_u_ddr4)); break; case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: - memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr)); - break; - case jsl_y_lpddr4: - memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr)); + memcpy(dqs_map_ptr, dqs_map_u_lpddr4, sizeof(dqs_map_u_lpddr4)); break; default: break; @@ -112,18 +96,16 @@ { /* Rcomp target */ static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = { - 100, 33, 32, 33, 28 }; + 0, 0, 0, 0, 0 }; static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = { 80, 40, 40, 40, 30 }; - switch (get_spd_index()) { + switch (get_board_type()) { case jsl_u_ddr4: memcpy(rcomp_strength_ptr, RcompTarget_DDR4, sizeof(RcompTarget_DDR4)); break; - case jsl_y_lpddr4: case jsl_u_lpddr4: - case jsl_u_lpddr4_type_3: memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax, sizeof(RcompTarget_LPDDR4_Ax)); break; -- To view, visit https://review.coreboot.org/c/coreboot/+/38507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia59b37900a7f3dba66f47c8f7333aa3503847fff Gerrit-Change-Number: 38507 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: soc/intel/cannonlake: Enable all C states in FSP
by Maulik V Vaghela (Code Review) 23 Jul '20

23 Jul '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32463 Change subject: soc/intel/cannonlake: Enable all C states in FSP ...................................................................... soc/intel/cannonlake: Enable all C states in FSP FSP will not enable all C-states by default when we use FSP to do MP initialization. We need to set UPD from coreboot to enable C-states in FSP. Change-Id: I845c61fd14f2f5de21288067eeb7c371710da249 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32463/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2b83275..7b28058 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -352,6 +352,9 @@ /* Unlock all GPIO pads */ tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads; + + /* Enable all Cx state in FSP */ + tconfig->Cx = 1; } /* Mainboard GPIO Configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32463 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I845c61fd14f2f5de21288067eeb7c371710da249 Gerrit-Change-Number: 32463 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: cpu/x86/smm: Add support for long mode
by Patrick Rudolph (Code Review) 08 Jul '20

08 Jul '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35681 ) Change subject: cpu/x86/smm: Add support for long mode ...................................................................... cpu/x86/smm: Add support for long mode Enable long mode in SMM handler. x86_32 isn't affected from this change. As the rsm instruction used to leave SMM doesn't restore MSR registers, drop back to protected mode after running the smi_handler and restore IA32_EFER MSR to previous value. Tested on Qemu Q35. Needs tests on real hardware. Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/cpu/x86/smm/smmhandler.S 2 files changed, 95 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/35681/1 diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 462e7e6..b02b879 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -45,6 +45,7 @@ * Add x86_64 exception handlers - *TODO* * Setup page tables for long mode - *DONE* * Add assembly code for long mode - *DONE* +* Add assembly code for SMM - *DONE* * Add assembly code for postcar stage - *TODO* * Add assembly code to return to protected mode - *TODO* * Implement reference code for mainboard `emulation/qemu-q35` - *TODO* diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index a2be7f2..fd8af79 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -20,6 +20,7 @@ */ #include <cpu/x86/lapic_def.h> +#include <cpu/x86/msr.h> /* * +--------------------------------+ 0xaffff @@ -171,15 +172,104 @@ /* Get SMM revision */ movl $0xa8000 + 0x7efc, %ebx /* core 0 address */ subl %ebp, %ebx /* subtract core X offset */ + +#if defined(__x86_64__) + /* Backup IA32_EFER. Preserves ebx. */ + movl $(IA32_EFER), %ecx + rdmsr + movl %eax, ia32efer_backup + + /* Enable long mode if required. Preserves ebx. */ +#include <cpu/x86/64bit/entry64.inc> + + mov (%ebx), %rdi + +#else movl (%ebx), %eax pushl %eax +#endif - /* Call 32bit C handler */ + /* Call C handler */ call smi_handler +#if defined(__x86_64__) + /* + * The only reason to go back to protected mode is that rsm doesn't restore + * MSR registers and IA32_EFER was modified. + * To restore IA32_EFER go back to protected mode. + */ + + /* Ensure cache is clean. */ + invd + + /* Set 32-bit code segment and ss */ + mov $0x08, %rcx + call SetCodeSelector32 + +.code32 + /* Running in 32-bit compatibility mode */ + + /* Use flat data segment */ + movl $0x10, %eax + movl %eax, %ds + movl %eax, %es + movl %eax, %ss + movl %eax, %fs + movl %eax, %gs + + /* Disable paging */ + movl %cr0, %eax + andl $0x7FFFFFFF, %eax + movl %eax, %cr0 + + /* Disable long mode */ + movl $(IA32_EFER), %ecx + rdmsr + andl $(~EFER_LME), %eax + wrmsr + + /* Disable PAE */ + movl %cr4, %eax + andl $(~0x20), %eax + movl %eax, %cr4 + + /* Restore IA32_EFER */ + movl $(IA32_EFER), %ecx + rdmsr + movl ia32efer_backup, %eax + wrmsr +#endif + /* To return, just do rsm. It will "clean up" protected mode */ rsm +#if defined(__x86_64__) +ia32efer_backup: +.long + +.align 8 +.code64 +SetCodeSelector32: + # pop the return address from stack + pop %rbx + + # save rsp because we need to push it after ss + mov %rsp, %rdx + + # use iret to jump to a 32-bit offset in a new code segment + # iret will pop cs:rip, flags, then ss:rsp + mov %ss, %ax # need to push ss.. + push %rax # push ss instuction not valid in x64 mode, + # so use ax + push %rdx # the rsp to load + pushfq # push rflags + push %rcx # cx is code segment selector from caller + push %rbx # push the IP for the next instruction + + # the iretq will behave like ret, with the new cs/ss value loaded + iretq +#endif + .code16 .align 4, 0xff @@ -202,6 +292,9 @@ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + /* gdt selector 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xaf, 0x00 smm_gdt_end: -- To view, visit https://review.coreboot.org/c/coreboot/+/35681 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bba4af4688c723fc079ae905dac95f57ea956f8 Gerrit-Change-Number: 35681 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

6 31

Change in coreboot[master]: mb/lenovo/t60: Switch to override tree
by Peter Lemenkov (Code Review) 06 Jul '20

06 Jul '20

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34779 ) Change subject: mb/lenovo/t60: Switch to override tree ...................................................................... mb/lenovo/t60: Switch to override tree Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/t60/Kconfig R src/mainboard/lenovo/t60/devicetree.cb A src/mainboard/lenovo/t60/variants/t60/overridetree.cb D src/mainboard/lenovo/t60/variants/z61t/devicetree.cb A src/mainboard/lenovo/t60/variants/z61t/overridetree.cb 5 files changed, 135 insertions(+), 257 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/34779/1 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 725528d..ad74f63 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -33,9 +33,9 @@ default "t60" if BOARD_LENOVO_T60 default "z61t" if BOARD_LENOVO_Z61T -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER string diff --git a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb similarity index 93% rename from src/mainboard/lenovo/t60/variants/t60/devicetree.cb rename to src/mainboard/lenovo/t60/devicetree.cb index 9279dcb..70900ea 100644 --- a/src/mainboard/lenovo/t60/variants/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -116,7 +116,6 @@ end register "scr" = "0x0844d070" register "mrr" = "0x01d01002" - end end device pci 1e.2 off end # AC'97 Audio @@ -159,10 +158,6 @@ register "eventb_enable" = "0xff" register "eventc_enable" = "0x3c" register "eventd_enable" = "0xff" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "7" - register "bdc_gpio_lvl" = "0" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR @@ -209,21 +204,12 @@ end end end - device pci 1f.1 on # IDE - subsystemid 0x17aa 0x200c - end device pci 1f.2 on # SATA subsystemid 0x17aa 0x200d end device pci 1f.3 on # SMBUS subsystemid 0x17aa 0x200f chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff }" - register "regs" = "{ 0x2e, 0xf7, 0x3c, - 0x20, 0x01, 0x00, 0x1b, 0x01, - 0x54, 0xff, 0xff, 0x07 }" device i2c 69 on end end # eeprom, 8 virtual devices, same chip diff --git a/src/mainboard/lenovo/t60/variants/t60/overridetree.cb b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb new file mode 100644 index 0000000..eee3a4d --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/t60/overridetree.cb @@ -0,0 +1,69 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2015 + end + device pci 01.0 on # PCI-e + device pci 00.0 on # VGA + subsystemid 0x17aa 0x20a4 + end + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # Ethernet + subsystemid 0x17aa 0x2001 + end + device pci 1c.1 on end # WLAN + device pci 1c.2 on end # PCIe port 3 + device pci 1c.3 on end # PCIe port 4 + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2012 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip ec/lenovo/h8 + register "has_bdc_detection" = "1" + register "bdc_gpio_num" = "7" + register "bdc_gpio_lvl" = "0" + end + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 4 + end + end + end + device pci 1f.1 on # IDE + subsystemid 0x17aa 0x200c + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff }" + register "regs" = "{ 0x2e, 0xf7, 0x3c, + 0x20, 0x01, 0x00, 0x1b, 0x01, + 0x54, 0xff, 0xff, 0x07 }" + end + end + end + end +end diff --git a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb b/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb deleted file mode 100644 index d35c62b..0000000 --- a/src/mainboard/lenovo/t60/variants/z61t/devicetree.cb +++ /dev/null @@ -1,241 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2009 coresystems GmbH -## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> -## -## This program is free software; you can redistribute it and/or -## modify it under the terms of the GNU General Public License as -## published by the Free Software Foundation; version 2 of -## the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -chip northbridge/intel/i945 - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "pwm_freq" = "275" - register "gpu_panel_power_up_delay" = "250" - register "gpu_panel_power_backlight_on_delay" = "2380" - register "gpu_panel_power_down_delay" = "250" - register "gpu_panel_power_backlight_off_delay" = "2380" - register "gpu_panel_power_cycle_delay" = "2" - - device cpu_cluster 0 on - chip cpu/intel/socket_m - device lapic 0 on end - end - end - - register "pci_mmio_size" = "768" - - device domain 0 on - device pci 00.0 on # Host bridge - subsystemid 0x17aa 0x2017 - end - - device pci 01.0 on # PEG - device pci 00.0 on end # VGA - end - - device pci 02.0 on # GMA Graphics controller - subsystemid 0x17aa 0x201a - end - device pci 02.1 on # display controller - subsystemid 0x17aa 0x201a - end - - chip southbridge/intel/i82801gx - register "pirqa_routing" = "0x0b" - register "pirqb_routing" = "0x0b" - register "pirqc_routing" = "0x0b" - register "pirqd_routing" = "0x0b" - register "pirqe_routing" = "0x0b" - register "pirqf_routing" = "0x0b" - register "pirqg_routing" = "0x0b" - register "pirqh_routing" = "0x0b" - - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "2" - register "gpi8_routing" = "2" - - register "sata_ports_implemented" = "0x01" - - register "gpe0_en" = "0x11000006" - register "alt_gp_smi_en" = "0x1000" - - register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" - register "docking_supported" = "1" - register "p_cnt_throttling_supported" = "1" - - device pci 1b.0 on # Audio Controller - subsystemid 0x17aa 0x2010 - end - device pci 1c.0 on # PCI Express Port 1 - subsystemid 0x17aa 0x2011 - end - device pci 1c.1 on # PCI Express Port 2 - subsystemid 0x17aa 0x2011 - end - device pci 1c.2 on # PCI Express Port 3 - subsystemid 0x17aa 0x2011 - end - device pci 1c.3 on # PCI Express Port 4 - subsystemid 0x17aa 0x2011 - end - device pci 1c.4 off end # PCIe port 5 - device pci 1c.5 off end # PCIe port 6 - - device pci 1d.0 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.1 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.2 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.3 on # USB UHCI - subsystemid 0x17aa 0x200a - end - device pci 1d.7 on # USB2 EHCI - subsystemid 0x17aa 0x200b - end - device pci 1e.0 on # PCI Bridge - chip southbridge/ti/pci1x2x - device pci 00.0 on - subsystemid 0x17aa 0x2013 - end - register "scr" = "0x0844d070" - register "mrr" = "0x01d01002" - - end - end - device pci 1e.2 off end # AC'97 Audio - device pci 1e.3 off end # AC'97 Modem - device pci 1f.0 on # PCI-LPC bridge - subsystemid 0x17aa 0x2009 - chip ec/lenovo/pmh7 - device pnp ff.1 on # dummy - end - - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa6" - register "config1" = "0x05" - register "config2" = "0xa0" - register "config3" = "0x01" - - register "beepmask0" = "0xfe" - register "beepmask1" = "0x96" - register "has_power_management_beeps" = "1" - - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xf4" - register "event5_enable" = "0x3f" - register "event6_enable" = "0x80" - register "event7_enable" = "0x01" - register "event8_enable" = "0x01" - register "event9_enable" = "0xff" - register "eventa_enable" = "0xff" - register "eventb_enable" = "0xff" - register "eventc_enable" = "0x3c" - register "eventd_enable" = "0xff" - - end - chip superio/nsc/pc87382 - device pnp 164e.2 on # IR - io 0x60 = 0x2f8 - end - - device pnp 164e.3 off # Serial Port - io 0x60 = 0x3f8 - end - - device pnp 164e.7 on # GPIO - io 0x60 = 0x1680 - end - - device pnp 164e.19 on # DLPC - io 0x60 = 0x164c - end - end - - chip superio/nsc/pc87384 - device pnp 2e.0 off #FDC - end - - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x3bc - irq 0x70 = 7 - end - - device pnp 2e.2 off # Serial Port / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - - device pnp 2e.3 on # Serial Port - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - - device pnp 2e.7 on # GPIO - io 0x60 = 0x1620 - end - - device pnp 2e.a off # WDT - end - end - end - device pci 1f.2 on # SATA - subsystemid 0x17aa 0x200d - end - device pci 1f.3 on # SMBUS - subsystemid 0x17aa 0x200f - chip drivers/i2c/ck505 - register "mask" = "{ 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff }" - # vendor clockgen setup - register "regs" = "{ 0x6d, 0xff, 0xff, - 0x20, 0x41, 0x7f, 0x18, 0x00 }" - device i2c 69 on end - end - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end - end - end -end diff --git a/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb new file mode 100644 index 0000000..d29df3b --- /dev/null +++ b/src/mainboard/lenovo/t60/variants/z61t/overridetree.cb @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/i945 + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2017 + end + device pci 01.0 on # PEG + device pci 00.0 on end # VGA + end + chip southbridge/intel/i82801gx + device pci 1c.0 on # PCI Express Port 1 + subsystemid 0x17aa 0x2011 + end + device pci 1c.1 on # PCI Express Port 2 + subsystemid 0x17aa 0x2011 + end + device pci 1c.2 on # PCI Express Port 3 + subsystemid 0x17aa 0x2011 + end + device pci 1c.3 on # PCI Express Port 4 + subsystemid 0x17aa 0x2011 + end + device pci 1e.0 on # PCI Bridge + chip southbridge/ti/pci1x2x + device pci 00.0 on + subsystemid 0x17aa 0x2013 + end + end + end + device pci 1f.0 on # PCI-LPC bridge + chip superio/nsc/pc87384 + device pnp 2e.2 off # Serial Port / IR + irq 0x70 = 3 + end + end + end + device pci 1f.3 on # SMBUS + chip drivers/i2c/ck505 + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff }" + # vendor clockgen setup + register "regs" = "{ 0x6d, 0xff, 0xff, + 0x20, 0x41, 0x7f, 0x18, 0x00 }" + end + end + end + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/34779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c0134b22e2203e6cee6ecafda0dae89e086aff Gerrit-Change-Number: 34779 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: [TESTONLY] devicetree: Remove weak declarations for ops
by Kyösti Mälkki (Code Review) 06 Jul '20

06 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35086 ) Change subject: [TESTONLY] devicetree: Remove weak declarations for ops ...................................................................... [TESTONLY] devicetree: Remove weak declarations for ops Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M util/sconfig/main.c 1 file changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/35086/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5e3a1d4..586de06 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -936,9 +936,14 @@ chip = tmp; while (chip) { - fprintf(fil, - "__attribute__((weak)) struct chip_operations %s_ops = {};\n", - chip->name_underscore); + if (strstr(chip->name_underscore, "cpu_") == chip->name_underscore) { + fprintf(fil, + "__attribute__((weak)) struct chip_operations %s_ops = {};\n", + chip->name_underscore); + } else { + fprintf(fil, "extern struct chip_operations %s_ops;\n", + chip->name_underscore); + } chip = chip->next; } fprintf(fil, "#endif\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/35086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb783e2f733d5c65c615e5c1879e3e4c7a83e049 Gerrit-Change-Number: 35086 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

9 25

Change in coreboot[master]: mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS
by Arthur Heymans (Code Review) 06 Jul '20

06 Jul '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35871 ) Change subject: mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS ...................................................................... mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESS Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/intel/dg43gt/Kconfig 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/35871/1 diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index 341baaa..64bda37 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -40,11 +40,6 @@ string default "8086,2e22" - -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config MAINBOARD_DIR string default "intel/dg43gt" -- To view, visit https://review.coreboot.org/c/coreboot/+/35871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48 Gerrit-Change-Number: 35871 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: util/inteltool: Refactoring #2
by Felix Singer (Code Review) 04 Jul '20

04 Jul '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31634 Change subject: util/inteltool: Refactoring #2 ...................................................................... util/inteltool: Refactoring #2 Change-Id: Ie92a5af141a907251fc847d53c767984949d9312 Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M util/inteltool/Makefile M util/inteltool/gpio.h A util/inteltool/gpio_test.c A util/inteltool/gpio_test.h 4 files changed, 447 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/31634/1 diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index d88063b..0097831 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -28,7 +28,7 @@ CPPFLAGS += -I$(top)/src/commonlib/include OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ - memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ + memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o gpio_test.o \ OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h index c89f393..161e9bb 100644 --- a/util/inteltool/gpio.h +++ b/util/inteltool/gpio.h @@ -17,6 +17,36 @@ #ifndef GPIO_H #define GPIO_H + +// Describes a native function +struct native_mode { + uint8_t mode; + char *name; +}; + +/* + * Describes a GPIO pad, which optionally can + * have one or more native functions and a default + * mode. If no default mode is set, + * default_mode to -1, else set it to the + * function number. + */ +struct gpio_pad { + const char *name; + uint8_t default_mode; + const struct native_mode *modes; + uint64_t default_config; + uint64_t config; +}; + +/* +struct gpio_pad { + const char *name; + size_t defaultMode; + const char **functions; +}; +*/ + struct gpio_group { const char *display; size_t pad_count; diff --git a/util/inteltool/gpio_test.c b/util/inteltool/gpio_test.c new file mode 100644 index 0000000..9052623 --- /dev/null +++ b/util/inteltool/gpio_test.c @@ -0,0 +1,66 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h> +#include <assert.h> +#include <inttypes.h> +#include "inteltool.h" +#include "pcr.h" +#include "gpio.h" +#include "gpio_test.h" + +#define SBBAR_SIZE (16 * MiB) +#define PCR_PORT_SIZE (64 * KiB) + +void select_gpio_community(struct pci_dev *const sb) +{ + size_t community_count; + const struct gpio_community *const *communities; + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_B150: + case PCI_DEVICE_ID_INTEL_CM236: +// community_count = ARRAY_SIZE(sunrise_communities); +// communities = sunrise_communities; +// pcr_init(sb); + break; + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM: + case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM: +// community_count = ARRAY_SIZE(sunrise_lp_communities); +// communities = sunrise_lp_communities; +// pcr_init(sb); + break; + case PCI_DEVICE_ID_INTEL_DNV_LPC: +// community_count = ARRAY_SIZE(denverton_communities); +// communities = denverton_communities; +// pcr_init(sb); + break; + default: + return; + } + + printf("\n============= GPIOS =============\n\n"); + +// for (; community_count; --community_count) +// print_gpio_community(*communities++); +} diff --git a/util/inteltool/gpio_test.h b/util/inteltool/gpio_test.h new file mode 100644 index 0000000..9edc4fe --- /dev/null +++ b/util/inteltool/gpio_test.h @@ -0,0 +1,350 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * Copyright (C) 2019 by 9elements Agency GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "gpio.h" + +#ifndef GPIO_TEST_H +#define GPIO_TEST_H + +/* +const struct gpio_pad test[] = { + { "gpio1", 2, (const char *[]) { "function1", "function2", NULL, } }, +}; +*/ + +const struct gpio_pad test[] = { + { "GPP_A0", -1, (const struct native_mode[]) { {1, "RCIN#" }, }, }, + { "GPP_A1", -1, (const struct native_mode[]) { {1, "LAD0" }, {3, "ESPI_IO0" }, }, }, + { "GPP_A2", -1, (const struct native_mode[]) { {1, "LAD1" }, {3, "ESPI_IO1" }, }, }, + { "GPP_A3", -1, (const struct native_mode[]) { {1, "LAD2" }, {3, "ESPI_IO2" }, }, }, + { "GPP_A4", -1, (const struct native_mode[]) { {1, "LAD3" }, {3, "ESPI_IO3" }, }, }, + { "GPP_A5", -1, (const struct native_mode[]) { {1, "LFRAME#" }, {3, "ESPI_CS#" }, }, }, + { "GPP_A6", -1, (const struct native_mode[]) { {1, "SERIRQ#" }, }, }, + { "GPP_A7", -1, (const struct native_mode[]) { {1, "PIRQA#" }, }, }, + { "GPP_A8", -1, (const struct native_mode[]) { {1, "CLKRUN#" }, }, }, + { "GPP_A9", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC0" }, {3, "ESPI_CLK" }, }, }, + { "GPP_A10", -1, (const struct native_mode[]) { {1, "CLKOUT_LPC1" }, }, }, + { "GPP_A11", -1, (const struct native_mode[]) { {1, "PME#" }, }, }, + { "GPP_A12", -1, (const struct native_mode[]) { {1, "BM_BUSY#" }, {2, "ISH_GP6" }, {3, "SX_EXIT_HOLDOFF#" }, }, }, + { "GPP_A13", -1, (const struct native_mode[]) { {1, "SUSWARN#/SUSPWRDNACK" }, }, }, + { "GPP_A14", -1, (const struct native_mode[]) { {1, "SUS_STAT#" }, {3, "ESPI_RESET#" }, }, }, + { "GPP_A15", -1, (const struct native_mode[]) { {1, "SUS_ACK#" }, }, }, + { "GPP_A16", -1, (const struct native_mode[]) { {1, "SD_1P8_SEL" }, }, }, + { "GPP_A17", -1, (const struct native_mode[]) { {1, "SD_PWR_EN#" }, {2, "ISH_GP7" }, }, }, + { "GPP_A18", -1, (const struct native_mode[]) { {1, "ISH_GP0" }, }, }, + { "GPP_A19", -1, (const struct native_mode[]) { {1, "ISH_GP1" }, }, }, + { "GPP_A20", -1, (const struct native_mode[]) { {1, "ISH_GP2" }, }, }, + { "GPP_A21", -1, (const struct native_mode[]) { {1, "ISH_GP3" }, }, }, + { "GPP_A22", -1, (const struct native_mode[]) { {1, "ISH_GP4" }, }, }, + { "GPP_A23", -1, (const struct native_mode[]) { {1, "ISH_GP5" }, }, }, +}; + +/* +const char *const sunrise_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "n/a", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_a = { + .display = "------- GPIO group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_a_names, +}; + +const char *const sunrise_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPI0_CS#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +const struct gpio_group sunrise_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_b_names, +}; + +const struct gpio_group *const sunrise_lp_community_ab_groups[] = { + &sunrise_lp_group_a, &sunrise_lp_group_b, +}; + +const struct gpio_community sunrise_lp_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), + .groups = sunrise_lp_community_ab_groups, +}; + +const char *const sunrise_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", +}; + +const struct gpio_group sunrise_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_c_names, +}; + +const char *const sunrise_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "n/a", + "GPP_D1", "SPI1_CLK", "n/a", "n/a", + "GPP_D2", "SPI1_MISO", "n/a", "n/a", + "GPP_D3", "SPI1_MOSI", "n/a", "n/a", + "GPP_D4", "FLASHTRIG", "n/a", "n/a", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_d_names, +}; + +const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "n/a", "n/a", + "GPP_E14", "DDPC_HPD1", "n/a", "n/a", + "GPP_E15", "DDPD_HPD2", "n/a", "n/a", + "GPP_E16", "DDPE_HPD3", "n/a", "n/a", + "GPP_E17", "EDP_HPD", "n/a", "n/a", + "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + +const char *const sunrise_lp_group_f_names[] = { + "GPP_F0", "I2S2_SCLK", "n/a", "n/a", + "GPP_F1", "I2S2_SFRM", "n/a", "n/a", + "GPP_F2", "I2S2_TXD", "n/a", "n/a", + "GPP_F3", "I2S2_RXD", "n/a", "n/a", + "GPP_F4", "I2C2_SDA", "n/a", "n/a", + "GPP_F5", "I2C2_SCL", "n/a", "n/a", + "GPP_F6", "I2C3_SDA", "n/a", "n/a", + "GPP_F7", "I2C3_SCL", "n/a", "n/a", + "GPP_F8", "I2C4_SDA", "n/a", "n/a", + "GPP_F9", "I2C4_SCL", "n/a", "n/a", + "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_F12", "EMMC_CMD", "n/a", "n/a", + "GPP_F13", "EMMC_DATA0", "n/a", "n/a", + "GPP_F14", "EMMC_DATA1", "n/a", "n/a", + "GPP_F15", "EMMC_DATA2", "n/a", "n/a", + "GPP_F16", "EMMC_DATA3", "n/a", "n/a", + "GPP_F17", "EMMC_DATA4", "n/a", "n/a", + "GPP_F18", "EMMC_DATA5", "n/a", "n/a", + "GPP_F19", "EMMC_DATA6", "n/a", "n/a", + "GPP_F20", "EMMC_DATA7", "n/a", "n/a", + "GPP_F21", "EMMC_RCLK", "n/a", "n/a", + "GPP_F22", "EMMC_CLK", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_f_names, +}; + +const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", + "GPP_G3", "SD_DATA2", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", +}; + +const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + +const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, +}; + +const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + +const char *const sunrise_group_gpd_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", +}; + +const struct gpio_group sunrise_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_gpd_names, +}; + +const struct gpio_group *const sunrise_community_gpd_groups[] = { + &sunrise_group_gpd, +}; + +const struct gpio_community sunrise_community_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), + .groups = sunrise_community_gpd_groups, +}; + +const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_lp_group_f, &sunrise_lp_group_g, +}; + +const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + +const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_lp_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +}; +*/ +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31634 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie92a5af141a907251fc847d53c767984949d9312 Gerrit-Change-Number: 31634 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

3 10

Change in ...coreboot[master]: util/inteltool: Refactor code of GPIO groups
by Felix Singer (Code Review) 04 Jul '20

04 Jul '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31504 Change subject: util/inteltool: Refactor code of GPIO groups ...................................................................... util/inteltool: Refactor code of GPIO groups Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- A util/inteltool/gpio.h A util/inteltool/gpio_denverton.h M util/inteltool/gpio_groups.c A util/inteltool/gpio_sunrise.h 4 files changed, 865 insertions(+), 816 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/31504/1 diff --git a/util/inteltool/gpio.h b/util/inteltool/gpio.h new file mode 100644 index 0000000..64f62f8 --- /dev/null +++ b/util/inteltool/gpio.h @@ -0,0 +1,29 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +struct gpio_group { + const char *display; + size_t pad_count; + size_t func_count; + const char *const *pad_names; /* indexed by 'pad * func_count + func' */ +}; + +struct gpio_community { + const char *name; + uint8_t pcr_port_id; + size_t group_count; + const struct gpio_group *const *groups; +}; diff --git a/util/inteltool/gpio_denverton.h b/util/inteltool/gpio_denverton.h new file mode 100644 index 0000000..e745b44 --- /dev/null +++ b/util/inteltool/gpio_denverton.h @@ -0,0 +1,237 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const denverton_group_north_all_names[] = { + "NORTH_ALL_GBE0_SDP0", + "NORTH_ALL_GBE1_SDP0", + "NORTH_ALL_GBE0_SDP1", + "NORTH_ALL_GBE1_SDP1", + "NORTH_ALL_GBE0_SDP2", + "NORTH_ALL_GBE1_SDP2", + "NORTH_ALL_GBE0_SDP3", + "NORTH_ALL_GBE1_SDP3", + "NORTH_ALL_GBE2_LED0", + "NORTH_ALL_GBE2_LED1", + "NORTH_ALL_GBE0_I2C_CLK", + "NORTH_ALL_GBE0_I2C_DATA", + "NORTH_ALL_GBE1_I2C_CLK", + "NORTH_ALL_GBE1_I2C_DATA", + "NORTH_ALL_NCSI_RXD0", + "NORTH_ALL_NCSI_CLK_IN", + "NORTH_ALL_NCSI_RXD1", + "NORTH_ALL_NCSI_CRS_DV", + "NORTH_ALL_NCSI_ARB_IN", + "NORTH_ALL_NCSI_TX_EN", + "NORTH_ALL_NCSI_TXD0", + "NORTH_ALL_NCSI_TXD1", + "NORTH_ALL_NCSI_ARB_OUT", + "NORTH_ALL_GBE0_LED0", + "NORTH_ALL_GBE0_LED1", + "NORTH_ALL_GBE1_LED0", + "NORTH_ALL_GBE1_LED1", + "NORTH_ALL_GPIO_0", + "NORTH_ALL_PCIE_CLKREQ0_N", + "NORTH_ALL_PCIE_CLKREQ1_N", + "NORTH_ALL_PCIE_CLKREQ2_N", + "NORTH_ALL_PCIE_CLKREQ3_N", + "NORTH_ALL_PCIE_CLKREQ4_N", + "NORTH_ALL_GPIO_1", + "NORTH_ALL_GPIO_2", + "NORTH_ALL_SVID_ALERT_N", + "NORTH_ALL_SVID_DATA", + "NORTH_ALL_SVID_CLK", + "NORTH_ALL_THERMTRIP_N", + "NORTH_ALL_PROCHOT_N", + "NORTH_ALL_MEMHOT_N", +}; + +static const struct gpio_group denverton_group_north_all = { + .display = "------- GPIO Group North All -------", + .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, + .func_count = 1, + .pad_names = denverton_group_north_all_names, +}; + +static const struct gpio_group *const denverton_community_north_groups[] = { + &denverton_group_north_all, +}; + +static const struct gpio_community denverton_community_north = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xc2, + .group_count = ARRAY_SIZE(denverton_community_north_groups), + .groups = denverton_community_north_groups, +}; + +static const char *const denverton_group_south_dfx_names[] = { + "SOUTH_DFX_DFX_PORT_CLK0", + "SOUTH_DFX_DFX_PORT_CLK1", + "SOUTH_DFX_DFX_PORT0", + "SOUTH_DFX_DFX_PORT1", + "SOUTH_DFX_DFX_PORT2", + "SOUTH_DFX_DFX_PORT3", + "SOUTH_DFX_DFX_PORT4", + "SOUTH_DFX_DFX_PORT5", + "SOUTH_DFX_DFX_PORT6", + "SOUTH_DFX_DFX_PORT7", + "SOUTH_DFX_DFX_PORT8", + "SOUTH_DFX_DFX_PORT9", + "SOUTH_DFX_DFX_PORT10", + "SOUTH_DFX_DFX_PORT11", + "SOUTH_DFX_DFX_PORT12", + "SOUTH_DFX_DFX_PORT13", + "SOUTH_DFX_DFX_PORT14", + "SOUTH_DFX_DFX_PORT15", +}; + +static const struct gpio_group denverton_group_south_dfx = { + .display = "------- GPIO Group South DFX -------", + .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_dfx_names, +}; + +static const char *const denverton_group_south_group0_names[] = { + "SOUTH_GROUP0_GPIO_12", + "SOUTH_GROUP0_SMB5_GBE_ALRT_N", + "SOUTH_GROUP0_PCIE_CLKREQ5_N", + "SOUTH_GROUP0_PCIE_CLKREQ6_N", + "SOUTH_GROUP0_PCIE_CLKREQ7_N", + "SOUTH_GROUP0_UART0_RXD", + "SOUTH_GROUP0_UART0_TXD", + "SOUTH_GROUP0_SMB5_GBE_CLK", + "SOUTH_GROUP0_SMB5_GBE_DATA", + "SOUTH_GROUP0_ERROR2_N", + "SOUTH_GROUP0_ERROR1_N", + "SOUTH_GROUP0_ERROR0_N", + "SOUTH_GROUP0_IERR_N", + "SOUTH_GROUP0_MCERR_N", + "SOUTH_GROUP0_SMB0_LEG_CLK", + "SOUTH_GROUP0_SMB0_LEG_DATA", + "SOUTH_GROUP0_SMB0_LEG_ALRT_N", + "SOUTH_GROUP0_SMB1_HOST_DATA", + "SOUTH_GROUP0_SMB1_HOST_CLK", + "SOUTH_GROUP0_SMB2_PECI_DATA", + "SOUTH_GROUP0_SMB2_PECI_CLK", + "SOUTH_GROUP0_SMB4_CSME0_DATA", + "SOUTH_GROUP0_SMB4_CSME0_CLK", + "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", + "SOUTH_GROUP0_USB_OC0_N", + "SOUTH_GROUP0_FLEX_CLK_SE0", + "SOUTH_GROUP0_FLEX_CLK_SE1", + "SOUTH_GROUP0_GPIO_4", + "SOUTH_GROUP0_GPIO_5", + "SOUTH_GROUP0_GPIO_6", + "SOUTH_GROUP0_GPIO_7", + "SOUTH_GROUP0_SATA0_LED_N", + "SOUTH_GROUP0_SATA1_LED_N", + "SOUTH_GROUP0_SATA_PDETECT0", + "SOUTH_GROUP0_SATA_PDETECT1", + "SOUTH_GROUP0_SATA0_SDOUT", + "SOUTH_GROUP0_SATA1_SDOUT", + "SOUTH_GROUP0_UART1_RXD", + "SOUTH_GROUP0_UART1_TXD", + "SOUTH_GROUP0_GPIO_8", + "SOUTH_GROUP0_GPIO_9", + "SOUTH_GROUP0_TCK", + "SOUTH_GROUP0_TRST_N", + "SOUTH_GROUP0_TMS", + "SOUTH_GROUP0_TDI", + "SOUTH_GROUP0_TDO", + "SOUTH_GROUP0_CX_PRDY_N", + "SOUTH_GROUP0_CX_PREQ_N", + "SOUTH_GROUP0_CTBTRIGINOUT", + "SOUTH_GROUP0_CTBTRIGOUT", + "SOUTH_GROUP0_DFX_SPARE2", + "SOUTH_GROUP0_DFX_SPARE3", + "SOUTH_GROUP0_DFX_SPARE4", +}; + +static const struct gpio_group denverton_group_south_group0 = { + .display = "------- GPIO Group South Group0 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group0_names, +}; + +static const char *const denverton_group_south_group1_names[] = { + "SOUTH_GROUP1_SUSPWRDNACK", + "SOUTH_GROUP1_PMU_SUSCLK", + "SOUTH_GROUP1_ADR_TRIGGER", + "SOUTH_GROUP1_PMU_SLP_S45_N", + "SOUTH_GROUP1_PMU_SLP_S3_N", + "SOUTH_GROUP1_PMU_WAKE_N", + "SOUTH_GROUP1_PMU_PWRBTN_N", + "SOUTH_GROUP1_PMU_RESETBUTTON_N", + "SOUTH_GROUP1_PMU_PLTRST_N", + "SOUTH_GROUP1_SUS_STAT_N", + "SOUTH_GROUP1_SLP_S0IX_N", + "SOUTH_GROUP1_SPI_CS0_N", + "SOUTH_GROUP1_SPI_CS1_N", + "SOUTH_GROUP1_SPI_MOSI_IO0", + "SOUTH_GROUP1_SPI_MISO_IO1", + "SOUTH_GROUP1_SPI_IO2", + "SOUTH_GROUP1_SPI_IO3", + "SOUTH_GROUP1_SPI_CLK", + "SOUTH_GROUP1_SPI_CLK_LOOPBK", + "SOUTH_GROUP1_ESPI_IO0", + "SOUTH_GROUP1_ESPI_IO1", + "SOUTH_GROUP1_ESPI_IO2", + "SOUTH_GROUP1_ESPI_IO3", + "SOUTH_GROUP1_ESPI_CS0_N", + "SOUTH_GROUP1_ESPI_CLK", + "SOUTH_GROUP1_ESPI_RST_N", + "SOUTH_GROUP1_ESPI_ALRT0_N", + "SOUTH_GROUP1_GPIO_10", + "SOUTH_GROUP1_GPIO_11", + "SOUTH_GROUP1_ESPI_CLK_LOOPBK", + "SOUTH_GROUP1_EMMC_CMD", + "SOUTH_GROUP1_EMMC_STROBE", + "SOUTH_GROUP1_EMMC_CLK", + "SOUTH_GROUP1_EMMC_D0", + "SOUTH_GROUP1_EMMC_D1", + "SOUTH_GROUP1_EMMC_D2", + "SOUTH_GROUP1_EMMC_D3", + "SOUTH_GROUP1_EMMC_D4", + "SOUTH_GROUP1_EMMC_D5", + "SOUTH_GROUP1_EMMC_D6", + "SOUTH_GROUP1_EMMC_D7", + "SOUTH_GROUP1_GPIO_3", +}; + +static const struct gpio_group denverton_group_south_group1 = { + .display = "------- GPIO Group South Group1 -------", + .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, + .func_count = 1, + .pad_names = denverton_group_south_group1_names, +}; + +static const struct gpio_group *const denverton_community_south_groups[] = { + &denverton_group_south_dfx, + &denverton_group_south_group0, + &denverton_group_south_group1, +}; + +static const struct gpio_community denverton_community_south = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xc5, + .group_count = ARRAY_SIZE(denverton_community_south_groups), + .groups = denverton_community_south_groups, +}; + +static const struct gpio_community *const denverton_communities[] = { + &denverton_community_north, &denverton_community_south, +}; diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 53a8eb9..c7ab186 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2,6 +2,7 @@ * inteltool - dump all registers on an Intel CPU + chipset based system. * * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,826 +22,13 @@ #include <inttypes.h> #include "inteltool.h" #include "pcr.h" +#include "gpio.h" +#include "gpio_denverton.h" +#include "gpio_sunrise.h" #define SBBAR_SIZE (16 * MiB) #define PCR_PORT_SIZE (64 * KiB) -struct gpio_group { - const char *display; - size_t pad_count; - size_t func_count; - const char *const *pad_names; /* indexed by 'pad * func_count + func' */ -}; - -struct gpio_community { - const char *name; - uint8_t pcr_port_id; - size_t group_count; - const struct gpio_group *const *groups; -}; - -static const char *const sunrise_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", - "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "CLKOUT_48", "n/a", "n/a", - "GPP_A17", "ISH_GP7", "n/a", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_a = { - .display = "------- GPIO Group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_a_names, -}; - -static const char *const sunrise_lp_group_a_names[] = { - "GPP_A0", "RCIN#", "n/a", "n/a", - "GPP_A1", "LAD0", "n/a", "ESPI_IO0", - "GPP_A2", "LAD1", "n/a", "ESPI_IO1", - "GPP_A3", "LAD2", "n/a", "ESPI_IO2", - "GPP_A4", "LAD3", "n/a", "ESPI_IO3", - "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", - "GPP_A6", "SERIRQ", "n/a", "n/a", - "GPP_A7", "PIRQA#", "n/a", "n/a", - "GPP_A8", "CLKRUN#", "n/a", "n/a", - "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", - "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", - "GPP_A11", "PME#", "n/a", "n/a", - "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", - "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", - "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", - "GPP_A15", "SUS_ACK#", "n/a", "n/a", - "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", - "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", - "GPP_A18", "ISH_GP0", "n/a", "n/a", - "GPP_A19", "ISH_GP1", "n/a", "n/a", - "GPP_A20", "ISH_GP2", "n/a", "n/a", - "GPP_A21", "ISH_GP3", "n/a", "n/a", - "GPP_A22", "ISH_GP4", "n/a", "n/a", - "GPP_A23", "ISH_GP5", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_a = { - .display = "------- GPIO group GPP_A -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_a_names, -}; - -static const char *const sunrise_group_b_names[] = { - "GPP_B0", "n/a", "n/a", "n/a", - "GPP_B1", "n/a", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "n/a", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPIO_CS#", "n/a", "n/a", - "GPP_B16", "GSPIO_CLK", "n/a", "n/a", - "GPP_B17", "GSPIO_MISO", "n/a", "n/a", - "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_b_names, -}; - -static const char *const sunrise_lp_group_b_names[] = { - "GPP_B0", "CORE_VID0", "n/a", "n/a", - "GPP_B1", "CORE_VID1", "n/a", "n/a", - "GPP_B2", "VRALERT#", "n/a", "n/a", - "GPP_B3", "CPU_GP2", "n/a", "n/a", - "GPP_B4", "CPU_GP3", "n/a", "n/a", - "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", - "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", - "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", - "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", - "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", - "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", - "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", - "GPP_B12", "SLP_S0#", "n/a", "n/a", - "GPP_B13", "PLTRST#", "n/a", "n/a", - "GPP_B14", "SPKR", "n/a", "n/a", - "GPP_B15", "GSPI0_CS#", "n/a", "n/a", - "GPP_B16", "GSPI0_CLK", "n/a", "n/a", - "GPP_B17", "GSPI0_MISO", "n/a", "n/a", - "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", - "GPP_B19", "GSPI1_CS#", "n/a", "n/a", - "GPP_B20", "GSPI1_CLK", "n/a", "n/a", - "GPP_B21", "GSPI1_MISO", "n/a", "n/a", - "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", - "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_b = { - .display = "------- GPIO Group GPP_B -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_b_names, -}; - -static const struct gpio_group *const sunrise_community_ab_groups[] = { - &sunrise_group_a, &sunrise_group_b, -}; - -static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { - &sunrise_lp_group_a, &sunrise_lp_group_b, -}; - -static const struct gpio_community sunrise_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_community_ab_groups), - .groups = sunrise_community_ab_groups, -}; - -static const struct gpio_community sunrise_lp_community_ab = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xaf, - .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), - .groups = sunrise_lp_community_ab_groups, -}; - -static const char *const sunrise_group_c_names[] = { - "GPP_C0", "SMBCLK", "n/a", "n/a", - "GPP_C1", "SMBDATA", "n/a", "n/a", - "GPP_C2", "SMBALERT#", "n/a", "n/a", - "GPP_C3", "SML0CLK", "n/a", "n/a", - "GPP_C4", "SML0DATA", "n/a", "n/a", - "GPP_C5", "SML0ALERT#", "n/a", "n/a", - "GPP_C6", "SML1CLK", "n/a", "n/a", - "GPP_C7", "SML1DATA", "n/a", "n/a", - "GPP_C8", "UART0_RXD", "n/a", "n/a", - "GPP_C9", "UART0_TXD", "n/a", "n/a", - "GPP_C10", "UART0_RTS#", "n/a", "n/a", - "GPP_C11", "UART0_CTS#", "n/a", "n/a", - "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", - "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", - "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", - "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", - "GPP_C16", "I2C0_SDA", "n/a", "n/a", - "GPP_C17", "I2C0_SCL", "n/a", "n/a", - "GPP_C18", "I2C1_SDA", "n/a", "n/a", - "GPP_C19", "I2C1_SCL", "n/a", "n/a", - "GPP_C20", "UART2_RXD", "n/a", "n/a", - "GPP_C21", "UART2_TXD", "n/a", "n/a", - "GPP_C22", "UART2_RTS#", "n/a", "n/a", - "GPP_C23", "UART2_CTS#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_c = { - .display = "------- GPIO Group GPP_C -------", - .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_c_names, -}; - -static const char *const sunrise_group_d_names[] = { - "GPP_D0", "n/a", "n/a", "n/a", - "GPP_D1", "n/a", "n/a", "n/a", - "GPP_D2", "n/a", "n/a", "n/a", - "GPP_D3", "n/a", "n/a", "n/a", - "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", - "GPP_D5", "I2S_SFRM", "n/a", "n/a", - "GPP_D6", "I2S_TXD", "n/a", "n/a", - "GPP_D7", "I2S_RXD", "n/a", "n/a", - "GPP_D8", "I2S_SCLK", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", - "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "n/a", "n/a", "n/a", - "GPP_D22", "n/a", "n/a", "n/a", - "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", -}; - -static const struct gpio_group sunrise_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_d_names, -}; - -static const char *const sunrise_lp_group_d_names[] = { - "GPP_D0", "SPI1_CS#", "n/a", "n/a", - "GPP_D1", "SPI1_CLK", "n/a", "n/a", - "GPP_D2", "SPI1_MISO", "n/a", "n/a", - "GPP_D3", "SPI1_MOSI", "n/a", "n/a", - "GPP_D4", "FLASHTRIG", "n/a", "n/a", - "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_D9", "n/a", "n/a", "n/a", - "GPP_D10", "n/a", "n/a", "n/a", - "GPP_D11", "n/a", "n/a", "n/a", - "GPP_D12", "n/a", "n/a", "n/a", - "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", - "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", - "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", - "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", - "GPP_D17", "DMIC_CLK1", "n/a", "n/a", - "GPP_D18", "DMIC_DATA1", "n/a", "n/a", - "GPP_D19", "DMIC_CLK0", "n/a", "n/a", - "GPP_D20", "DMIC_DATA0", "n/a", "n/a", - "GPP_D21", "SPI1_IO2", "n/a", "n/a", - "GPP_D22", "SPI1_IO3", "n/a", "n/a", - "GPP_D23", "I2S_MCLK", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_d = { - .display = "------- GPIO Group GPP_D -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_d_names, -}; - -static const char *const sunrise_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATA_LED#", "n/a", "n/a", - "GPP_E9", "USB_OC0#", "n/a", "n/a", - "GPP_E10", "USB_OC1#", "n/a", "n/a", - "GPP_E11", "USB_OC2#", "n/a", "n/a", - "GPP_E12", "USB_OC3#", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_e_names, -}; - -static const char *const sunrise_lp_group_e_names[] = { - "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", - "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", - "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", - "GPP_E3", "CPU_GP0", "n/a", "n/a", - "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", - "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", - "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", - "GPP_E7", "CPU_GP1", "n/a", "n/a", - "GPP_E8", "SATALED#", "n/a", "n/a", - "GPP_E9", "USB2_OC0#", "n/a", "n/a", - "GPP_E10", "USB2_OC1#", "n/a", "n/a", - "GPP_E11", "USB2_OC2#", "n/a", "n/a", - "GPP_E12", "USB2_OC3#", "n/a", "n/a", - "GPP_E13", "DDPB_HPD0", "n/a", "n/a", - "GPP_E14", "DDPC_HPD1", "n/a", "n/a", - "GPP_E15", "DDPD_HPD2", "n/a", "n/a", - "GPP_E16", "DDPE_HPD3", "n/a", "n/a", - "GPP_E17", "EDP_HPD", "n/a", "n/a", - "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_E22", "n/a", "n/a", "n/a", - "GPP_E23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_e = { - .display = "------- GPIO Group GPP_E -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_e_names, -}; - -static const char *const sunrise_group_f_names[] = { - "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", - "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", - "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", - "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", - "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", - "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", - "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", - "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", - "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", - "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", - "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", - "GPP_F11", "SATA_SLOAD", "n/a", "n/a", - "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", - "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", - "GPP_F14", "n/a", "n/a", "n/a", - "GPP_F15", "USB_OC4#", "n/a", "n/a", - "GPP_F16", "USB_OC5#", "n/a", "n/a", - "GPP_F17", "USB_OC6#", "n/a", "n/a", - "GPP_F18", "USB_OC7#", "n/a", "n/a", - "GPP_F19", "eDP_VDDEN", "n/a", "n/a", - "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", - "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", - "GPP_F22", "n/a", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_f_names, -}; - -static const char *const sunrise_lp_group_f_names[] = { - "GPP_F0", "I2S2_SCLK", "n/a", "n/a", - "GPP_F1", "I2S2_SFRM", "n/a", "n/a", - "GPP_F2", "I2S2_TXD", "n/a", "n/a", - "GPP_F3", "I2S2_RXD", "n/a", "n/a", - "GPP_F4", "I2C2_SDA", "n/a", "n/a", - "GPP_F5", "I2C2_SCL", "n/a", "n/a", - "GPP_F6", "I2C3_SDA", "n/a", "n/a", - "GPP_F7", "I2C3_SCL", "n/a", "n/a", - "GPP_F8", "I2C4_SDA", "n/a", "n/a", - "GPP_F9", "I2C4_SCL", "n/a", "n/a", - "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", - "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", - "GPP_F12", "EMMC_CMD", "n/a", "n/a", - "GPP_F13", "EMMC_DATA0", "n/a", "n/a", - "GPP_F14", "EMMC_DATA1", "n/a", "n/a", - "GPP_F15", "EMMC_DATA2", "n/a", "n/a", - "GPP_F16", "EMMC_DATA3", "n/a", "n/a", - "GPP_F17", "EMMC_DATA4", "n/a", "n/a", - "GPP_F18", "EMMC_DATA5", "n/a", "n/a", - "GPP_F19", "EMMC_DATA6", "n/a", "n/a", - "GPP_F20", "EMMC_DATA7", "n/a", "n/a", - "GPP_F21", "EMMC_RCLK", "n/a", "n/a", - "GPP_F22", "EMMC_CLK", "n/a", "n/a", - "GPP_F23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_f = { - .display = "------- GPIO Group GPP_F -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_f_names, -}; - -static const char *const sunrise_group_g_names[] = { - "GPP_G0", "FAN_TACH_0", "n/a", "n/a", - "GPP_G1", "FAN_TACH_1", "n/a", "n/a", - "GPP_G2", "FAN_TACH_2", "n/a", "n/a", - "GPP_G3", "FAN_TACH_3", "n/a", "n/a", - "GPP_G4", "FAN_TACH_4", "n/a", "n/a", - "GPP_G5", "FAN_TACH_5", "n/a", "n/a", - "GPP_G6", "FAN_TACH_6", "n/a", "n/a", - "GPP_G7", "FAN_TACH_7", "n/a", "n/a", - "GPP_G8", "FAN_PWM_0", "n/a", "n/a", - "GPP_G9", "FAN_PWM_1", "n/a", "n/a", - "GPP_G10", "FAN_PWM_2", "n/a", "n/a", - "GPP_G11", "FAN_PWM_3", "n/a", "n/a", - "GPP_G12", "GSXDOUT", "n/a", "n/a", - "GPP_G13", "GSXSLOAD", "n/a", "n/a", - "GPP_G14", "GSXDIN", "n/a", "n/a", - "GPP_G15", "GSXRESET#", "n/a", "n/a", - "GPP_G16", "GSXCLK", "n/a", "n/a", - "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", - "GPP_G18", "NMI#", "n/a", "n/a", - "GPP_G19", "SMI#", "n/a", "n/a", - "GPP_G20", "n/a", "n/a", "n/a", - "GPP_G21", "n/a", "n/a", "n/a", - "GPP_G22", "n/a", "n/a", "n/a", - "GPP_G23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_g_names, -}; - -static const char *const sunrise_lp_group_g_names[] = { - "GPP_G0", "SD_CMD", "n/a", "n/a", - "GPP_G1", "SD_DATA0", "n/a", "n/a", - "GPP_G2", "SD_DATA1", "n/a", "n/a", - "GPP_G3", "SD_DATA2", "n/a", "n/a", - "GPP_G4", "SD_DATA3", "n/a", "n/a", - "GPP_G5", "SD_CD#", "n/a", "n/a", - "GPP_G6", "SD_CLK", "n/a", "n/a", - "GPP_G7", "SD_WP", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_lp_group_g = { - .display = "------- GPIO Group GPP_G -------", - .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, - .func_count = 4, - .pad_names = sunrise_lp_group_g_names, -}; - -static const char *const sunrise_group_h_names[] = { - "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", - "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", - "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", - "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", - "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", - "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", - "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", - "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", - "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", - "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", - "GPP_H10", "SML2CLK", "n/a", "n/a", - "GPP_H11", "SML2DATA", "n/a", "n/a", - "GPP_H12", "SML2ALERT#", "n/a", "n/a", - "GPP_H13", "SML3CLK", "n/a", "n/a", - "GPP_H14", "SML3DATA", "n/a", "n/a", - "GPP_H15", "SML3ALERT#", "n/a", "n/a", - "GPP_H16", "SML4CLK", "n/a", "n/a", - "GPP_H17", "SML4DATA", "n/a", "n/a", - "GPP_H18", "SML4ALERT#", "n/a", "n/a", - "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", - "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", - "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", - "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", - "GPP_H23", "n/a", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_h = { - .display = "------- GPIO Group GPP_H -------", - .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_h_names, -}; - -static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { - &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, - &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, -}; - -static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { - &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, -}; - -static const struct gpio_community sunrise_community_cdefgh = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), - .groups = sunrise_community_cdefgh_groups, -}; - -static const struct gpio_community sunrise_lp_community_cde = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xae, - .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), - .groups = sunrise_lp_community_cde_groups, -}; - -static const char *const sunrise_group_gpd_names[] = { - "GPD0", "BATLOW#", "n/a", "n/a", - "GPD1", "ACPRESENT", "n/a", "n/a", - "GPD2", "LAN_WAKE#", "n/a", "n/a", - "GPD3", "PWRBTN#", "n/a", "n/a", - "GPD4", "SLP_S3#", "n/a", "n/a", - "GPD5", "SLP_S4#", "n/a", "n/a", - "GPD6", "SLP_A#", "n/a", "n/a", - "GPD7", "RESERVED", "n/a", "n/a", - "GPD8", "SUSCLK", "n/a", "n/a", - "GPD9", "SLP_WLAN#", "n/a", "n/a", - "GPD10", "SLP_S5#", "n/a", "n/a", - "GPD11", "LANPHYPC", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_gpd = { - .display = "-------- GPIO Group GPD --------", - .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_gpd_names, -}; - -static const struct gpio_group *const sunrise_community_gpd_groups[] = { - &sunrise_group_gpd, -}; - -static const struct gpio_community sunrise_community_gpd = { - .name = "------- GPIO Community 2 -------", - .pcr_port_id = 0xad, - .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), - .groups = sunrise_community_gpd_groups, -}; - -static const char *const sunrise_group_i_names[] = { - "GPP_I0", "DDPB_HPD0", "n/a", "n/a", - "GPP_I1", "DDPC_HPD1", "n/a", "n/a", - "GPP_I2", "DDPD_HPD2", "n/a", "n/a", - "GPP_I3", "DDPE_HPD3", "n/a", "n/a", - "GPP_I4", "EDP_HPD", "n/a", "n/a", - "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", - "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", - "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", - "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", - "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", - "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", -}; - -static const struct gpio_group sunrise_group_i = { - .display = "------- GPIO Group GPP_I -------", - .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, - .func_count = 4, - .pad_names = sunrise_group_i_names, -}; - -static const struct gpio_group *const sunrise_community_i_groups[] = { - &sunrise_group_i, -}; - -static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { - &sunrise_lp_group_f, &sunrise_lp_group_g, -}; - -static const struct gpio_community sunrise_community_i = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_community_i_groups), - .groups = sunrise_community_i_groups, -}; - -static const struct gpio_community sunrise_lp_community_fg = { - .name = "------- GPIO Community 3 -------", - .pcr_port_id = 0xac, - .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), - .groups = sunrise_lp_community_fg_groups, -}; - -static const struct gpio_community *const sunrise_communities[] = { - &sunrise_community_ab, &sunrise_community_cdefgh, - &sunrise_community_gpd, &sunrise_community_i, -}; - -static const struct gpio_community *const sunrise_lp_communities[] = { - &sunrise_lp_community_ab, &sunrise_lp_community_cde, - &sunrise_community_gpd, &sunrise_lp_community_fg, -}; - -static const char *const denverton_group_north_all_names[] = { - "NORTH_ALL_GBE0_SDP0", - "NORTH_ALL_GBE1_SDP0", - "NORTH_ALL_GBE0_SDP1", - "NORTH_ALL_GBE1_SDP1", - "NORTH_ALL_GBE0_SDP2", - "NORTH_ALL_GBE1_SDP2", - "NORTH_ALL_GBE0_SDP3", - "NORTH_ALL_GBE1_SDP3", - "NORTH_ALL_GBE2_LED0", - "NORTH_ALL_GBE2_LED1", - "NORTH_ALL_GBE0_I2C_CLK", - "NORTH_ALL_GBE0_I2C_DATA", - "NORTH_ALL_GBE1_I2C_CLK", - "NORTH_ALL_GBE1_I2C_DATA", - "NORTH_ALL_NCSI_RXD0", - "NORTH_ALL_NCSI_CLK_IN", - "NORTH_ALL_NCSI_RXD1", - "NORTH_ALL_NCSI_CRS_DV", - "NORTH_ALL_NCSI_ARB_IN", - "NORTH_ALL_NCSI_TX_EN", - "NORTH_ALL_NCSI_TXD0", - "NORTH_ALL_NCSI_TXD1", - "NORTH_ALL_NCSI_ARB_OUT", - "NORTH_ALL_GBE0_LED0", - "NORTH_ALL_GBE0_LED1", - "NORTH_ALL_GBE1_LED0", - "NORTH_ALL_GBE1_LED1", - "NORTH_ALL_GPIO_0", - "NORTH_ALL_PCIE_CLKREQ0_N", - "NORTH_ALL_PCIE_CLKREQ1_N", - "NORTH_ALL_PCIE_CLKREQ2_N", - "NORTH_ALL_PCIE_CLKREQ3_N", - "NORTH_ALL_PCIE_CLKREQ4_N", - "NORTH_ALL_GPIO_1", - "NORTH_ALL_GPIO_2", - "NORTH_ALL_SVID_ALERT_N", - "NORTH_ALL_SVID_DATA", - "NORTH_ALL_SVID_CLK", - "NORTH_ALL_THERMTRIP_N", - "NORTH_ALL_PROCHOT_N", - "NORTH_ALL_MEMHOT_N", -}; - -static const struct gpio_group denverton_group_north_all = { - .display = "------- GPIO Group North All -------", - .pad_count = ARRAY_SIZE(denverton_group_north_all_names) / 1, - .func_count = 1, - .pad_names = denverton_group_north_all_names, -}; - -static const struct gpio_group *const denverton_community_north_groups[] = { - &denverton_group_north_all, -}; - -static const struct gpio_community denverton_community_north = { - .name = "------- GPIO Community 0 -------", - .pcr_port_id = 0xc2, - .group_count = ARRAY_SIZE(denverton_community_north_groups), - .groups = denverton_community_north_groups, -}; - -static const char *const denverton_group_south_dfx_names[] = { - "SOUTH_DFX_DFX_PORT_CLK0", - "SOUTH_DFX_DFX_PORT_CLK1", - "SOUTH_DFX_DFX_PORT0", - "SOUTH_DFX_DFX_PORT1", - "SOUTH_DFX_DFX_PORT2", - "SOUTH_DFX_DFX_PORT3", - "SOUTH_DFX_DFX_PORT4", - "SOUTH_DFX_DFX_PORT5", - "SOUTH_DFX_DFX_PORT6", - "SOUTH_DFX_DFX_PORT7", - "SOUTH_DFX_DFX_PORT8", - "SOUTH_DFX_DFX_PORT9", - "SOUTH_DFX_DFX_PORT10", - "SOUTH_DFX_DFX_PORT11", - "SOUTH_DFX_DFX_PORT12", - "SOUTH_DFX_DFX_PORT13", - "SOUTH_DFX_DFX_PORT14", - "SOUTH_DFX_DFX_PORT15", -}; - -static const struct gpio_group denverton_group_south_dfx = { - .display = "------- GPIO Group South DFX -------", - .pad_count = ARRAY_SIZE(denverton_group_south_dfx_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_dfx_names, -}; - -static const char *const denverton_group_south_group0_names[] = { - "SOUTH_GROUP0_GPIO_12", - "SOUTH_GROUP0_SMB5_GBE_ALRT_N", - "SOUTH_GROUP0_PCIE_CLKREQ5_N", - "SOUTH_GROUP0_PCIE_CLKREQ6_N", - "SOUTH_GROUP0_PCIE_CLKREQ7_N", - "SOUTH_GROUP0_UART0_RXD", - "SOUTH_GROUP0_UART0_TXD", - "SOUTH_GROUP0_SMB5_GBE_CLK", - "SOUTH_GROUP0_SMB5_GBE_DATA", - "SOUTH_GROUP0_ERROR2_N", - "SOUTH_GROUP0_ERROR1_N", - "SOUTH_GROUP0_ERROR0_N", - "SOUTH_GROUP0_IERR_N", - "SOUTH_GROUP0_MCERR_N", - "SOUTH_GROUP0_SMB0_LEG_CLK", - "SOUTH_GROUP0_SMB0_LEG_DATA", - "SOUTH_GROUP0_SMB0_LEG_ALRT_N", - "SOUTH_GROUP0_SMB1_HOST_DATA", - "SOUTH_GROUP0_SMB1_HOST_CLK", - "SOUTH_GROUP0_SMB2_PECI_DATA", - "SOUTH_GROUP0_SMB2_PECI_CLK", - "SOUTH_GROUP0_SMB4_CSME0_DATA", - "SOUTH_GROUP0_SMB4_CSME0_CLK", - "SOUTH_GROUP0_SMB4_CSME0_ALRT_N", - "SOUTH_GROUP0_USB_OC0_N", - "SOUTH_GROUP0_FLEX_CLK_SE0", - "SOUTH_GROUP0_FLEX_CLK_SE1", - "SOUTH_GROUP0_GPIO_4", - "SOUTH_GROUP0_GPIO_5", - "SOUTH_GROUP0_GPIO_6", - "SOUTH_GROUP0_GPIO_7", - "SOUTH_GROUP0_SATA0_LED_N", - "SOUTH_GROUP0_SATA1_LED_N", - "SOUTH_GROUP0_SATA_PDETECT0", - "SOUTH_GROUP0_SATA_PDETECT1", - "SOUTH_GROUP0_SATA0_SDOUT", - "SOUTH_GROUP0_SATA1_SDOUT", - "SOUTH_GROUP0_UART1_RXD", - "SOUTH_GROUP0_UART1_TXD", - "SOUTH_GROUP0_GPIO_8", - "SOUTH_GROUP0_GPIO_9", - "SOUTH_GROUP0_TCK", - "SOUTH_GROUP0_TRST_N", - "SOUTH_GROUP0_TMS", - "SOUTH_GROUP0_TDI", - "SOUTH_GROUP0_TDO", - "SOUTH_GROUP0_CX_PRDY_N", - "SOUTH_GROUP0_CX_PREQ_N", - "SOUTH_GROUP0_CTBTRIGINOUT", - "SOUTH_GROUP0_CTBTRIGOUT", - "SOUTH_GROUP0_DFX_SPARE2", - "SOUTH_GROUP0_DFX_SPARE3", - "SOUTH_GROUP0_DFX_SPARE4", -}; - -static const struct gpio_group denverton_group_south_group0 = { - .display = "------- GPIO Group South Group0 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group0_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group0_names, -}; - -static const char *const denverton_group_south_group1_names[] = { - "SOUTH_GROUP1_SUSPWRDNACK", - "SOUTH_GROUP1_PMU_SUSCLK", - "SOUTH_GROUP1_ADR_TRIGGER", - "SOUTH_GROUP1_PMU_SLP_S45_N", - "SOUTH_GROUP1_PMU_SLP_S3_N", - "SOUTH_GROUP1_PMU_WAKE_N", - "SOUTH_GROUP1_PMU_PWRBTN_N", - "SOUTH_GROUP1_PMU_RESETBUTTON_N", - "SOUTH_GROUP1_PMU_PLTRST_N", - "SOUTH_GROUP1_SUS_STAT_N", - "SOUTH_GROUP1_SLP_S0IX_N", - "SOUTH_GROUP1_SPI_CS0_N", - "SOUTH_GROUP1_SPI_CS1_N", - "SOUTH_GROUP1_SPI_MOSI_IO0", - "SOUTH_GROUP1_SPI_MISO_IO1", - "SOUTH_GROUP1_SPI_IO2", - "SOUTH_GROUP1_SPI_IO3", - "SOUTH_GROUP1_SPI_CLK", - "SOUTH_GROUP1_SPI_CLK_LOOPBK", - "SOUTH_GROUP1_ESPI_IO0", - "SOUTH_GROUP1_ESPI_IO1", - "SOUTH_GROUP1_ESPI_IO2", - "SOUTH_GROUP1_ESPI_IO3", - "SOUTH_GROUP1_ESPI_CS0_N", - "SOUTH_GROUP1_ESPI_CLK", - "SOUTH_GROUP1_ESPI_RST_N", - "SOUTH_GROUP1_ESPI_ALRT0_N", - "SOUTH_GROUP1_GPIO_10", - "SOUTH_GROUP1_GPIO_11", - "SOUTH_GROUP1_ESPI_CLK_LOOPBK", - "SOUTH_GROUP1_EMMC_CMD", - "SOUTH_GROUP1_EMMC_STROBE", - "SOUTH_GROUP1_EMMC_CLK", - "SOUTH_GROUP1_EMMC_D0", - "SOUTH_GROUP1_EMMC_D1", - "SOUTH_GROUP1_EMMC_D2", - "SOUTH_GROUP1_EMMC_D3", - "SOUTH_GROUP1_EMMC_D4", - "SOUTH_GROUP1_EMMC_D5", - "SOUTH_GROUP1_EMMC_D6", - "SOUTH_GROUP1_EMMC_D7", - "SOUTH_GROUP1_GPIO_3", -}; - -static const struct gpio_group denverton_group_south_group1 = { - .display = "------- GPIO Group South Group1 -------", - .pad_count = ARRAY_SIZE(denverton_group_south_group1_names) / 1, - .func_count = 1, - .pad_names = denverton_group_south_group1_names, -}; - -static const struct gpio_group *const denverton_community_south_groups[] = { - &denverton_group_south_dfx, - &denverton_group_south_group0, - &denverton_group_south_group1, -}; - -static const struct gpio_community denverton_community_south = { - .name = "------- GPIO Community 1 -------", - .pcr_port_id = 0xc5, - .group_count = ARRAY_SIZE(denverton_community_south_groups), - .groups = denverton_community_south_groups, -}; - -static const struct gpio_community *const denverton_communities[] = { - &denverton_community_north, &denverton_community_south, -}; - static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) { diff --git a/util/inteltool/gpio_sunrise.h b/util/inteltool/gpio_sunrise.h new file mode 100644 index 0000000..5553b7d --- /dev/null +++ b/util/inteltool/gpio_sunrise.h @@ -0,0 +1,595 @@ +/* + * inteltool - dump all registers on an Intel CPU + chipset based system. + * + * Copyright (C) 2017 secunet Security Networks AG + * Copyright (C) 2019 Felix Singer <migy(a)darmstadt.ccc.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const char *const sunrise_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "ESPI_ALERT1#", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "ESPI_CS1#", + "GPP_A7", "PIRQA#", "n/a", "ESPI_ALERT0#", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "CLKOUT_48", "n/a", "n/a", + "GPP_A17", "ISH_GP7", "n/a", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_a_names, +}; + +static const char *const sunrise_lp_group_a_names[] = { + "GPP_A0", "RCIN#", "n/a", "n/a", + "GPP_A1", "LAD0", "n/a", "ESPI_IO0", + "GPP_A2", "LAD1", "n/a", "ESPI_IO1", + "GPP_A3", "LAD2", "n/a", "ESPI_IO2", + "GPP_A4", "LAD3", "n/a", "ESPI_IO3", + "GPP_A5", "LFRAME#", "n/a", "ESPI_CS#", + "GPP_A6", "SERIRQ", "n/a", "n/a", + "GPP_A7", "PIRQA#", "n/a", "n/a", + "GPP_A8", "CLKRUN#", "n/a", "n/a", + "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", + "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", + "GPP_A11", "PME#", "n/a", "n/a", + "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", + "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", + "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", + "GPP_A15", "SUS_ACK#", "n/a", "n/a", + "GPP_A16", "SD_1P8_SEL", "n/a", "n/a", + "GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a", + "GPP_A18", "ISH_GP0", "n/a", "n/a", + "GPP_A19", "ISH_GP1", "n/a", "n/a", + "GPP_A20", "ISH_GP2", "n/a", "n/a", + "GPP_A21", "ISH_GP3", "n/a", "n/a", + "GPP_A22", "ISH_GP4", "n/a", "n/a", + "GPP_A23", "ISH_GP5", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_a = { + .display = "------- GPIO group GPP_A -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_a_names, +}; + +static const char *const sunrise_group_b_names[] = { + "GPP_B0", "n/a", "n/a", "n/a", + "GPP_B1", "n/a", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "n/a", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPIO_CS#", "n/a", "n/a", + "GPP_B16", "GSPIO_CLK", "n/a", "n/a", + "GPP_B17", "GSPIO_MISO", "n/a", "n/a", + "GPP_B18", "GSPIO_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_b_names, +}; + +static const char *const sunrise_lp_group_b_names[] = { + "GPP_B0", "CORE_VID0", "n/a", "n/a", + "GPP_B1", "CORE_VID1", "n/a", "n/a", + "GPP_B2", "VRALERT#", "n/a", "n/a", + "GPP_B3", "CPU_GP2", "n/a", "n/a", + "GPP_B4", "CPU_GP3", "n/a", "n/a", + "GPP_B5", "SRCCLKREQ0#", "n/a", "n/a", + "GPP_B6", "SRCCLKREQ1#", "n/a", "n/a", + "GPP_B7", "SRCCLKREQ2#", "n/a", "n/a", + "GPP_B8", "SRCCLKREQ3#", "n/a", "n/a", + "GPP_B9", "SRCCLKREQ4#", "n/a", "n/a", + "GPP_B10", "SRCCLKREQ5#", "n/a", "n/a", + "GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a", + "GPP_B12", "SLP_S0#", "n/a", "n/a", + "GPP_B13", "PLTRST#", "n/a", "n/a", + "GPP_B14", "SPKR", "n/a", "n/a", + "GPP_B15", "GSPI0_CS#", "n/a", "n/a", + "GPP_B16", "GSPI0_CLK", "n/a", "n/a", + "GPP_B17", "GSPI0_MISO", "n/a", "n/a", + "GPP_B18", "GSPI0_MOSI", "n/a", "n/a", + "GPP_B19", "GSPI1_CS#", "n/a", "n/a", + "GPP_B20", "GSPI1_CLK", "n/a", "n/a", + "GPP_B21", "GSPI1_MISO", "n/a", "n/a", + "GPP_B22", "GSPI1_MOSI", "n/a", "n/a", + "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_b_names, +}; + +static const struct gpio_group *const sunrise_community_ab_groups[] = { + &sunrise_group_a, &sunrise_group_b, +}; + +static const struct gpio_group *const sunrise_lp_community_ab_groups[] = { + &sunrise_lp_group_a, &sunrise_lp_group_b, +}; + +static const struct gpio_community sunrise_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_community_ab_groups), + .groups = sunrise_community_ab_groups, +}; + +static const struct gpio_community sunrise_lp_community_ab = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0xaf, + .group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups), + .groups = sunrise_lp_community_ab_groups, +}; + +static const char *const sunrise_group_c_names[] = { + "GPP_C0", "SMBCLK", "n/a", "n/a", + "GPP_C1", "SMBDATA", "n/a", "n/a", + "GPP_C2", "SMBALERT#", "n/a", "n/a", + "GPP_C3", "SML0CLK", "n/a", "n/a", + "GPP_C4", "SML0DATA", "n/a", "n/a", + "GPP_C5", "SML0ALERT#", "n/a", "n/a", + "GPP_C6", "SML1CLK", "n/a", "n/a", + "GPP_C7", "SML1DATA", "n/a", "n/a", + "GPP_C8", "UART0_RXD", "n/a", "n/a", + "GPP_C9", "UART0_TXD", "n/a", "n/a", + "GPP_C10", "UART0_RTS#", "n/a", "n/a", + "GPP_C11", "UART0_CTS#", "n/a", "n/a", + "GPP_C12", "UART1_RXD", "ISH_UART1_RXD", "n/a", + "GPP_C13", "UART1_TXD", "ISH_UART1_TXD", "n/a", + "GPP_C14", "UART1_RTS#", "ISH_UART1_RTS#", "n/a", + "GPP_C15", "UART1_CTS#", "ISH_UART1_CTS#", "n/a", + "GPP_C16", "I2C0_SDA", "n/a", "n/a", + "GPP_C17", "I2C0_SCL", "n/a", "n/a", + "GPP_C18", "I2C1_SDA", "n/a", "n/a", + "GPP_C19", "I2C1_SCL", "n/a", "n/a", + "GPP_C20", "UART2_RXD", "n/a", "n/a", + "GPP_C21", "UART2_TXD", "n/a", "n/a", + "GPP_C22", "UART2_RTS#", "n/a", "n/a", + "GPP_C23", "UART2_CTS#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(sunrise_group_c_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_c_names, +}; + +static const char *const sunrise_group_d_names[] = { + "GPP_D0", "n/a", "n/a", "n/a", + "GPP_D1", "n/a", "n/a", "n/a", + "GPP_D2", "n/a", "n/a", "n/a", + "GPP_D3", "n/a", "n/a", "n/a", + "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a", + "GPP_D5", "I2S_SFRM", "n/a", "n/a", + "GPP_D6", "I2S_TXD", "n/a", "n/a", + "GPP_D7", "I2S_RXD", "n/a", "n/a", + "GPP_D8", "I2S_SCLK", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "I2C2_SDA", + "GPP_D14", "ISH_UART0_TXD", "n/a", "I2C2_SCL", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "n/a", "n/a", "n/a", + "GPP_D22", "n/a", "n/a", "n/a", + "GPP_D23", "ISH_I2C2_SCL", "I2C3_SCL", "n/a", +}; + +static const struct gpio_group sunrise_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_d_names, +}; + +static const char *const sunrise_lp_group_d_names[] = { + "GPP_D0", "SPI1_CS#", "n/a", "n/a", + "GPP_D1", "SPI1_CLK", "n/a", "n/a", + "GPP_D2", "SPI1_MISO", "n/a", "n/a", + "GPP_D3", "SPI1_MOSI", "n/a", "n/a", + "GPP_D4", "FLASHTRIG", "n/a", "n/a", + "GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_D9", "n/a", "n/a", "n/a", + "GPP_D10", "n/a", "n/a", "n/a", + "GPP_D11", "n/a", "n/a", "n/a", + "GPP_D12", "n/a", "n/a", "n/a", + "GPP_D13", "ISH_UART0_RXD", "n/a", "n/a", + "GPP_D14", "ISH_UART0_TXD", "n/a", "n/a", + "GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a", + "GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a", + "GPP_D17", "DMIC_CLK1", "n/a", "n/a", + "GPP_D18", "DMIC_DATA1", "n/a", "n/a", + "GPP_D19", "DMIC_CLK0", "n/a", "n/a", + "GPP_D20", "DMIC_DATA0", "n/a", "n/a", + "GPP_D21", "SPI1_IO2", "n/a", "n/a", + "GPP_D22", "SPI1_IO3", "n/a", "n/a", + "GPP_D23", "I2S_MCLK", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_d_names, +}; + +static const char *const sunrise_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATA_LED#", "n/a", "n/a", + "GPP_E9", "USB_OC0#", "n/a", "n/a", + "GPP_E10", "USB_OC1#", "n/a", "n/a", + "GPP_E11", "USB_OC2#", "n/a", "n/a", + "GPP_E12", "USB_OC3#", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_e_names, +}; + +static const char *const sunrise_lp_group_e_names[] = { + "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", + "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", + "GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a", + "GPP_E3", "CPU_GP0", "n/a", "n/a", + "GPP_E4", "SATA_DEVSLP0", "n/a", "n/a", + "GPP_E5", "SATA_DEVSLP1", "n/a", "n/a", + "GPP_E6", "SATA_DEVSLP2", "n/a", "n/a", + "GPP_E7", "CPU_GP1", "n/a", "n/a", + "GPP_E8", "SATALED#", "n/a", "n/a", + "GPP_E9", "USB2_OC0#", "n/a", "n/a", + "GPP_E10", "USB2_OC1#", "n/a", "n/a", + "GPP_E11", "USB2_OC2#", "n/a", "n/a", + "GPP_E12", "USB2_OC3#", "n/a", "n/a", + "GPP_E13", "DDPB_HPD0", "n/a", "n/a", + "GPP_E14", "DDPC_HPD1", "n/a", "n/a", + "GPP_E15", "DDPD_HPD2", "n/a", "n/a", + "GPP_E16", "DDPE_HPD3", "n/a", "n/a", + "GPP_E17", "EDP_HPD", "n/a", "n/a", + "GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_E22", "n/a", "n/a", "n/a", + "GPP_E23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_e = { + .display = "------- GPIO Group GPP_E -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_e_names, +}; + +static const char *const sunrise_group_f_names[] = { + "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", + "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", + "GPP_F2", "SATAXPCIE5", "SATAGP5", "n/a", + "GPP_F3", "SATAXPCIE6", "SATAGP6", "n/a", + "GPP_F4", "SATAXPCIE7", "SATAGP7", "n/a", + "GPP_F5", "SATA_DEVSLP3", "n/a", "n/a", + "GPP_F6", "SATA_DEVSLP4", "n/a", "n/a", + "GPP_F7", "SATA_DEVSLP5", "n/a", "n/a", + "GPP_F8", "SATA_DEVSLP6", "n/a", "n/a", + "GPP_F9", "SATA_DEVSLP7", "n/a", "n/a", + "GPP_F10", "SATA_SCLOCK", "n/a", "n/a", + "GPP_F11", "SATA_SLOAD", "n/a", "n/a", + "GPP_F12", "SATA_SDATAOUT1", "n/a", "n/a", + "GPP_F13", "SATA_SDATAOUT2", "n/a", "n/a", + "GPP_F14", "n/a", "n/a", "n/a", + "GPP_F15", "USB_OC4#", "n/a", "n/a", + "GPP_F16", "USB_OC5#", "n/a", "n/a", + "GPP_F17", "USB_OC6#", "n/a", "n/a", + "GPP_F18", "USB_OC7#", "n/a", "n/a", + "GPP_F19", "eDP_VDDEN", "n/a", "n/a", + "GPP_F20", "eDP_BKLTEN", "n/a", "n/a", + "GPP_F21", "eDP_BKLTCTL", "n/a", "n/a", + "GPP_F22", "n/a", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_f_names, +}; + +static const char *const sunrise_lp_group_f_names[] = { + "GPP_F0", "I2S2_SCLK", "n/a", "n/a", + "GPP_F1", "I2S2_SFRM", "n/a", "n/a", + "GPP_F2", "I2S2_TXD", "n/a", "n/a", + "GPP_F3", "I2S2_RXD", "n/a", "n/a", + "GPP_F4", "I2C2_SDA", "n/a", "n/a", + "GPP_F5", "I2C2_SCL", "n/a", "n/a", + "GPP_F6", "I2C3_SDA", "n/a", "n/a", + "GPP_F7", "I2C3_SCL", "n/a", "n/a", + "GPP_F8", "I2C4_SDA", "n/a", "n/a", + "GPP_F9", "I2C4_SCL", "n/a", "n/a", + "GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a", + "GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a", + "GPP_F12", "EMMC_CMD", "n/a", "n/a", + "GPP_F13", "EMMC_DATA0", "n/a", "n/a", + "GPP_F14", "EMMC_DATA1", "n/a", "n/a", + "GPP_F15", "EMMC_DATA2", "n/a", "n/a", + "GPP_F16", "EMMC_DATA3", "n/a", "n/a", + "GPP_F17", "EMMC_DATA4", "n/a", "n/a", + "GPP_F18", "EMMC_DATA5", "n/a", "n/a", + "GPP_F19", "EMMC_DATA6", "n/a", "n/a", + "GPP_F20", "EMMC_DATA7", "n/a", "n/a", + "GPP_F21", "EMMC_RCLK", "n/a", "n/a", + "GPP_F22", "EMMC_CLK", "n/a", "n/a", + "GPP_F23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_f_names, +}; + +static const char *const sunrise_group_g_names[] = { + "GPP_G0", "FAN_TACH_0", "n/a", "n/a", + "GPP_G1", "FAN_TACH_1", "n/a", "n/a", + "GPP_G2", "FAN_TACH_2", "n/a", "n/a", + "GPP_G3", "FAN_TACH_3", "n/a", "n/a", + "GPP_G4", "FAN_TACH_4", "n/a", "n/a", + "GPP_G5", "FAN_TACH_5", "n/a", "n/a", + "GPP_G6", "FAN_TACH_6", "n/a", "n/a", + "GPP_G7", "FAN_TACH_7", "n/a", "n/a", + "GPP_G8", "FAN_PWM_0", "n/a", "n/a", + "GPP_G9", "FAN_PWM_1", "n/a", "n/a", + "GPP_G10", "FAN_PWM_2", "n/a", "n/a", + "GPP_G11", "FAN_PWM_3", "n/a", "n/a", + "GPP_G12", "GSXDOUT", "n/a", "n/a", + "GPP_G13", "GSXSLOAD", "n/a", "n/a", + "GPP_G14", "GSXDIN", "n/a", "n/a", + "GPP_G15", "GSXRESET#", "n/a", "n/a", + "GPP_G16", "GSXCLK", "n/a", "n/a", + "GPP_G17", "ADR_COMPLETE", "n/a", "n/a", + "GPP_G18", "NMI#", "n/a", "n/a", + "GPP_G19", "SMI#", "n/a", "n/a", + "GPP_G20", "n/a", "n/a", "n/a", + "GPP_G21", "n/a", "n/a", "n/a", + "GPP_G22", "n/a", "n/a", "n/a", + "GPP_G23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_g_names, +}; + +static const char *const sunrise_lp_group_g_names[] = { + "GPP_G0", "SD_CMD", "n/a", "n/a", + "GPP_G1", "SD_DATA0", "n/a", "n/a", + "GPP_G2", "SD_DATA1", "n/a", "n/a", + "GPP_G3", "SD_DATA2", "n/a", "n/a", + "GPP_G4", "SD_DATA3", "n/a", "n/a", + "GPP_G5", "SD_CD#", "n/a", "n/a", + "GPP_G6", "SD_CLK", "n/a", "n/a", + "GPP_G7", "SD_WP", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_lp_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4, + .func_count = 4, + .pad_names = sunrise_lp_group_g_names, +}; + +static const char *const sunrise_group_h_names[] = { + "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", + "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", + "GPP_H2", "SRCCLKREQ8#", "n/a", "n/a", + "GPP_H3", "SRCCLKREQ9#", "n/a", "n/a", + "GPP_H4", "SRCCLKREQ10#", "n/a", "n/a", + "GPP_H5", "SRCCLKREQ11#", "n/a", "n/a", + "GPP_H6", "SRCCLKREQ12#", "n/a", "n/a", + "GPP_H7", "SRCCLKREQ13#", "n/a", "n/a", + "GPP_H8", "SRCCLKREQ14#", "n/a", "n/a", + "GPP_H9", "SRCCLKREQ15#", "n/a", "n/a", + "GPP_H10", "SML2CLK", "n/a", "n/a", + "GPP_H11", "SML2DATA", "n/a", "n/a", + "GPP_H12", "SML2ALERT#", "n/a", "n/a", + "GPP_H13", "SML3CLK", "n/a", "n/a", + "GPP_H14", "SML3DATA", "n/a", "n/a", + "GPP_H15", "SML3ALERT#", "n/a", "n/a", + "GPP_H16", "SML4CLK", "n/a", "n/a", + "GPP_H17", "SML4DATA", "n/a", "n/a", + "GPP_H18", "SML4ALERT#", "n/a", "n/a", + "GPP_H19", "ISH_I2C0_SDA", "n/a", "n/a", + "GPP_H20", "ISH_I2C0_SCL", "n/a", "n/a", + "GPP_H21", "ISH_I2C1_SDA", "n/a", "n/a", + "GPP_H22", "ISH_I2C1_SCL", "n/a", "n/a", + "GPP_H23", "n/a", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(sunrise_group_h_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_h_names, +}; + +static const struct gpio_group *const sunrise_community_cdefgh_groups[] = { + &sunrise_group_c, &sunrise_group_d, &sunrise_group_e, + &sunrise_group_f, &sunrise_group_g, &sunrise_group_h, +}; + +static const struct gpio_group *const sunrise_lp_community_cde_groups[] = { + &sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e, +}; + +static const struct gpio_community sunrise_community_cdefgh = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_community_cdefgh_groups), + .groups = sunrise_community_cdefgh_groups, +}; + +static const struct gpio_community sunrise_lp_community_cde = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0xae, + .group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups), + .groups = sunrise_lp_community_cde_groups, +}; + +static const char *const sunrise_group_gpd_names[] = { + "GPD0", "BATLOW#", "n/a", "n/a", + "GPD1", "ACPRESENT", "n/a", "n/a", + "GPD2", "LAN_WAKE#", "n/a", "n/a", + "GPD3", "PWRBTN#", "n/a", "n/a", + "GPD4", "SLP_S3#", "n/a", "n/a", + "GPD5", "SLP_S4#", "n/a", "n/a", + "GPD6", "SLP_A#", "n/a", "n/a", + "GPD7", "RESERVED", "n/a", "n/a", + "GPD8", "SUSCLK", "n/a", "n/a", + "GPD9", "SLP_WLAN#", "n/a", "n/a", + "GPD10", "SLP_S5#", "n/a", "n/a", + "GPD11", "LANPHYPC", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_gpd = { + .display = "-------- GPIO Group GPD --------", + .pad_count = ARRAY_SIZE(sunrise_group_gpd_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_gpd_names, +}; + +static const struct gpio_group *const sunrise_community_gpd_groups[] = { + &sunrise_group_gpd, +}; + +static const struct gpio_community sunrise_community_gpd = { + .name = "------- GPIO Community 2 -------", + .pcr_port_id = 0xad, + .group_count = ARRAY_SIZE(sunrise_community_gpd_groups), + .groups = sunrise_community_gpd_groups, +}; + +static const char *const sunrise_group_i_names[] = { + "GPP_I0", "DDPB_HPD0", "n/a", "n/a", + "GPP_I1", "DDPC_HPD1", "n/a", "n/a", + "GPP_I2", "DDPD_HPD2", "n/a", "n/a", + "GPP_I3", "DDPE_HPD3", "n/a", "n/a", + "GPP_I4", "EDP_HPD", "n/a", "n/a", + "GPP_I5", "DDPB_CTRLCLK", "n/a", "n/a", + "GPP_I6", "DDPB_CTRLDATA", "n/a", "n/a", + "GPP_I7", "DDPC_CTRLCLK", "n/a", "n/a", + "GPP_I8", "DDPC_CTRLDATA", "n/a", "n/a", + "GPP_I9", "DDPD_CTRLCLK", "n/a", "n/a", + "GPP_I10", "DDPD_CTRLDATA", "n/a", "n/a", +}; + +static const struct gpio_group sunrise_group_i = { + .display = "------- GPIO Group GPP_I -------", + .pad_count = ARRAY_SIZE(sunrise_group_i_names) / 4, + .func_count = 4, + .pad_names = sunrise_group_i_names, +}; + +static const struct gpio_group *const sunrise_community_i_groups[] = { + &sunrise_group_i, +}; + +static const struct gpio_group *const sunrise_lp_community_fg_groups[] = { + &sunrise_lp_group_f, &sunrise_lp_group_g, +}; + +static const struct gpio_community sunrise_community_i = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_community_i_groups), + .groups = sunrise_community_i_groups, +}; + +static const struct gpio_community sunrise_lp_community_fg = { + .name = "------- GPIO Community 3 -------", + .pcr_port_id = 0xac, + .group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups), + .groups = sunrise_lp_community_fg_groups, +}; + +static const struct gpio_community *const sunrise_communities[] = { + &sunrise_community_ab, &sunrise_community_cdefgh, + &sunrise_community_gpd, &sunrise_community_i, +}; + +static const struct gpio_community *const sunrise_lp_communities[] = { + &sunrise_lp_community_ab, &sunrise_lp_community_cde, + &sunrise_community_gpd, &sunrise_lp_community_fg, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/31504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic61871f5cf95ac3da93892fa2f7721e682176c8d Gerrit-Change-Number: 31504 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

7 34

Change in coreboot[master]: sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM
by Nico Huber (Code Review) 03 Jul '20

03 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35489 ) Change subject: sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM ...................................................................... sb/nvidia/{ck804,mcp55}: Use new device references for MAC EEPROM Instead of using fragile dev_find_slot_on_smbus(), link the devices in the devicetree directly. msi/ms9652 referenced a non-existing device (commented), so remove the reference entirely. Change-Id: I050e681142c5b19f97fec865e887eda157ee830b Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/mainboard/msi/ms9652_fam10/devicetree.cb M src/mainboard/supermicro/h8dmr_fam10/devicetree.cb M src/mainboard/supermicro/h8qme_fam10/devicetree.cb M src/mainboard/tyan/s2912_fam10/devicetree.cb M src/southbridge/nvidia/ck804/chip.h M src/southbridge/nvidia/ck804/nic.c M src/southbridge/nvidia/mcp55/chip.h M src/southbridge/nvidia/mcp55/nic.c 8 files changed, 56 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/35489/1 diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index c6dae6d..1815870 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -149,9 +149,6 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end end device pci 18.0 on end # HT 1.0 diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index ee88c31..89c579e 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -103,7 +103,7 @@ # device i2c 55 on end # end chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device i2c 51 alias mac on end end end device pci 2.0 on end # USB 1.1 @@ -133,9 +133,7 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + use mac as mac_eeprom end end device pci 18.1 on end diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 317d643..de78ce2 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -56,11 +56,8 @@ end device pci 1.1 on end device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device i2c 51 alias mac on end end end device pci 2.0 on end # USB 1.1 @@ -84,9 +81,7 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + use mac as mac_eeprom end end device pci 18.1 on end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index e49e16b..4a4118e 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -103,7 +103,7 @@ # device i2c 55 on end # end chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device i2c 51 alias mac on end end end device pci 2.0 on end # USB 1.1 @@ -127,9 +127,7 @@ register "ide0_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + use mac as mac_eeprom end end device pci 18.1 on end diff --git a/src/southbridge/nvidia/ck804/chip.h b/src/southbridge/nvidia/ck804/chip.h index b1676ce..16fdbde 100644 --- a/src/southbridge/nvidia/ck804/chip.h +++ b/src/southbridge/nvidia/ck804/chip.h @@ -17,14 +17,15 @@ #ifndef SOUTHBRIDGE_NVIDIA_CK804_CHIP_H #define SOUTHBRIDGE_NVIDIA_CK804_CHIP_H +#include <device/device.h> + struct southbridge_nvidia_ck804_config { unsigned int usb1_hc_reset : 1; unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; + DEVTREE_CONST struct device *mac_eeprom; }; extern struct pci_operations ck804_pci_ops; diff --git a/src/southbridge/nvidia/ck804/nic.c b/src/southbridge/nvidia/ck804/nic.c index 5dbb6b4..188dc23 100644 --- a/src/southbridge/nvidia/ck804/nic.c +++ b/src/southbridge/nvidia/ck804/nic.c @@ -47,37 +47,31 @@ conf = dev->chip_info; - if (conf->mac_eeprom_smbus != 0) { + if (conf->mac_eeprom) { /* Read MAC address from EEPROM at first. */ - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, - conf->mac_eeprom_addr); - - if (dev_eeprom) { - /* If that is valid we will use that. */ - unsigned char dat[6]; - int i, status; - for (i = 0; i < 6; i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) - break; - dat[i] = status & 0xff; + /* If that is valid we will use that. */ + unsigned char dat[6]; + int i, status; + for (i = 0; i < 6; i++) { + status = smbus_read_byte(conf->mac_eeprom, i); + if (status < 0) + break; + dat[i] = status & 0xff; + } + if (status >= 0) { + mac_l = 0; + for (i = 3; i >= 0; i--) { + mac_l <<= 8; + mac_l += dat[i]; } - if (status >= 0) { - mac_l = 0; - for (i = 3; i >= 0; i--) { - mac_l <<= 8; - mac_l += dat[i]; + if (mac_l != 0xffffffff) { + mac_l += nic_index; + mac_h = 0; + for (i = 5; i >= 4; i--) { + mac_h <<= 8; + mac_h += dat[i]; } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i = 5; i >= 4; i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } + eeprom_valid = 1; } } } diff --git a/src/southbridge/nvidia/mcp55/chip.h b/src/southbridge/nvidia/mcp55/chip.h index 4bc8428..36eea22 100644 --- a/src/southbridge/nvidia/mcp55/chip.h +++ b/src/southbridge/nvidia/mcp55/chip.h @@ -18,14 +18,15 @@ #ifndef SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H #define SOUTHBRIDGE_NVIDIA_MCP55_CHIP_H +#include <device/device.h> + struct southbridge_nvidia_mcp55_config { unsigned int ide0_enable : 1; unsigned int ide1_enable : 1; unsigned int sata0_enable : 1; unsigned int sata1_enable : 1; - unsigned int mac_eeprom_smbus; - unsigned int mac_eeprom_addr; + DEVTREE_CONST struct device *mac_eeprom; }; #endif diff --git a/src/southbridge/nvidia/mcp55/nic.c b/src/southbridge/nvidia/mcp55/nic.c index af4df44..b562503 100644 --- a/src/southbridge/nvidia/mcp55/nic.c +++ b/src/southbridge/nvidia/mcp55/nic.c @@ -124,36 +124,31 @@ conf = dev->chip_info; - if (conf->mac_eeprom_smbus != 0) { + if (conf->mac_eeprom) { // read MAC address from EEPROM at first - struct device *dev_eeprom; - dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); - - if (dev_eeprom) { - // if that is valid we will use that - unsigned char dat[6]; - int status; - int i; - for (i=0;i<6;i++) { - status = smbus_read_byte(dev_eeprom, i); - if (status < 0) break; - dat[i] = status & 0xff; + // if that is valid we will use that + unsigned char dat[6]; + int status; + int i; + for (i=0;i<6;i++) { + status = smbus_read_byte(conf->mac_eeprom, i); + if (status < 0) break; + dat[i] = status & 0xff; + } + if (status >= 0) { + mac_l = 0; + for (i=3;i>=0;i--) { + mac_l <<= 8; + mac_l += dat[i]; } - if (status >= 0) { - mac_l = 0; - for (i=3;i>=0;i--) { - mac_l <<= 8; - mac_l += dat[i]; + if (mac_l != 0xffffffff) { + mac_l += nic_index; + mac_h = 0; + for (i=5;i>=4;i--) { + mac_h <<= 8; + mac_h += dat[i]; } - if (mac_l != 0xffffffff) { - mac_l += nic_index; - mac_h = 0; - for (i=5;i>=4;i--) { - mac_h <<= 8; - mac_h += dat[i]; - } - eeprom_valid = 1; - } + eeprom_valid = 1; } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/35489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I050e681142c5b19f97fec865e887eda157ee830b Gerrit-Change-Number: 35489 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: crossgcc: Upgrade IASL to version 20200214
by HAOUAS Elyes (Code Review) 01 Jul '20

01 Jul '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38907 ) Change subject: crossgcc: Upgrade IASL to version 20200214 ...................................................................... crossgcc: Upgrade IASL to version 20200214 Change: https://acpica.org/node/177 Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20200214_iasl.patch D util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/38907/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 150e616..b1c930b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,7 +54,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 -IASL_VERSION=20200110 +IASL_VERSION=20200214 PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20200110_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200214_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20200110_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200214_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum deleted file mode 100644 index 48c0a2f..0000000 --- a/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -50c163d965aa2cbee9a3a5d9244d1a0d16c06ec0 tarballs/acpica-unix2-20200110.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum new file mode 100644 index 0000000..97ef41e --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20200214.tar.gz.cksum @@ -0,0 +1 @@ +70f4e47590c82553287b2f301020352c59db7589 tarballs/acpica-unix2-20200214.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/38907 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd995561ca53458b04f87cee5693850c0d90d3d6 Gerrit-Change-Number: 38907 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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