coreboot-gerrit February 2020

coreboot-gerrit@coreboot.org

1 participants
1797 discussions

Change in coreboot[master]: soc/amd/picasso: Add bootram reservations
by Marshall Dawson (Code Review) 18 Jun '20

18 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38702 ) Change subject: soc/amd/picasso: Add bootram reservations ...................................................................... soc/amd/picasso: Add bootram reservations Picasso consumes DRAM to avoid running XIP from the boot flash. This must be reserved from use by the OS. During bootblock, save the region used by the stage (and reserve 0 for verstage). Save romstage's region in romstage. Override the weak bootmem_platform_add_ranges() to retrieve the bases and sizes, then add them as BM_MEM_RESERVED. Note the design of verstage, as it applies to the x86, is T.B.D. The reservation of its bootram should be reevaluated later. Change-Id: I7032117bbf12b845e06df8cfa7a62445e589ecf5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/bootblock/bootblock.c M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/romstage.c 3 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/38702/1 diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c index 00f8416..e845437 100644 --- a/src/soc/amd/picasso/bootblock/bootblock.c +++ b/src/soc/amd/picasso/bootblock/bootblock.c @@ -24,6 +24,7 @@ #include <soc/southbridge.h> #include <soc/i2c.h> #include <amdblocks/amd_pci_mmconf.h> +#include <amdblocks/biosram.h> static void amd_initmmio(void) { @@ -108,4 +109,7 @@ fch_early_init(); i2c_soc_early_init(); + + set_bootram_bootblock((uintptr_t)_bootblock, _ebootblock - _bootblock); + set_bootram_verstage(0, 0); /* TODO: load values once supported */ } diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index c5bd9fa..9d3c98b 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -35,10 +35,29 @@ #include <stdint.h> #include <string.h> #include <arch/bert_storage.h> +#include <bootmem.h> #include <fsp/util.h> #include "chip.h" +void bootmem_platform_add_ranges(void) +{ + uint64_t base; + uint32_t size; + + get_bootram_bootblock(&base, &size); + bootmem_add_range(base, size, BM_MEM_RESERVED); + + get_bootram_verstage(&base, &size); + bootmem_add_range(base, size, BM_MEM_RESERVED); + + get_bootram_romstage(&base, &size); + bootmem_add_range(base, size, BM_MEM_RESERVED); + + get_bootram_fspm(&base, &size); + bootmem_add_range(base, size, BM_MEM_RESERVED); +} + static void read_resources(struct device *dev) { uint32_t mem_usable = (uintptr_t)cbmem_top(); diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index a8651fa..3c2343c 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -28,6 +28,7 @@ #include <symbols.h> #include <elog.h> #include <soc/romstage.h> +#include <amdblocks/biosram.h> #include "chip.h" #include <fsp/api.h> @@ -160,6 +161,11 @@ mainboard_fsp_memory_init_params_cb(mcfg, version); } +void fsp_reserve_fspm_mem(uintptr_t base, size_t size) +{ + set_bootram_fspm(base, (uint32_t)size); +} + asmlinkage void car_stage_entry(void) { int s3_resume; @@ -186,6 +192,9 @@ set_mtrrs_for_ramstage(); post_code(0x46); + set_bootram_romstage((uintptr_t)_romstage, _eromstage - _romstage); + + post_code(0x47); run_ramstage(); post_code(0x50); /* Should never see this post code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7032117bbf12b845e06df8cfa7a62445e589ecf5 Gerrit-Change-Number: 38702 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: drivers/intel/fsp2_0: Add weak reservation for FSP-M memory
by Marshall Dawson (Code Review) 18 Jun '20

18 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38700 ) Change subject: drivers/intel/fsp2_0: Add weak reservation for FSP-M memory ...................................................................... drivers/intel/fsp2_0: Add weak reservation for FSP-M memory The function fsp_memory_init() is capable of executing in place or as non-XIP. For devices starting with DRAM enabled, this option increases performance but requires the memory to be reserved later. Add a weak function so the soc may save the base and size of the memory consumed by FSP-M. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I04b2fff4074b720d1910ff21e1a1f841cfea8efb --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/memory_init.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/38700/1 diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 60adb98..a0366f6 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -50,6 +50,12 @@ void fsp_temp_ram_exit(void); /* + * When fsp_memory_init() runs non-XIP, and if it affects any DRAM, allow + * the soc to note the memory to be reserved. + */ +void fsp_reserve_fspm_mem(uintptr_t base, size_t size); + +/* * Load FSP-S from stage cache or CBFS. This allows SoCs to load FSPS-S * separately from calling silicon init. It might be required in cases where * stage cache is no longer available by the point SoC calls into silicon init. diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 455dfa5..3e9da8e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -42,6 +42,8 @@ CONFIG(VBOOT_STARTS_IN_BOOTBLOCK), "for TPM MRC hash functionality, vboot must start in bootblock"); +__weak void fsp_reserve_fspm_mem(uintptr_t base, size_t size) {} + static void save_memory_training_data(bool s3wake, uint32_t fsp_version) { size_t mrc_data_size; @@ -356,6 +358,8 @@ if (rdev_readat(rdev, (void *)fspm_begin, 0, fspm_end - fspm_begin) < 0) return CB_ERR; + fsp_reserve_fspm_mem(fspm_begin, fspm_end - fspm_begin); + return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/38700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I04b2fff4074b720d1910ff21e1a1f841cfea8efb Gerrit-Change-Number: 38700 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

8 26

Change in coreboot[master]: soc/amd/common/biosram: Add functions to get/set bootram used
by Marshall Dawson (Code Review) 18 Jun '20

18 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38701 ) Change subject: soc/amd/common/biosram: Add functions to get/set bootram used ...................................................................... soc/amd/common/biosram: Add functions to get/set bootram used Designs that use RESET_VECTOR_IN_RAM (typ. AMD Family 17h and later) do not run as XIP from the boot flash device. Stage and other images are loaded to DRAM to improve performance. These regions that are consumed must be reserved, otherwise resuming from S3 will corrupt the OS's memory. Define offsets where the base and size of early stages can be saved and add get/set functions to access them. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I14f5be795803b4cda1a4f0fcb2ee151adb9980a9 --- M src/soc/amd/common/block/acpimmio/biosram.c M src/soc/amd/common/block/include/amdblocks/biosram.h 2 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/38701/1 diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index 814fdf3..8450759 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -18,6 +18,14 @@ #include <stdint.h> /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_RAM_BOOTBLOCK_SIZE 0xb8 /* 4 bytes */ +#define BIOSRAM_RAM_VERSTAGE_SIZE 0xbc /* 4 bytes */ +#define BIOSRAM_RAM_ROMSTAGE_SIZE 0xc0 /* 4 bytes */ +#define BIOSRAM_RAM_FSPM_SIZE 0xc4 /* 4 bytes */ +#define BIOSRAM_RAM_BOOTBLOCK_BASE 0xc8 /* 8 bytes */ +#define BIOSRAM_RAM_VERSTAGE_BASE 0xd0 /* 8 bytes */ +#define BIOSRAM_RAM_ROMSTAGE_BASE 0xd8 /* 8 bytes */ +#define BIOSRAM_RAM_FSPM_BASE 0xe0 /* 8 bytes */ #define BIOSRAM_AP_ENTRY 0xe8 /* 8 bytes */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ @@ -105,3 +113,59 @@ base |= ((uint64_t)(biosram_read32(BIOSRAM_UMA_BASE + 4)) << 32); return base; } + +void set_bootram_bootblock(uint64_t base, uint32_t size) +{ + biosram_write32(BIOSRAM_RAM_BOOTBLOCK_BASE, (uint32_t)base); + biosram_write32(BIOSRAM_RAM_BOOTBLOCK_BASE + 4, (uint32_t)(base >> 32)); + biosram_write32(BIOSRAM_RAM_BOOTBLOCK_SIZE, size); +} + +void get_bootram_bootblock(uint64_t *base, uint32_t *size) +{ + *base = biosram_read32(BIOSRAM_RAM_BOOTBLOCK_BASE); + *base |= ((uint64_t)(biosram_read32(BIOSRAM_RAM_BOOTBLOCK_BASE + 4)) << 32); + *size = biosram_read32(BIOSRAM_RAM_BOOTBLOCK_SIZE); +} + +void set_bootram_verstage(uint64_t base, uint32_t size) +{ + biosram_write32(BIOSRAM_RAM_VERSTAGE_BASE, (uint32_t)base); + biosram_write32(BIOSRAM_RAM_VERSTAGE_BASE + 4, (uint32_t)(base >> 32)); + biosram_write32(BIOSRAM_RAM_VERSTAGE_SIZE, size); +} + +void get_bootram_verstage(uint64_t *base, uint32_t *size) +{ + *base = biosram_read32(BIOSRAM_RAM_VERSTAGE_BASE); + *base |= ((uint64_t)(biosram_read32(BIOSRAM_RAM_VERSTAGE_BASE + 4)) << 32); + *size = biosram_read32(BIOSRAM_RAM_VERSTAGE_SIZE); +} + +void set_bootram_romstage(uint64_t base, uint32_t size) +{ + biosram_write32(BIOSRAM_RAM_ROMSTAGE_BASE, (uint32_t)base); + biosram_write32(BIOSRAM_RAM_ROMSTAGE_BASE + 4, (uint32_t)(base >> 32)); + biosram_write32(BIOSRAM_RAM_ROMSTAGE_SIZE, size); +} + +void get_bootram_romstage(uint64_t *base, uint32_t *size) +{ + *base = biosram_read32(BIOSRAM_RAM_ROMSTAGE_BASE); + *base |= ((uint64_t)(biosram_read32(BIOSRAM_RAM_ROMSTAGE_BASE + 4)) << 32); + *size = biosram_read32(BIOSRAM_RAM_ROMSTAGE_SIZE); +} + +void set_bootram_fspm(uint64_t base, uint32_t size) +{ + biosram_write32(BIOSRAM_RAM_FSPM_BASE, (uint32_t)base); + biosram_write32(BIOSRAM_RAM_FSPM_BASE + 4, (uint32_t)(base >> 32)); + biosram_write32(BIOSRAM_RAM_FSPM_SIZE, size); +} + +void get_bootram_fspm(uint64_t *base, uint32_t *size) +{ + *base = biosram_read32(BIOSRAM_RAM_FSPM_BASE); + *base |= ((uint64_t)(biosram_read32(BIOSRAM_RAM_FSPM_BASE + 4)) << 32); + *size = biosram_read32(BIOSRAM_RAM_FSPM_SIZE); +} diff --git a/src/soc/amd/common/block/include/amdblocks/biosram.h b/src/soc/amd/common/block/include/amdblocks/biosram.h index 4bfd629..f3d95df 100644 --- a/src/soc/amd/common/block/include/amdblocks/biosram.h +++ b/src/soc/amd/common/block/include/amdblocks/biosram.h @@ -29,4 +29,23 @@ /* Returns the saved UMA base */ uint64_t get_uma_base(void); +/* set/get_bootram typically only used for RESET_VECTOR_IN_RAM */ + +/* Saves RAM consumed by bootblock */ +void set_bootram_bootblock(uint64_t base, uint32_t size); +/* Gets RAM consumed by bootblock */ +void get_bootram_bootblock(uint64_t *base, uint32_t *size); +/* Saves RAM consumed by verstage */ +void set_bootram_verstage(uint64_t base, uint32_t size); +/* Gets RAM consumed by verstage */ +void get_bootram_verstage(uint64_t *base, uint32_t *size); +/* Saves RAM consumed by romstage */ +void set_bootram_romstage(uint64_t base, uint32_t size); +/* Gets RAM consumed by romstage */ +void get_bootram_romstage(uint64_t *base, uint32_t *size); +/* Saves RAM consumed by FSP-M */ +void set_bootram_fspm(uint64_t base, uint32_t size); +/* Gets RAM consumed by FSP-M */ +void get_bootram_fspm(uint64_t *base, uint32_t *size); + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/38701 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14f5be795803b4cda1a4f0fcb2ee151adb9980a9 Gerrit-Change-Number: 38701 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: arch/x86: Set/get DRAM consumed by early non-XIP stages
by Marshall Dawson (Code Review) 18 Jun '20

18 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38729 ) Change subject: arch/x86: Set/get DRAM consumed by early non-XIP stages ...................................................................... arch/x86: Set/get DRAM consumed by early non-XIP stages Save DRAM consumed by bootblock, verstage, and romstage when those stages do not execute in place (and also not from CAR). Gather each program's region as they are prepared to be run. Store the information in a new earlymem region then move to cbmem when it comes online. Override the weak bootmem_platform_add_ranges() to reserve the regions in ramstage. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: Ieaf2885cb23ea42520c086f2ba06d7013becae07 --- M src/arch/x86/Makefile.inc M src/arch/x86/early_ram.ld M src/arch/x86/include/arch/stages.h A src/arch/x86/nonxip_rsvd.c M src/commonlib/include/commonlib/cbmem_id.h M src/cpu/x86/mtrr/nonxip_cache.c M src/include/memlayout.h M src/include/symbols.h 8 files changed, 117 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/38729/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 534f2ce..1e52a32 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -100,6 +100,7 @@ all-y += memset.c all-y += cpu_common.c all-y += post.c +all-$(CONFIG_RESET_VECTOR_IN_RAM) += nonxip_rsvd.c endif diff --git a/src/arch/x86/early_ram.ld b/src/arch/x86/early_ram.ld index af576ca..c8afe2a 100644 --- a/src/arch/x86/early_ram.ld +++ b/src/arch/x86/early_ram.ld @@ -17,6 +17,7 @@ * regions by placing them near the top of bootblock's program region. * The stack area is reused although not shared across stages. */ +_EARLYSTAGES_RSVD_SIZE = 0x40; _STACK_SIZE = CONFIG_EARLYRAM_BSP_STACK_SIZE; _CONSOLE_SIZE = CONFIG_PRERAM_CBMEM_CONSOLE_SIZE; _TIMESTAMPS_SIZE = 0x200; @@ -30,8 +31,9 @@ _bogus1 = ASSERT(_STACK_SIZE > 0x0, "Early BSP stack size not configured"); /* Place the following regions in predictable locations */ -. = CONFIG_X86_RESET_VECTOR - _STACK_SIZE - _CONSOLE_SIZE - _TIMESTAMPS_SIZE - _FMAP_SIZE - _PAD_FOR_ALIGNS; +. = CONFIG_X86_RESET_VECTOR - _EARLYSTAGES_RSVD_SIZE - _STACK_SIZE - _CONSOLE_SIZE - _TIMESTAMPS_SIZE - _FMAP_SIZE - _PAD_FOR_ALIGNS; .earlyram.data . (NOLOAD) : { + EARLYSTAGES_RSVD_MEM(., _EARLYSTAGES_RSVD_SIZE) EARLYRAM_STACK(., _STACK_SIZE) PRERAM_CBMEM_CONSOLE(., _CONSOLE_SIZE) TIMESTAMP(., _TIMESTAMPS_SIZE) diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h index 0726cac..c598faf 100644 --- a/src/arch/x86/include/arch/stages.h +++ b/src/arch/x86/include/arch/stages.h @@ -14,4 +14,9 @@ #ifndef __ARCH_STAGES_H #define __ARCH_STAGES_H +#include <program_loading.h> + +/* Reserve DRAM used by an early stage not executing as XIP or from CAR */ +void reserve_non_xip_prog(struct prog *prog); + #endif diff --git a/src/arch/x86/nonxip_rsvd.c b/src/arch/x86/nonxip_rsvd.c new file mode 100644 index 0000000..1d231ec --- /dev/null +++ b/src/arch/x86/nonxip_rsvd.c @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/stages.h> +#include <bootmem.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <program_loading.h> +#include <string.h> +#include <symbols.h> + +struct stages_rsvd_dram { + struct region bootblock; + struct region verstage; + struct region romstage; +}; + + +void reserve_non_xip_prog(struct prog *prog) +{ + struct stages_rsvd_dram *p; + + p = (struct stages_rsvd_dram *)_earlystages_rsvd_mem; + + if (ENV_BOOTBLOCK) { + /* bootblock inits the region and reserves self */ + memset(p, _eearlystages_rsvd_mem - _earlystages_rsvd_mem, 0); + p->bootblock.offset = (uintptr_t)_bootblock; + p->bootblock.size = ALIGN_UP(_ebootblock - _bootblock, 4 * KiB); + } + + switch (prog->type) { + case PROG_VERSTAGE: + p->verstage.offset = region_device_offset(&prog->rdev); + p->verstage.size = ALIGN_UP(region_device_sz(&prog->rdev), 4 * KiB); + break; + case PROG_ROMSTAGE: + p->romstage.offset = region_device_offset(&prog->rdev); + p->romstage.size = ALIGN_UP(region_device_sz(&prog->rdev), 4 * KiB); + break; + default: + printk(BIOS_ERR, "BUG: Unexpected PROG_LOAD for type %d\n", prog->type); + } +} + +void bootmem_platform_add_ranges(void) +{ + const struct cbmem_entry *rsvd_mem; + struct stages_rsvd_dram *p; + + rsvd_mem = cbmem_entry_find(CBMEM_ID_NONXIP_RSVD); + if (!rsvd_mem) { + printk(BIOS_ERR, "Error: Unable to find reserved regions in cbmem: %s()\n", + __func__); + return; + } + p = cbmem_entry_start(rsvd_mem); + + bootmem_add_range(p->bootblock.offset, p->bootblock.size, BM_MEM_RESERVED); + bootmem_add_range(p->verstage.offset, p->verstage.size, BM_MEM_RESERVED); + bootmem_add_range(p->romstage.offset, p->romstage.size, BM_MEM_RESERVED); +} + +static void alloc_reservations_in_cbmem(int unused) +{ + struct stages_rsvd_dram *c, *p; + + c = cbmem_add(CBMEM_ID_NONXIP_RSVD, sizeof(struct stages_rsvd_dram)); + if (!c) { + printk(BIOS_ERR, "Error: Unable to add reserved regions to cbmem: %s()\n", + __func__); + return; + } + + p = (struct stages_rsvd_dram *)_earlystages_rsvd_mem; + memcpy(c, p, sizeof(*p)); +} + +ROMSTAGE_CBMEM_INIT_HOOK(alloc_reservations_in_cbmem) diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index b063cd1..3a4f563 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -56,6 +56,7 @@ #define CBMEM_ID_ROMSTAGE_RAM_STACK 0x90357ac4 #define CBMEM_ID_ROOT 0xff4007ff #define CBMEM_ID_SMBIOS 0x534d4254 +#define CBMEM_ID_NONXIP_RSVD 0x4e584950 #define CBMEM_ID_BERT_RAW_DATA 0x42455254 #define CBMEM_ID_SMM_TSEG_SPACE 0x54534547 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee @@ -122,6 +123,7 @@ { CBMEM_ID_ROMSTAGE_RAM_STACK, "ROMSTG STCK" }, \ { CBMEM_ID_ROOT, "CBMEM ROOT " }, \ { CBMEM_ID_SMBIOS, "SMBIOS " }, \ + { CBMEM_ID_NONXIP_RSVD, "NONXIP RSVD" }, \ { CBMEM_ID_BERT_RAW_DATA, "BERT DATA " }, \ { CBMEM_ID_SMM_TSEG_SPACE, "TSEG " }, \ { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, \ diff --git a/src/cpu/x86/mtrr/nonxip_cache.c b/src/cpu/x86/mtrr/nonxip_cache.c index 334e829..6309b48 100644 --- a/src/cpu/x86/mtrr/nonxip_cache.c +++ b/src/cpu/x86/mtrr/nonxip_cache.c @@ -12,11 +12,14 @@ */ #include <stdint.h> +#include <arch/stages.h> #include <cpu/x86/mtrr.h> #include <console/console.h> #include <program_loading.h> - -void reserve_non_xip_prog(struct prog *prog); // move me +#include <string.h> +#include <commonlib/region.h> +#include <cbmem.h> +#include <symbols.h> /* Set a variable MTRR to WB for the program about to run. * It is up to the designer to ensure ranges are chosen carefully to avoid @@ -33,6 +36,11 @@ uint32_t mtrr_base; uint32_t mtrr_size = 4 * KiB; + if (!ENV_ROMSTAGE_OR_BEFORE) + return; + + reserve_non_xip_prog(prog); + mtrr_num = get_free_var_mtrr(); if (mtrr_num == -1) { printk(BIOS_NOTICE, diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 3c8e02b..0afc551 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -74,6 +74,10 @@ ALIGN_COUNTER(16) \ REGION(earlyram_stack, addr, size, 16) +#define EARLYSTAGES_RSVD_MEM(addr, size) \ + ALIGN_COUNTER(4) \ + REGION(earlystages_rsvd_mem, addr, size, 4) + /* Use either CBFS_CACHE (unified) or both (PRERAM|POSTRAM)_CBFS_CACHE */ #define CBFS_CACHE(addr, size) \ REGION(cbfs_cache, addr, size, 4) \ diff --git a/src/include/symbols.h b/src/include/symbols.h index eec4701..649accc 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -35,6 +35,7 @@ DECLARE_REGION(postram_cbfs_cache) DECLARE_REGION(cbfs_cache) DECLARE_REGION(fmap_cache) +DECLARE_REGION(earlystages_rsvd_mem) DECLARE_REGION(payload) /* "program" always refers to the current execution unit. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaf2885cb23ea42520c086f2ba06d7013becae07 Gerrit-Change-Number: 38729 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 8

Change in coreboot[master]: mb/amd/inagua: Fix typos
by HAOUAS Elyes (Code Review) 18 Jun '20

18 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39102 ) Change subject: mb/amd/inagua: Fix typos ...................................................................... mb/amd/inagua: Fix typos Change-Id: Idff7c3ef6d8b7b0809857fbfd591851943ffc9fd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/inagua/irq_tables.c M src/mainboard/amd/inagua/mainboard.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39102/1 diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 1d1e81f..ad5c310 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -77,7 +77,7 @@ pirq_info = (void *)(&pirq->checksum + 1); slot_num = 0; - /* pci bridge */ + /* PCI bridge */ write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c index 47a267b..b868a58 100644 --- a/src/mainboard/amd/inagua/mainboard.c +++ b/src/mainboard/amd/inagua/mainboard.c @@ -20,14 +20,14 @@ static void init_gpios(void) { /** - * GPIO32 Pcie Device DeAssert for APU - * GPIO25 Pcie LAN, APU GPP2 + * GPIO32 PCIe Device DeAssert for APU + * GPIO25 PCIe LAN, APU GPP2 * GPIO02 MINIPCIE SLOT1, APU GPP3 - * GPIO50 Pcie Device DeAssert for Hudson Southbridge + * GPIO50 PCIe Device DeAssert for Hudson Southbridge * GPIO05 Express Card, SB GPP0 * GPIO26 NEC USB3.0GPPUSB, SB GPP1 * GPIO00 MINIPCIE SLOT2, SB GPP2 - * GPIO05 Pcie X1 Slot, SB GPP3 + * GPIO05 PCIe X1 Slot, SB GPP3 */ /* Multi-function pins switch to GPIO0-35, these pins are shared with -- To view, visit https://review.coreboot.org/c/coreboot/+/39102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idff7c3ef6d8b7b0809857fbfd591851943ffc9fd Gerrit-Change-Number: 39102 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: sb/intel/i82801{d,j}x/nvs: Rename register
by HAOUAS Elyes (Code Review) 18 Jun '20

18 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38957 ) Change subject: sb/intel/i82801{d,j}x/nvs: Rename register ...................................................................... sb/intel/i82801{d,j}x/nvs: Rename register Rename register to match recent intel models. Change-Id: Ibf0f684efdf311cafc0184609c65ecc893c8f63d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/getac/p470/acpi/ec.asl M src/mainboard/getac/p470/acpi/thermal.asl M src/southbridge/intel/i82801dx/nvs.h M src/southbridge/intel/i82801jx/acpi/globalnvs.asl M src/southbridge/intel/i82801jx/nvs.h 5 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/38957/1 diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl index 6783289..2a551fa 100644 --- a/src/mainboard/getac/p470/acpi/ec.asl +++ b/src/mainboard/getac/p470/acpi/ec.asl @@ -54,7 +54,7 @@ CTMP, 8, // CPU Temperature Offset(0x15), CTRO, 8, // EC throttling on trip point - CRTT, 8, // Critical Shut-down Temperature + TCRT, 8, // Critical Shut-down Temperature Offset(0x17), BKLL, 8, // Backlight Level diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl index 6c9f2e9..bb51bb9 100644 --- a/src/mainboard/getac/p470/acpi/thermal.asl +++ b/src/mainboard/getac/p470/acpi/thermal.asl @@ -49,7 +49,7 @@ // Critical shutdown temperature Method (_CRT, 0, Serialized) { - Store(\_SB.PCI0.LPCB.EC0.CRTT, Local0) + Store(\_SB.PCI0.LPCB.EC0.TCRT, Local0) Store(DEGR(Local0), Local0) Return(Local0) } diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h index 3a72f4d..8928c62 100644 --- a/src/southbridge/intel/i82801dx/nvs.h +++ b/src/southbridge/intel/i82801dx/nvs.h @@ -33,11 +33,11 @@ u8 dckn; /* 0x13 - PCIe docking state */ /* Thermal policy */ u8 actt; /* 0x14 - active trip point */ - u8 psvt; /* 0x15 - passive trip point */ + u8 tpsv; /* 0x15 - passive trip point */ u8 tc1v; /* 0x16 - passive trip point TC1 */ u8 tc2v; /* 0x17 - passive trip point TC2 */ u8 tspv; /* 0x18 - passive trip point TSP */ - u8 crtt; /* 0x19 - critical trip point */ + u8 tcrt; /* 0x19 - critical trip point */ u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ u8 dts1; /* 0x1b - DT sensor 1 */ u8 dts2; /* 0x1c - DT sensor 2 */ diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl index 44aa8e4..c1be852 100644 --- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl @@ -51,11 +51,11 @@ /* Thermal policy */ Offset (0x14), ACTT, 8, // 0x14 - active trip point - PSVT, 8, // 0x15 - passive trip point + TPSV, 8, // 0x15 - passive trip point TC1V, 8, // 0x16 - passive trip point TC1 TC2V, 8, // 0x17 - passive trip point TC2 TSPV, 8, // 0x18 - passive trip point TSP - CRTT, 8, // 0x19 - critical trip point + TCRT, 8, // 0x19 - critical trip point DTSE, 8, // 0x1a - Digital Thermal Sensor enable DTS1, 8, // 0x1b - DT sensor 1 FLVL, 8, // 0x1c - current fan level diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h index 88944c0..c13ad70 100644 --- a/src/southbridge/intel/i82801jx/nvs.h +++ b/src/southbridge/intel/i82801jx/nvs.h @@ -35,11 +35,11 @@ u8 dckn; /* 0x13 - PCIe docking state */ /* Thermal policy */ u8 actt; /* 0x14 - active trip point */ - u8 psvt; /* 0x15 - passive trip point */ + u8 tpsv; /* 0x15 - passive trip point */ u8 tc1v; /* 0x16 - passive trip point TC1 */ u8 tc2v; /* 0x17 - passive trip point TC2 */ u8 tspv; /* 0x18 - passive trip point TSP */ - u8 crtt; /* 0x19 - critical trip point */ + u8 tcrt; /* 0x19 - critical trip point */ u8 dtse; /* 0x1a - Digital Thermal Sensor enable */ u8 dts1; /* 0x1b - DT sensor 1 */ u8 flvl; /* 0x1c - current fan level */ -- To view, visit https://review.coreboot.org/c/coreboot/+/38957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf0f684efdf311cafc0184609c65ecc893c8f63d Gerrit-Change-Number: 38957 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: crossgcc: Upgrade GDB to version 9.1
by HAOUAS Elyes (Code Review) 17 Jun '20

17 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38787 ) Change subject: crossgcc: Upgrade GDB to version 9.1 ...................................................................... crossgcc: Upgrade GDB to version 9.1 Change-Id: I30dae356ec3b373ac036c7eced7d6e89ddd08246 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gdb-8.3.1_no-doc.patch R util/crossgcc/patches/gdb-9.1_amd64.patch A util/crossgcc/patches/gdb-9.1_no-doc.patch R util/crossgcc/patches/gdb-9.1_pythonhome.patch D util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum A util/crossgcc/sum/gdb-9.1.tar.xz.cksum 7 files changed, 13 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/38787/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9920799..9fe14d0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -53,7 +53,7 @@ GCC_VERSION=9.2.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 -GDB_VERSION=8.3.1 +GDB_VERSION=9.1 IASL_VERSION=20200110 PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 diff --git a/util/crossgcc/patches/gdb-8.3.1_no-doc.patch b/util/crossgcc/patches/gdb-8.3.1_no-doc.patch deleted file mode 100644 index 80dd349..0000000 --- a/util/crossgcc/patches/gdb-8.3.1_no-doc.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN gdb-8.0.orig/gdb/Makefile.in gdb-8.0/gdb/Makefile.in ---- gdb-8.2.1.orig/gdb/Makefile.in 2019-01-04 12:58:10.227572419 +0100 -+++ gdb-8.2.1/gdb/Makefile.in 2019-01-04 12:59:00.539134274 +0100 -@@ -1568,7 +1568,7 @@ - - TSOBS = inflow.o - --SUBDIRS = doc @subdirs@ data-directory $(GNULIB_BUILDDIR) -+SUBDIRS = @subdirs@ data-directory $(GNULIB_BUILDDIR) - CLEANDIRS = $(SUBDIRS) - - # List of subdirectories in the build tree that must exist. diff --git a/util/crossgcc/patches/gdb-8.3.1_amd64.patch b/util/crossgcc/patches/gdb-9.1_amd64.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3.1_amd64.patch rename to util/crossgcc/patches/gdb-9.1_amd64.patch diff --git a/util/crossgcc/patches/gdb-9.1_no-doc.patch b/util/crossgcc/patches/gdb-9.1_no-doc.patch new file mode 100644 index 0000000..59ca998 --- /dev/null +++ b/util/crossgcc/patches/gdb-9.1_no-doc.patch @@ -0,0 +1,11 @@ +--- gdb-9.1.orig/gdb/Makefile.in 2020-02-08 13:50:14.000000000 +0100 ++++ gdb-9.1/gdb/Makefile.in 2020-02-08 20:11:17.201244042 +0100 +@@ -1606,7 +1606,7 @@ + $(SUBDIR_TARGET_OBS) \ + $(SUBDIR_GCC_COMPILE_OBS) + +-SUBDIRS = doc @subdirs@ data-directory ++SUBDIRS = @subdirs@ data-directory + CLEANDIRS = $(SUBDIRS) + + # List of subdirectories in the build tree that must exist. diff --git a/util/crossgcc/patches/gdb-8.3.1_pythonhome.patch b/util/crossgcc/patches/gdb-9.1_pythonhome.patch similarity index 100% rename from util/crossgcc/patches/gdb-8.3.1_pythonhome.patch rename to util/crossgcc/patches/gdb-9.1_pythonhome.patch diff --git a/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum b/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum deleted file mode 100644 index c362858..0000000 --- a/util/crossgcc/sum/gdb-8.3.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -d403ba208945bbf04f8130ea4853730cdf0c8fc7 tarballs/gdb-8.3.1.tar.xz diff --git a/util/crossgcc/sum/gdb-9.1.tar.xz.cksum b/util/crossgcc/sum/gdb-9.1.tar.xz.cksum new file mode 100644 index 0000000..b65b5e9 --- /dev/null +++ b/util/crossgcc/sum/gdb-9.1.tar.xz.cksum @@ -0,0 +1 @@ +a50e13e1eecea468ea28c4a23d8c5a84f4db25be tarballs/gdb-9.1.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/38787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30dae356ec3b373ac036c7eced7d6e89ddd08246 Gerrit-Change-Number: 38787 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: crossgcc: Upgrade make to version 4.3
by HAOUAS Elyes (Code Review) 17 Jun '20

17 Jun '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38483 ) Change subject: crossgcc: Upgrade make to version 4.3 ...................................................................... crossgcc: Upgrade make to version 4.3 _0068-configure.ac-Support-GLIBC-glob-interface-version-2.patch and _0053-glob-Do-not-assume-glibc-glob-internals.patch are integrated in upstream, so we don't need it anymore Change-Id: I08f592731c3da2ac19e1f93682256f559a067fc4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/make-4.2.1_0053-glob-Do-not-assume-glibc-glob-internals.patch D util/crossgcc/patches/make-4.2.1_0068-configure.ac-Support-GLIBC-glob-interface-version-2.patch R util/crossgcc/patches/make-4.3_alloca.patch D util/crossgcc/sum/make-4.2.1.tar.bz2.cksum A util/crossgcc/sum/make-4.3.tar.gz.cksum 6 files changed, 5 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/38483/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ab2ea89..863afa5 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -63,7 +63,7 @@ EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=9.0.0 -MAKE_VERSION=4.2.1 +MAKE_VERSION=4.3 CMAKE_VERSION=3.16.2 NASM_VERSION=2.14.02 @@ -85,7 +85,7 @@ CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src…" CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSIO…" -MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" +MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.gz" CMAKE_ARCHIVE="https://cmake.org/files/v3.16/cmake-${CMAKE_VERSION}.tar.gz" NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERS…" diff --git a/util/crossgcc/patches/make-4.2.1_0053-glob-Do-not-assume-glibc-glob-internals.patch b/util/crossgcc/patches/make-4.2.1_0053-glob-Do-not-assume-glibc-glob-internals.patch deleted file mode 100644 index 3d45025..0000000 --- a/util/crossgcc/patches/make-4.2.1_0053-glob-Do-not-assume-glibc-glob-internals.patch +++ /dev/null @@ -1,67 +0,0 @@ -From 193f1e81edd6b1b56b0eb0ff8aa4b41c7b4257b4 Mon Sep 17 00:00:00 2001 -From: Paul Eggert <eggert(a)cs.ucla.edu> -Date: Sun, 24 Sep 2017 09:12:58 -0400 -Subject: [PATCH 53/78] glob: Do not assume glibc glob internals. - -It has been proposed that glibc glob start using gl_lstat, -which the API allows it to do. GNU 'make' should not get in -the way of this. See: -https://sourceware.org/ml/libc-alpha/2017-09/msg00409.html - -* dir.c (local_lstat): New function, like local_stat. -(dir_setup_glob): Use it to initialize gl_lstat too, as the API -requires. ---- - dir.c | 29 +++++++++++++++++++++++++++-- - 1 file changed, 27 insertions(+), 2 deletions(-) - -diff --git a/dir.c b/dir.c -index adbb8a9..c343e4c 100644 ---- a/dir.c -+++ b/dir.c -@@ -1299,15 +1299,40 @@ local_stat (const char *path, struct stat *buf) - } - #endif - -+/* Similarly for lstat. */ -+#if !defined(lstat) && !defined(WINDOWS32) || defined(VMS) -+# ifndef VMS -+# ifndef HAVE_SYS_STAT_H -+int lstat (const char *path, struct stat *sbuf); -+# endif -+# else -+ /* We are done with the fake lstat. Go back to the real lstat */ -+# ifdef lstat -+# undef lstat -+# endif -+# endif -+# define local_lstat lstat -+#elif defined(WINDOWS32) -+/* Windows doesn't support lstat(). */ -+# define local_lstat local_stat -+#else -+static int -+local_lstat (const char *path, struct stat *buf) -+{ -+ int e; -+ EINTRLOOP (e, lstat (path, buf)); -+ return e; -+} -+#endif -+ - void - dir_setup_glob (glob_t *gl) - { - gl->gl_opendir = open_dirstream; - gl->gl_readdir = read_dirstream; - gl->gl_closedir = free; -+ gl->gl_lstat = local_lstat; - gl->gl_stat = local_stat; -- /* We don't bother setting gl_lstat, since glob never calls it. -- The slot is only there for compatibility with 4.4 BSD. */ - } - - void --- -2.18.0 - diff --git a/util/crossgcc/patches/make-4.2.1_0068-configure.ac-Support-GLIBC-glob-interface-version-2.patch b/util/crossgcc/patches/make-4.2.1_0068-configure.ac-Support-GLIBC-glob-interface-version-2.patch deleted file mode 100644 index 53e61b8..0000000 --- a/util/crossgcc/patches/make-4.2.1_0068-configure.ac-Support-GLIBC-glob-interface-version-2.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 48c8a116a914a325a0497721f5d8b58d5bba34d4 Mon Sep 17 00:00:00 2001 -From: Paul Smith <psmith(a)gnu.org> -Date: Sun, 19 Nov 2017 15:09:16 -0500 -Subject: [PATCH 68/78] * configure.ac: Support GLIBC glob interface version 2 - ---- - configure.ac | 3 +-- - 1 file changed, 1 insertion(+), 2 deletions(-) - -diff --git a/configure.ac b/configure.ac -index 8c72568..4710832 100644 ---- a/configure.ac -+++ b/configure.ac -@@ -404,10 +404,9 @@ AC_CACHE_CHECK([if system libc has GNU glob], [make_cv_sys_gnu_glob], - #include <glob.h> - #include <fnmatch.h> - --#define GLOB_INTERFACE_VERSION 1 - #if !defined _LIBC && defined __GNU_LIBRARY__ && __GNU_LIBRARY__ > 1 - # include <gnu-versions.h> --# if _GNU_GLOB_INTERFACE_VERSION == GLOB_INTERFACE_VERSION -+# if _GNU_GLOB_INTERFACE_VERSION == 1 || _GNU_GLOB_INTERFACE_VERSION == 2 - gnu glob - # endif - #endif], --- -2.18.0 - diff --git a/util/crossgcc/patches/make-4.2.1_alloca.patch b/util/crossgcc/patches/make-4.3_alloca.patch similarity index 61% rename from util/crossgcc/patches/make-4.2.1_alloca.patch rename to util/crossgcc/patches/make-4.3_alloca.patch index 61a3581..6dd1fd1 100644 --- a/util/crossgcc/patches/make-4.2.1_alloca.patch +++ b/util/crossgcc/patches/make-4.3_alloca.patch @@ -1,5 +1,5 @@ ---- clean/make-4.2/glob/glob.c 2013-10-20 17:14:38.000000000 +0000 -+++ make-4.2/glob/glob.c 2018-09-18 10:16:03.860886356 +0000 +--- clean/make-4.3/lib/glob.c ++++ make-4.3/lib/glob.c @@ -208,7 +208,7 @@ #endif /* __GNU_LIBRARY__ || __DJGPP__ */ diff --git a/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum b/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum deleted file mode 100644 index 34af72c..0000000 --- a/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -7d9d11eb36cfb752da1fb11bb3e521d2a3cc8830 tarballs/make-4.2.1.tar.bz2 diff --git a/util/crossgcc/sum/make-4.3.tar.gz.cksum b/util/crossgcc/sum/make-4.3.tar.gz.cksum new file mode 100644 index 0000000..c68844a --- /dev/null +++ b/util/crossgcc/sum/make-4.3.tar.gz.cksum @@ -0,0 +1 @@ +3c40e5b49b893dbb14f1e2e1f8fe89b7298cc51d tarballs/make-4.3.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/38483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08f592731c3da2ac19e1f93682256f559a067fc4 Gerrit-Change-Number: 38483 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

6 30

Change in coreboot[master]: [WIP] arch/x86: Declare acpi_disable_sci_on_exit()
by Kyösti Mälkki (Code Review) 10 Jun '20

10 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36828 ) Change subject: [WIP] arch/x86: Declare acpi_disable_sci_on_exit() ...................................................................... [WIP] arch/x86: Declare acpi_disable_sci_on_exit() Change-Id: I9d9b2085c0f06235f1e7ea395c9df826c3988027 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/cpu/x86/smm.h M src/soc/amd/picasso/finalize.c M src/soc/amd/stoneyridge/finalize.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/denverton_ns/pmc.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 14 files changed, 48 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/36828/1 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index c3e1b9c..0f0d19b 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -62,6 +62,11 @@ return CONFIG(HAVE_SMI_HANDLER); } +static inline int acpi_disable_sci_on_exit(void) +{ + return CONFIG(HAVE_SMI_HANDLER); +} + /* This is the SMM handler. */ extern unsigned char _binary_smm_start[]; extern unsigned char _binary_smm_end[]; diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 947337d..eb6dd3d 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -57,12 +57,10 @@ { finalize_cores(); - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - acpi_disable_sci(); - else - acpi_enable_sci(); - } + if (acpi_disable_sci_on_exit()) + acpi_disable_sci(); + else + acpi_enable_sci(); post_code(POST_OS_BOOT); } diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 947337d..eb6dd3d 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -57,12 +57,10 @@ { finalize_cores(); - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - acpi_disable_sci(); - else - acpi_enable_sci(); - } + if (acpi_disable_sci_on_exit()) + acpi_disable_sci(); + else + acpi_enable_sci(); post_code(POST_OS_BOOT); } diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 3392614..0dbd91f 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -424,7 +424,7 @@ static void pch_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 1d2aa61..aebbead 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -106,7 +106,7 @@ void pmc_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index 8b52087..75da082 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -38,7 +38,7 @@ static void pch_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c index 7759758..77d7159 100644 --- a/src/southbridge/amd/agesa/hudson/lpc.c +++ b/src/southbridge/amd/agesa/hudson/lpc.c @@ -338,12 +338,10 @@ static void lpc_final(struct device *dev) { - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ - else - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - } + if (acpi_disable_sci_on_exit()) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } static struct pci_operations lops_pci = { diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 6654830..9d093ec 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -354,12 +354,10 @@ static void lpc_final(struct device *dev) { - if (!acpi_is_wakeup_s3()) { - if (CONFIG(HAVE_SMI_HANDLER)) - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ - else - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ - } + if (acpi_disable_sci_on_exit()) + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + else + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ } static struct pci_operations lops_pci = { diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index e7b7db8..b77a05b 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -418,7 +418,7 @@ static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 34250d39..30c0263 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -335,15 +335,13 @@ static void i82801gx_set_acpi_mode(struct device *dev) { - if (CONFIG(HAVE_SMI_HANDLER)) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - } + if (acpi_disable_sci_on_exit()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 63d3ffe..3709f71 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -368,15 +368,13 @@ static void i82801ix_set_acpi_mode(struct device *dev) { - if (CONFIG(HAVE_SMI_HANDLER)) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - } + if (acpi_disable_sci_on_exit()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a594452..a88b239 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -372,15 +372,13 @@ static void i82801jx_set_acpi_mode(struct device *dev) { - if (CONFIG(HAVE_SMI_HANDLER)) { - if (!acpi_is_wakeup_s3()) { - printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); - outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode - printk(BIOS_DEBUG, "done.\n"); - } else { - printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); - outb(APM_CNT_ACPI_ENABLE, APM_CNT); - } + if (acpi_disable_sci_on_exit()) { + printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); + outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode + printk(BIOS_DEBUG, "done.\n"); + } else { + printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); + outb(APM_CNT_ACPI_ENABLE, APM_CNT); } } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 2b48eab..e20320e 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -428,7 +428,7 @@ static void pch_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3() && CONFIG(HAVE_SMI_HANDLER)) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); // Disable ACPI mode printk(BIOS_DEBUG, "done.\n"); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index c8e91c3..63dcbc0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -490,7 +490,7 @@ static void pch_set_acpi_mode(void) { - if (CONFIG(HAVE_SMI_HANDLER) && !acpi_is_wakeup_s3()) { + if (acpi_disable_sci_on_exit()) { printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n"); outb(APM_CNT_ACPI_DISABLE, APM_CNT); printk(BIOS_DEBUG, "done.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/36828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d9b2085c0f06235f1e7ea395c9df826c3988027 Gerrit-Change-Number: 36828 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: _WIP_ soc/amd/picasso: Update all remaining pci_devs
by Marshall Dawson (Code Review) 10 Jun '20

10 Jun '20

Hello Martin Roth, Furquan Shaikh, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34429 to review the following change. Change subject: _WIP_ soc/amd/picasso: Update all remaining pci_devs ...................................................................... _WIP_ soc/amd/picasso: Update all remaining pci_devs Unlike older products, many of the Family 17h PCI devices are not on bus 0, and therefore cannot be located using pcidev_on_root(). The PPR (PID #55570, NDA required) shows Bus A and Bus B devices, where 0:8.1 and 0:8.2 are the bridges to them. Also, unlike older products, the bridges are not hidden for the purpose of making devices appear to be on bus 0. Rework pci_devs.h and other files to account for the new topology. Change-Id: I704e70fa266a13f1f3bcf0cd3afe5bc594d85894 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/picasso/include/soc/pci_devs.h 1 file changed, 32 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/34429/1 diff --git a/src/soc/amd/picasso/include/soc/pci_devs.h b/src/soc/amd/picasso/include/soc/pci_devs.h index 28fa99f..de5e446 100644 --- a/src/soc/amd/picasso/include/soc/pci_devs.h +++ b/src/soc/amd/picasso/include/soc/pci_devs.h @@ -84,7 +84,6 @@ #define PCIE8_DEVFN PCI_DEVFN(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC) #define SOC_PCIE8_DEV _SOC_DEV(PCIE_AB_BRIDGE_DEV, PCIE8_FUNC) - /* Data Fabric functions */ #define DF_DEV 0x18 @@ -116,29 +115,6 @@ #define DF_F6_DEVFN PCI_DEVFN(DF_DEV, 6) #define SOC_DF_F6_DEVFN _SOC_DEV(DF_DEV, 6) -/* USB 3.1 */ -#define XHCI0_DEV 0x0 -#define XHCI0_FUNC 3 -#define XHCI0_DEVID 0x15e0 -#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) -#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) - -/* USB 3.1 */ -#define XHCI1_DEV 0x0 -#define XHCI1_FUNC 4 -#define XHCI1_DEVID 0x15e1 -#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) -#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) - -/* SATA */ -#define SATA_DEV 0x11 -#define SATA_FUNC 0 -#define SATA_IDE_DEVID 0x7900 -#define AHCI_DEVID_MS 0x7901 -#define AHCI_DEVID_AMD 0x7904 -#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) -#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) - /* SMBUS */ #define SMBUS_DEV 0x14 #define SMBUS_FUNC 0 @@ -153,25 +129,48 @@ #define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) #define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) +/* + * Bus A devices + */ + /* Internal Graphics */ -#define GFX_DEV 0x1 +#define GFX_DEV 0x0 #define GFX_FUNC 0 #define GFX_DEVID 0x15d8 #define GFX_DEVFN PCI_DEVFN(GFX_DEV, GFX_FUNC) #define SOC_GFX_DEV _SOC_DEV(GFX_DEV, GFX_FUNC) /* HD Audio 0 */ -#define HDA0_DEV 0x1 +#define HDA0_DEV 0x0 #define HDA0_FUNC 1 -#define HDA0_DEVID 0x15b3 +#define HDA0_DEVID 0x15de #define HDA0_DEVFN PCI_DEVFN(HDA0_DEV, HDA0_FUNC) #define SOC_HDA0_DEV _SOC_DEV(HDA0_DEV, HDA0_FUNC) -/* HD Audio 1 */ -#define HDA1_DEV 0x9 -#define HDA1_FUNC 2 -#define HDA1_DEVID 0x157a -#define HDA1_DEVFN PCI_DEVFN(HDA1_DEV, HDA1_FUNC) -#define SOC_HDA1_DEV _SOC_DEV(HDA1_DEV, HDA1_FUNC) +/* USB 3.1 */ +#define XHCI0_DEV 0x0 +#define XHCI0_FUNC 3 +#define XHCI0_DEVID 0x15e0 +#define XHCI0_DEVFN PCI_DEVFN(XHCI0_DEV, XHCI0_FUNC) +#define SOC_XHCI0_DEV _SOC_DEV(XHCI0_DEV, XHCI0_FUNC) + +/* USB 3.1 */ +#define XHCI1_DEV 0x0 +#define XHCI1_FUNC 4 +#define XHCI1_DEVID 0x15e1 +#define XHCI1_DEVFN PCI_DEVFN(XHCI1_DEV, XHCI1_FUNC) +#define SOC_XHCI1_DEV _SOC_DEV(XHCI1_DEV, XHCI1_FUNC) + +/* + * Bus B devices + */ + +/* SATA */ +#define SATA_DEV 0x0 +#define SATA_FUNC 0 +#define AHCI_DEVID_MS 0x7901 +#define AHCI_DEVID_AMD 0x7904 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV, SATA_FUNC) +#define SOC_SATA_DEV _SOC_DEV(SATA_DEV, SATA_FUNC) #endif /* __PI_PICASSO_PCI_DEVS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34429 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I704e70fa266a13f1f3bcf0cd3afe5bc594d85894 Gerrit-Change-Number: 34429 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

1 1

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2020