coreboot-gerrit February 2020

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Change in coreboot[master]: soc/intel/baytrail,braswell: Refactor .post_mp_init
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37131 ) Change subject: soc/intel/baytrail,braswell: Refactor .post_mp_init ...................................................................... soc/intel/baytrail,braswell: Refactor .post_mp_init Make it consistent with rest of soc/intel. Change-Id: I42ce0af603f93a074bd629a68223cef88cbc210b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/baytrail/cpu.c M src/soc/intel/braswell/cpu.c 2 files changed, 12 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/37131/1 diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index d12ece0..2c59531 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -193,6 +193,11 @@ smm_state->smbase = staggered_smbase; } +static void post_mp_init(void) +{ + smm_southbridge_enable_smi(); +} + static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, @@ -201,7 +206,7 @@ .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = relocation_handler, - .post_mp_init = smm_southbridge_enable_smi, + .post_mp_init = post_mp_init, }; void baytrail_init_cpus(struct device *dev) diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index a44b9cb..33fe685 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -208,6 +208,11 @@ smm_state->smbase = staggered_smbase; } +static void post_mp_init(void) +{ + smm_southbridge_enable_smi(); +} + static const struct mp_ops mp_ops = { .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, @@ -216,7 +221,7 @@ .pre_mp_smm_init = smm_southbridge_clear_state, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = relocation_handler, - .post_mp_init = smm_southbridge_enable_smi, + .post_mp_init = post_mp_init, }; void soc_init_cpus(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/37131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42ce0af603f93a074bd629a68223cef88cbc210b Gerrit-Change-Number: 37131 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: cpu,soc/intel/smm: Define inlined smm_lock()
by Kyösti Mälkki (Code Review) 30 Jul '20

30 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34875 ) Change subject: cpu,soc/intel/smm: Define inlined smm_lock() ...................................................................... cpu,soc/intel/smm: Define inlined smm_lock() Change-Id: I66983b771feb5c05744255b9000c742c4c0e5025 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/smmrelocate.c M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/intel/smm_reloc.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/nehalem/smi.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/smmrelocate.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/smmrelocate.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/smmrelocate.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801dx/smi.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801ix/smi.c 30 files changed, 101 insertions(+), 172 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34875/1 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 1eb6f68..e2f468d 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -332,14 +332,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index b0c2c1a..b32af6f 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -34,11 +34,6 @@ #define SMRR_SUPPORTED (1 << 11) -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) @@ -141,17 +136,6 @@ memset(ied_base + (1 << 20), 0, (32 << 10)); } -void smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - - northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); -} - void smm_info(uintptr_t *perm_smbase, size_t *perm_smsize, size_t *smm_save_state_size) { diff --git a/src/include/cpu/intel/smm_reloc.h b/src/include/cpu/intel/smm_reloc.h index cb196fc..12247ab 100644 --- a/src/include/cpu/intel/smm_reloc.h +++ b/src/include/cpu/intel/smm_reloc.h @@ -23,11 +23,24 @@ } __packed; /* These helpers are for performing SMM relocation. */ -void northbridge_write_smram(u8 smram); - -void smm_lock(void); void smm_relocate(void); +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) + +static inline void smm_lock(void) +{ + /* LOCK the SMM memory window and enable normal SMM. + * After running this function, only a full reset can + * make the SMM registers writable again. + */ + printk(BIOS_DEBUG, "Locking SMM.\n"); + nb_smram_lock(); +} + /* The initialization of the southbridge is split into 2 components. One is * for clearing the state in the SMM registers. The other is for enabling * SMIs. They are split so that other work between the 2 actions. */ diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 7033f89..e6ccdb6 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -19,6 +19,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/intel/smm_reloc.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> #include "e7505.h" @@ -35,12 +36,10 @@ return (void *)tolm; } -void northbridge_write_smram(u8 smram); - -void northbridge_write_smram(u8 smram) +void nb_smram_lock(void) { pci_devfn_t mch = PCI_DEV(0, 0, 0); - pci_write_config8(mch, SMRAMC, smram); + pci_write_config8(mch, SMRAMC, D_LCK | G_SMRAME | C_BASE_SEG); } void fill_postcar_frame(struct postcar_frame *pcf) diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index 7eb07b8..207b120 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -124,6 +124,12 @@ return (void *) top_of_ram; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, D0F0_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 384d98a..39f98da 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -219,16 +219,6 @@ return NULL; } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, D0F0_SMRAM, smram); -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 59508be..a81a4bb 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -41,6 +41,12 @@ return (void *)smm_region_start(); } +void nb_smram_lock(void) +{ + pci_devfn_t dev = PCI_DEV(0,0,0); + pci_write_config8(dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = smm_region_start(); diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 3d3457d..93b307c 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -90,6 +90,12 @@ return ggc2uma[gms] << 10; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index dd4e8ac..73de993 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -154,16 +154,6 @@ return NULL; } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, SMRAM, smram); -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c index 8c19852..ea99da7 100644 --- a/src/northbridge/intel/nehalem/smi.c +++ b/src/northbridge/intel/nehalem/smi.c @@ -21,7 +21,8 @@ #include <cpu/intel/smm_reloc.h> -void northbridge_write_smram(u8 smram) +void nb_smram_lock(void) { - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); + pci_devfn_t qpd_d0f1 = PCI_DEV(QUICKPATH_BUS, 0, 1); + pci_write_config8(qpd_d0f1, QPD0F1_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); } diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 2400c59..fd02f77 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -140,6 +140,12 @@ } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 34cb583..b8dbaa2 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -140,16 +140,6 @@ add_fixed_resources(dev, index); } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, SMRAM, smram); -} - static void mch_domain_set_resources(struct device *dev) { struct resource *res; diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 41330f2..368456b 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -48,6 +48,12 @@ return CONFIG_SMM_TSEG_SIZE; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 58f4a68..a5872b6 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -444,11 +444,6 @@ MCHBAR32(0x5500) = 0x00100001; } -void northbridge_write_smram(u8 smram) -{ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, smram); -} - static struct pci_operations intel_pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 42786bb..b802973 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -135,6 +135,12 @@ return (void *) top_of_ram; } +void nb_smram_lock(void) +{ + pci_devfn_t mch = PCI_DEV(0, 0, 0); + pci_write_config8(mch, D0F0_SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + void smm_region(uintptr_t *start, size_t *size) { *start = northbridge_get_tseg_base(); diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index ee70527..8b5b9e0 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -171,16 +171,6 @@ return NULL; } -void northbridge_write_smram(u8 smram) -{ - struct device *dev = pcidev_on_root(0, 0); - - if (dev == NULL) - die("could not find pci 00:00.0!\n"); - - pci_write_config8(dev, D0F0_SMRAM, smram); -} - static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index f4a9d0e..062963d 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -56,3 +56,8 @@ *start = tseg; *size = bgsm - tseg; } + +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 21c534a..13d591d 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -295,14 +295,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c index 276b9a3..15ca276 100644 --- a/src/soc/intel/cannonlake/memmap.c +++ b/src/soc/intel/cannonlake/memmap.c @@ -35,6 +35,11 @@ *size = sa_get_tseg_size(); } +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + /* Calculate ME Stolen size */ static size_t get_imr_size(void) { diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index 493d003..11fe760 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -254,15 +254,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c index 0d41f25..94b1daf 100644 --- a/src/soc/intel/icelake/memmap.c +++ b/src/soc/intel/icelake/memmap.c @@ -33,6 +33,11 @@ *size = sa_get_tseg_size(); } +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + /* Calculate ME Stolen size */ static size_t get_imr_size(void) { diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index 65505c4..bb77375 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -253,15 +253,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 9d3f377..e4f4487 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -36,6 +36,11 @@ *size = sa_get_tseg_size(); } +void nb_smram_lock(void) +{ + pci_write_config8(SA_DEV_ROOT, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + static bool is_ptt_enable(void) { if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) == diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e1779d1..479abf7 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -253,15 +253,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index ac53ae1..678d5d7 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -37,9 +37,6 @@ void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); #endif - -void aseg_smm_lock(void); - #endif #define DEBUG_PERIODIC_SMIS 0 diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index 94d8e14..422ed57 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -304,7 +304,7 @@ * userspace applications to deceive us: */ if (CONFIG(HAVE_SMI_HANDLER)) - aseg_smm_lock(); + smm_lock(); } static void i82801dx_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index 521b98d..d85cd63 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -27,16 +27,6 @@ #include <string.h> #include "i82801dx.h" - -void northbridge_write_smram(u8 smram); - -/* For intel/e7505. */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) - /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value */ @@ -343,16 +333,6 @@ restore_default_smm_area(default_smm_area); } -void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - northbridge_write_smram(D_LCK | G_SMRAME | C_BASE_SEG); -} - void smm_setup_structures(void *gnvs, void *tcg, void *smi1) { /* The GDT or coreboot table is going to live here. But a long time diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 31eabb6..421a101 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -212,8 +212,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -void aseg_smm_lock(void); - #if defined(__PRE_RAM__) void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index ba2b028..cb79e96 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -431,7 +431,7 @@ * userspace applications to deceive us: */ if (CONFIG(HAVE_SMI_HANDLER) && CONFIG(SMM_ASEG)) - aseg_smm_lock(); + smm_lock(); } static void i82801ix_lpc_read_resources(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 0a80dd2..c02e823 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -30,6 +30,7 @@ #include "i82801ix.h" /* I945/GM45 */ + #define SMRAM 0x9d #define D_OPEN (1 << 6) #define D_CLS (1 << 5) @@ -126,6 +127,24 @@ static int smm_handler_copied = 0; +static void nb_smram_open(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG); +} + +static void nb_smram_close(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, G_SMRAME | C_BASE_SEG); +} + +void nb_smram_lock(void) +{ + struct device *mch = pcidev_on_root(0, 0); + pci_write_config8(mch, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); +} + static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -135,24 +154,20 @@ return; smm_handler_copied = 1; - /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_OPEN | G_SMRAME | C_BASE_SEG); + nb_smram_open(); /* copy the real SMM handler */ memcpy((void *)0xa0000, _binary_smm_start, _binary_smm_end - _binary_smm_start); wbinvd(); } - /* close the SMM memory window and enable normal SMM */ - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - G_SMRAME | C_BASE_SEG); + nb_smram_close(); } void smm_init(void) @@ -171,14 +186,3 @@ { restore_default_smm_area(default_smm_area); } - -void aseg_smm_lock(void) -{ - /* LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(pcidev_on_root(0, 0), SMRAM, - D_LCK | G_SMRAME | C_BASE_SEG); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/34875 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66983b771feb5c05744255b9000c742c4c0e5025 Gerrit-Change-Number: 34875 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

6 37

Change in libgfxinit[master]: gma panel: Report used timings
by Nico Huber (Code Review) 30 Jul '20

30 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/34472 ) Change subject: gma panel: Report used timings ...................................................................... gma panel: Report used timings Change-Id: If7a3b7ec755d85b9d570b8031ea4a2a31fe37514 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-panel.adb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/72/34472/1 diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index ba91254..bc0f7b8 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -141,7 +141,15 @@ if Delays (D) = 0 then Delays (D) := Default_EDP_Delays_US (D); Override := True; + + pragma Debug (Debug.Put ("PP: Using default ")); + else + pragma Debug (Debug.Put ("PP: Using preset ")); end if; + pragma Debug (Debug.Put (Delays_Enum'Image (D))); + pragma Debug (Debug.Put (" of ")); + pragma Debug (Debug.Put_Int32 (Int32 (Delays (D)))); + pragma Debug (Debug.Put_Line (" us.")); end loop; end Check_PP_Delays; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/34472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If7a3b7ec755d85b9d570b8031ea4a2a31fe37514 Gerrit-Change-Number: 34472 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 1

Change in libgfxinit[master]: gma panel: Also wait for `power cycle delay active`
by Nico Huber (Code Review) 30 Jul '20

30 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/34470 ) Change subject: gma panel: Also wait for `power cycle delay active` ...................................................................... gma panel: Also wait for `power cycle delay active` It's possible that the `power cycle progress` bits are only valid if no power-cycle delay is active. So let's check that bit, too. Also increase the timeouts to the theoretical maximum, including a pos- sibly ongoing sequence and the power-cycle delay. Change-Id: I536a094151c5cc5036c2d39a3d8d6e5826f198ac Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-panel.adb 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/70/34470/1 diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index 968fbbe..8ccbbb9 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -1,5 +1,6 @@ -- -- Copyright (C) 2015-2016 secunet Security Networks AG +-- Copyright (C) 2019 Nico Huber <nico.h(a)gmx.de> -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by @@ -305,8 +306,9 @@ Time.Delay_Until (Power_Up_Timer); Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, - Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK, - TOut_MS => 300); + Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK or + PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, + TOut_MS => 820 + 3_100 + 820); -- theoretical max: off + cycle + on Registers.Unset_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_VDD_OVERRIDE); end Wait_On; @@ -327,8 +329,9 @@ end if; Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, - Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK, - TOut_MS => 600); + Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK or + PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, + TOut_MS => 820 + 3_100 + 820); -- theoretical max: on + cycle + off if Was_On then Power_Cycle_Timer := Time.US_From_Now (Delays_US (Power_Cycle_Delay)); end if; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/34470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I536a094151c5cc5036c2d39a3d8d6e5826f198ac Gerrit-Change-Number: 34470 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 1

Change in libgfxinit[master]: gma panel: Add `Debug_Sts` flag to dump PP_STATUS register
by Nico Huber (Code Review) 30 Jul '20

30 Jul '20

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/34473 ) Change subject: gma panel: Add `Debug_Sts` flag to dump PP_STATUS register ...................................................................... gma panel: Add `Debug_Sts` flag to dump PP_STATUS register Change-Id: I68955ee315ddd25a58606ac3827257b6c716342e Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M common/hw-gfx-gma-panel.adb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/73/34473/1 diff --git a/common/hw-gfx-gma-panel.adb b/common/hw-gfx-gma-panel.adb index bc0f7b8..e8eb170 100644 --- a/common/hw-gfx-gma-panel.adb +++ b/common/hw-gfx-gma-panel.adb @@ -20,6 +20,8 @@ package body HW.GFX.GMA.Panel is + Debug_Sts : constant Boolean := True; + type Delays_Enum is (Power_Up_Delay, Power_Up_To_BL_On, @@ -252,6 +254,7 @@ procedure On (Wait : Boolean := True) is begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); Registers.Set_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_TARGET_ON); if Wait then @@ -262,6 +265,7 @@ procedure Wait_On is begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, @@ -269,22 +273,32 @@ PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, TOut_MS => 820 + 3_100 + 820); -- theoretical max: off + cycle + on + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); + Registers.Unset_Mask (Panel_PP_Regs.CONTROL, PCH_PP_CONTROL_VDD_OVERRIDE); + + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); end Wait_On; procedure Off is begin pragma Debug (Debug.Put_Line (GNAT.Source_Info.Enclosing_Entity)); + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); Registers.Unset_Mask (Register => Panel_PP_Regs.CONTROL, Mask => PCH_PP_CONTROL_TARGET_ON or PCH_PP_CONTROL_VDD_OVERRIDE); + + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); + Registers.Wait_Unset_Mask (Register => Panel_PP_Regs.STATUS, Mask => PCH_PP_STATUS_PWR_SEQ_PROGRESS_MASK or PCH_PP_STATUS_PWR_CYC_DELAY_ACTIVE, TOut_MS => 820 + 3_100 + 820); -- theoretical max: on + cycle + off + + pragma Debug (Debug_Sts, (Registers.Posting_Read (Panel_PP_Regs.STATUS))); end Off; ---------------------------------------------------------------------------- -- To view, visit https://review.coreboot.org/c/libgfxinit/+/34473 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I68955ee315ddd25a58606ac3827257b6c716342e Gerrit-Change-Number: 34473 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

2 1

Change in coreboot[master]: HACK trogdor: handle QCLib issue that breaks qup fw HACK
by mturney mturney (Code Review) 30 Jul '20

30 Jul '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37796 ) Change subject: HACK trogdor: handle QCLib issue that breaks qup fw HACK ...................................................................... HACK trogdor: handle QCLib issue that breaks qup fw HACK Change-Id: Id3bbcfef7c41609e26435697227617fbe5989f3e Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> --- M src/soc/qualcomm/sc7180/qclib.c 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/37796/1 diff --git a/src/soc/qualcomm/sc7180/qclib.c b/src/soc/qualcomm/sc7180/qclib.c index 9c05452..c7a1412 100644 --- a/src/soc/qualcomm/sc7180/qclib.c +++ b/src/soc/qualcomm/sc7180/qclib.c @@ -18,6 +18,15 @@ #include <console/console.h> #include <soc/symbols.h> #include <soc/qclib_common.h> +#include <soc/qcom_qup_se.h> +#include <soc/qupv3_spi.h> + +int qclib_post_fixup(void) +{ + qup_spi_init(QUPV3_0_SE0, 1010 * KHz); /* EC SPI */ + qup_spi_init(QUPV3_1_SE0, 1010 * KHz); /* H1 SPI */ + return 0; +} int qclib_soc_blob_load(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/37796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3bbcfef7c41609e26435697227617fbe5989f3e Gerrit-Change-Number: 37796 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: util/intelp2m: initial commit
by Maxim Polyakov (Code Review) 28 Jul '20

28 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35643 ) Change subject: util/intelp2m: initial commit ...................................................................... util/intelp2m: initial commit intelp2m - Intel Pad to Macro A small utility for converting a pad configuration from an inteltool dump to a PAD_CFG_ * macro coreboot. Tested on Asroch-H110M-DVS motherboard [2] [1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/33565 Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- A util/intelp2m/main.go A util/intelp2m/parser/parser.go A util/intelp2m/sunrise/dw.go A util/intelp2m/sunrise/macro.go 4 files changed, 871 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/35643/1 diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go new file mode 100644 index 0000000..0881e10 --- /dev/null +++ b/util/intelp2m/main.go @@ -0,0 +1,129 @@ +package main + +import ( + "flag" + "fmt" + "os" +) + +import "./parser" + +// HdrInfoAdd - adds license header to file f +func HdrInfoAdd(f *os.File) { + f.WriteString(`/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +`) +} + +// CreateHdrFile - generates include file +func CreateHdrFile() (err error) { + hrdFile, err := os.Create("generate/gpio.h") + if err != nil { + fmt.Printf("Error!\n") + return err + } + defer hrdFile.Close() + + HdrInfoAdd(hrdFile) + hrdFile.WriteString(`#ifndef PCH_GPIO_H +#define PCH_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +const struct pad_config *get_gpio_table(size_t *num); +const struct pad_config *get_early_gpio_table(size_t *num); + +#endif /* PCH_GPIO_H */ +`) + return nil +} + +// CreateGpioFile - generates gpio_raw.c file +// parser : parser data structure +// showRawDataFlag : raw data flag +// in the case when this flag is false, pad information will +// be create as macro +func CreateGpioFile(parser *parser.ParserData, showRawDataFlag bool) (err error) { + var name = "generate/gpio" + if showRawDataFlag { + name += "_raw" + } + name += ".c" + gpio, err := os.Create(name) + if err != nil { + fmt.Printf("Error!\n") + return err + } + defer gpio.Close() + + HdrInfoAdd(gpio) + gpio.WriteString(` +#include <commonlib/helpers.h> +#include "include/gpio.h" +`) + // Add the pads map to gpio.h file + parser.PadMapFprint(gpio, showRawDataFlag) + return nil +} + +// main +func main() { + // Command line arguments + wordPtr := flag.String("file", + "inteltool.log", + "the path to the inteltool log file") + dbgPtr := flag.Bool("dbg", false, "debug flag") + flag.Parse() + + fmt.Println("dbg:", *dbgPtr) + fmt.Println("file:", *wordPtr) + + var parser parser.ParserData + parser.DbgFlag = *dbgPtr + err := parser.Parse(*wordPtr) + if err != nil { + fmt.Printf("Parser: Error!\n") + os.Exit(1) + } + + // create dir for output files + err = os.MkdirAll("generate", os.ModePerm) + if err != nil { + fmt.Printf("Create a directory of generated files: Error!\n") + os.Exit(1) + } + + // gpio.h + err = CreateHdrFile() + if err != nil { + fmt.Printf("Create pch_gpio.h: Error!\n") + os.Exit(1) + } + + // gpio_raw.c + err = CreateGpioFile(&parser, true) + if err != nil { + fmt.Printf("Create gpio_raw.c: Error!\n") + os.Exit(1) + } + + // gpio.c with macros + err = CreateGpioFile(&parser, false) + if err != nil { + fmt.Printf("Create gpio.c: Error!\n") + os.Exit(1) + } +} diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go new file mode 100644 index 0000000..b684653 --- /dev/null +++ b/util/intelp2m/parser/parser.go @@ -0,0 +1,189 @@ +package parser + +import ( + "bufio" + "fmt" + "os" + "strings" +) + +import "../sunrise" + +// padInfo - information about pad +// id : pad id string +// offset : the offset of the register address relative to the base +// function : the string that means the pad function +// dw0 : DW0 register value +// dw1 : DW1 register value +type padInfo struct { + id string + offset uint16 + function string + community uint8 + dw0 uint32 + dw1 uint32 +} + +// add - add information about pad to data structure +// line : string from inteltool log file +func (info *padInfo) add(line string) { + var val uint64 + if strings.HasPrefix(line, "----") { + // ------- GPIO Group GPP_A ------- + // ------- GPIO Community 0 ------- + // Add header to define GPIO group or community + info.function = line + return + } + // 0x0520: 0x0000003c44000600 GPP_B12 SLP_S0# + // 0x0438: 0xffffffffffffffff GPP_C7 RESERVED + fmt.Sscanf(line, + "0x%x: 0x%x %s %s", + &info.offset, + &val, + &info.id, + &info.function) + info.dw0 = uint32(val & 0xffffffff) + info.dw1 = uint32(val >> 32) +} + +// titleFprint - print GPIO group title to file +// gpio : gpio.c file descriptor +func (info *padInfo) titleFprint(gpio *os.File) { + fmt.Fprintf(gpio, "\n\t/* %s */\n", info.function) +} + +// reservedFprint - print reserved GPIO to file as comment +// gpio : gpio.c file descriptor +func (info *padInfo) reservedFprint(gpio *os.File) { + // small comment about reserved port + fmt.Fprintf(gpio, "\t/* %s - %s */\n", info.id, info.function) +} + +// padInfoRawFprint - print information about current pad to file using +// raw format: +// _PAD_CFG_STRUCT(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ +// gpio : gpio.c file descriptor +func (info *padInfo) padInfoRawFprint(gpio *os.File) { + fmt.Fprintf(gpio, + "\t_PAD_CFG_STRUCT(%s, 0x%0.8x, 0x%0.8x), /* %s */\n", + info.id, + info.dw0, + (info.dw1 & 0xffffff00), // Interrupt Select - RO + info.function) +} + +// padInfoMacroFprint - print information about current pad to file using +// special macros: +// PAD_CFG_NF(GPP_F1, 20K_PU, PLTRST, NF1), /* SATAXPCIE4 */ +// gpio : gpio.c file descriptor +func (info *padInfo) padInfoMacroFprint(gpio *os.File) { + fmt.Fprintf(gpio, "\t/* %s - %s */\n\t%s\n", + info.id, + info.function, + sunrise.GetMacro(info.id, info.dw0, info.dw1)) +} + +// ParserData - global data +// padmap : pad info map +// dbgFlag : gebug flag, currently not used +type ParserData struct { + padmap []padInfo + DbgFlag bool +} + +// padInfoAdd - adds a new entry to pad info map +// line : string/line from the inteltool log file +// community : pads community number +func (parser *ParserData) padInfoAdd(line string, community uint8) { + pad := padInfo{community : community} + pad.add(line) + parser.padmap = append(parser.padmap, pad) +} + +// getCommunity - scans the string and returns the pads community number +// line : string from inteltool log file +// return +// community number +func (parser *ParserData) getCommunity(line string) uint8 { + var comm uint8 + fmt.Sscanf(line, "------- GPIO Community %d -------", &comm) + return comm +} + +// PadMapFprint - print pad info map to file +// gpio : gpio.c descriptor file +// raw : in the case when this flag is false, pad information will be print +// as macro +func (parser *ParserData) PadMapFprint(gpio *os.File, raw bool) { + gpio.WriteString("\n/* Pad configuration in ramstage */\n") + gpio.WriteString("static const struct pad_config gpio_table[] = {\n") + for _, pad := range parser.padmap { + switch pad.dw0 { + case 0: + pad.titleFprint(gpio) + case 0xffffffff: + pad.reservedFprint(gpio) + default: + if raw { + pad.padInfoRawFprint(gpio) + } else { + pad.padInfoMacroFprint(gpio) + } + } + } + gpio.WriteString("};\n") + + // FIXME: need to add early configuration + gpio.WriteString(`/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* TODO: Add early pad configuration */ +}; + +const struct pad_config *get_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *get_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +`) +} + +// Parse pads groupe information in the inteltool log file +// logFile : name of inteltool log file +// return +// err : error +func (parser *ParserData) Parse(logFile string) (err error) { + file, err := os.Open(logFile) + if err != nil { + return err + } + defer file.Close() + + // Read all lines from inteltool log file + fmt.Println("Parse IntelTool Log File...") + scanner := bufio.NewScanner(file) + var line string + var community uint8 = 0 + for scanner.Scan() { + line = scanner.Text() + // Use only the string that contains the GPP information + if !strings.Contains(line, "GPP_") && !strings.Contains(line, "GPD") { + // ------- GPIO Community 0 ------- + if strings.Contains(line, "Community") { + community = parser.getCommunity(line) + } else { + continue + } + } + parser.padInfoAdd(line, community) + } + fmt.Println("...done!") + return nil +} \ No newline at end of file diff --git a/util/intelp2m/sunrise/dw.go b/util/intelp2m/sunrise/dw.go new file mode 100644 index 0000000..f3623b0 --- /dev/null +++ b/util/intelp2m/sunrise/dw.go @@ -0,0 +1,198 @@ +package sunrise + +// Bit field constants for DW0 register +const ( + padRstCfgShift uint8 = 30 + padRstCfgMask uint32 = 0x3 << padRstCfgShift + + rxPadStateSelectShift uint8 = 29 + rxPadStateSelectMask uint32 = 0x1 << rxPadStateSelectShift + + rxRawOverrideTo1Shift uint8 = 28 + rxRawOverrideTo1Mask uint32 = 0x1 << rxRawOverrideTo1Shift + + rxLevelEdgeConfigurationShift uint8 = 25 + rxLevelEdgeConfigurationMask uint32 = 0x3 << rxLevelEdgeConfigurationShift + + rxInvertShift uint8 = 23 + rxInvertMask uint32 = 0x1 << rxInvertShift + + gpioInputRouteIOxApicShift uint8 = 20 + gpioInputRouteIOxApicMask uint32 = 0x1 << gpioInputRouteIOxApicShift + + gpioInputRouteSCIShift uint8 = 19 + gpioInputRouteSCIMask uint32 = 0x1 << gpioInputRouteSCIShift + + gpioInputRouteSMIShift uint8 = 18 + gpioInputRouteSMIMask uint32 = 0x1 << gpioInputRouteSMIShift + + gpioInputRouteNMIShift uint8 = 17 + gpioInputRouteNMIMask uint32 = 0x1 << gpioInputRouteNMIShift + + padModeShift uint8 = 10 + padModeMask uint32 = 0x7 << padModeShift + + gpioRxTxDisableShift uint8 = 8 + gpioRxTxDisableMask uint32 = 0x3 << gpioRxTxDisableShift + + gpioRxStateShift uint8 = 1 + gpioRxStateMask uint32 = 0x1 << gpioRxStateShift + + gpioTxStateMask uint32 = 0x1 +) + +// Bit field constants for DW1 register +const ( + termShift uint8 = 10 + termMask uint32 = 0xF << termShift + interruptSelectShift uint32 = 0xFF +) + +// Maximum numbers of the config DW register for Sunrise chipset +const ( + MaxDWNum = 2 +) + +// dwcfg - configuration data structure based on DW0/1 reg value +// reg : register value +// mask : bit fileds mask +type dwcfg struct { + reg [MaxDWNum]uint32 + mask [MaxDWNum]uint32 +} + +// getResetConfig - get Reset Configuration from PADRSTCFG field in PAD_CFG_DW0_GPx register +func (dw *dwcfg) getFieldVal(regNum uint8, mask uint32, shift uint8) uint8 { + if regNum < MaxDWNum { + dw.mask[regNum] |= mask + return uint8((dw.reg[regNum] & mask) >> shift) + } + return 0 +} + +// Check the mask of the new macro +// regNum : DW register number +// Returns true if the macro is generated correctly +func (dw *dwcfg) maskCheck(regNum uint8) bool { + if regNum >= MaxDWNum { + return false + } + + // Take into account the bits that are read-only + readonly := [MaxDWNum]uint32{ + (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfe, + 0xfffffc3f, + } + mask := ^(dw.mask[regNum] | readonly[regNum]) + return dw.reg[regNum]&mask == 0 +} + +// Fix Pad Reset Config field in mask for DW0 register +// Returns *dwcfg +func (dw *dwcfg) maskResetFix() *dwcfg { + dw.mask[0] |= padRstCfgMask + return dw +} + +// Fix RX Level/Edge Configuration field in mask for DW0 register +// Returns *dwcfg +func (dw *dwcfg) maskTrigFix() *dwcfg { + dw.mask[0] |= rxLevelEdgeConfigurationMask + return dw +} + +// getResetConfig - returns type reset source for corresponding pad +// PADRSTCFG field in PAD_CFG_DW0 register +// 00 = RSMRST#, 01 = DEEP#, 10 = PLTRST#, 11 = RSMRST# for GPDx pads +// and Reserved for others +func (dw *dwcfg) getResetConfig() uint8 { + return dw.getFieldVal(0, padRstCfgMask, padRstCfgShift) +} + +// getRXPadStateSelect - returns RX Pad State (RXINV) +// 0 = Raw RX pad state directly from RX buffer +// 1 = Internal RX pad state +func (dw *dwcfg) getRXPadStateSelect() uint8 { + return dw.getFieldVal(0, rxPadStateSelectMask, rxPadStateSelectShift) +} + +// getRXRawOverrideStatus - returns 1 if the selected pad state is being +// overridden to '1' (RXRAW1 field) +func (dw *dwcfg) getRXRawOverrideStatus() uint8 { + return dw.getFieldVal(0, rxRawOverrideTo1Mask, rxRawOverrideTo1Shift) +} + +// getRXLevelEdgeConfiguration - returns RX Level/Edge Configuration (RXEVCFG) +// 0h = Level, 1h = Edge, 2h = Drive '0', 3h = Reserved (implement as setting 0h) +func (dw *dwcfg) getRXLevelEdgeConfiguration() uint8 { + return dw.getFieldVal(0, rxLevelEdgeConfigurationMask, rxLevelEdgeConfigurationShift) +} + +// getRXLevelConfiguration - returns RX Invert state (RXINV) +// 1 - Inversion, 0 - No inversion +func (dw *dwcfg) getRXLevelConfiguration() bool { + return dw.getFieldVal(0, rxInvertMask, rxInvertShift) != 0 +} + +// getGPIOInputRouteIOxAPIC - returns 1 if the pad can be routed to cause +// peripheral IRQ when configured in GPIO input mode. +func (dw *dwcfg) getGPIOInputRouteIOxAPIC() bool { + return dw.getFieldVal(0, gpioInputRouteIOxApicMask, gpioInputRouteIOxApicShift) != 0 +} + +// getGPIOInputRouteSCI - returns 1 if the pad can be routed to cause SCI when +// configured in GPIO input mode. +func (dw *dwcfg) getGPIOInputRouteSCI() bool { + return dw.getFieldVal(0, gpioInputRouteSCIMask, gpioInputRouteSCIShift) != 0 +} + +// getGPIOInputRouteSMI - returns 1 if the pad can be routed to cause SMI when +// configured in GPIO input mode +func (dw *dwcfg) getGPIOInputRouteSMI() bool { + return dw.getFieldVal(0, gpioInputRouteSMIMask, gpioInputRouteSMIShift) != 0 +} + +// getGPIOInputRouteNMI - returns 1 if the pad can be routed to cause NMI when +// configured in GPIO input mode +func (dw *dwcfg) getGPIOInputRouteNMI() bool { + return dw.getFieldVal(0, gpioInputRouteNMIMask, gpioInputRouteNMIShift) != 0 +} + +// getPadMode - reutrns pad mode or one of the native functions +// 0h = GPIO control the Pad. +// 1h = native function 1, if applicable, controls the Pad +// 2h = native function 2, if applicable, controls the Pad +// 3h = native function 3, if applicable, controls the Pad +// 4h = enable GPIO blink/PWM capability if applicable +func (dw *dwcfg) getPadMode() uint8 { + return dw.getFieldVal(0, padModeMask, padModeShift) +} + +// getGPIORxTxDisableStatus - returns GPIO RX/TX buffer state (GPIORXDIS | GPIOTXDIS) +// 0 - both are enabled, 1 - TX Disable, 2 - RX Disable, 3 - both are disabled +func (dw *dwcfg) getGPIORxTxDisableStatus() uint8 { + return dw.getFieldVal(0, gpioRxTxDisableMask, gpioRxTxDisableShift) +} + +// getGPIORXState - returns GPIO RX State (GPIORXSTATE) +func (dw *dwcfg) getGPIORXState() uint8 { + return dw.getFieldVal(0, gpioRxStateMask, gpioRxStateShift) +} + +// getGPIOTXState - returns GPIO TX State (GPIOTXSTATE) +func (dw *dwcfg) getGPIOTXState() int { + return int(dw.getFieldVal(0, gpioTxStateMask, 0)) +} + +// getTermination - returns the pad termination state defines the different weak +// pull-up and pull-down settings that are supported by the buffer +// 0000 = none; 0010 = 5k PD; 0100 = 20k PD; 1010 = 5k PU; 1100 = 20k PU; +// 1111 = Native controller selected +func (dw *dwcfg) getTermination() uint8 { + return dw.getFieldVal(1, termMask, termShift) +} + +// getInterruptSelect - returns Interrupt Line number from the GPIO controller +func (dw *dwcfg) getInterruptSelect() uint8 { + return dw.getFieldVal(1, interruptSelectShift, 0) +} diff --git a/util/intelp2m/sunrise/macro.go b/util/intelp2m/sunrise/macro.go new file mode 100644 index 0000000..7489709 --- /dev/null +++ b/util/intelp2m/sunrise/macro.go @@ -0,0 +1,355 @@ +package sunrise + +import ( + "fmt" + "strconv" + "strings" +) + +// macro - contains macro information and methods +// padID : pad ID string +// str : macro string entirely +// dwcfg : configuration data structure +type macro struct { + padID string + str string + dwcfg +} + +// dw - returns dwcfg data configuration structure with PAD_CFG_DW0/1 register +// values +func (macro *macro) dw() *dwcfg { + return &macro.dwcfg +} + +// add a string to macro +func (macro *macro) add(str string) *macro { + macro.str += str + return macro +} + +// set a string in a macro instead of its previous contents +func (macro *macro) set(str string) *macro { + macro.str = str + return macro +} + +// get macro string +func (macro *macro) get() string { + return macro.str +} + +// Adds PAD Id to the macro as a new argument +// return: macro +func (macro *macro) id() *macro { + return macro.add(macro.padID) +} + +// Add separator to macro if needed +func (macro *macro) separator() *macro { + str := macro.get() + c := str[len(str)-1] + if c != '(' && c != '_' { + macro.add(", ") + } + return macro +} + +// Adds the PADRSTCFG parameter from DW0 to the macro as a new argument +// return: macro +func (macro *macro) rstsrc() *macro { + var resetSrc = map[uint8]string{ + 0x0: "PWROK", + 0x1: "DEEP", + 0x2: "PLTRST", + } + str, valid := resetSrc[macro.dw().getResetConfig()] + if !valid { + // Pad Reset Config field in DW0 register should implements 3h value + // as RSMRST for GPD pads group, but this value is reserved for other + // groups + if strings.Contains(macro.padID, "GPD") { + str = "RSMRST" + } else { + str = resetSrc[0] + fmt.Println("Warning:", macro.padID, "PADRSTCFG = 3h Reserved") + fmt.Println("It is implemented as setting 0h (PWROK) for Sunrise PCH") + } + } + return macro.separator().add(str) +} + +// Adds The Pad Termination (TERM) parameter from DW1 to the macro as a new argument +// return: macro +func (macro *macro) pull() *macro { + var pull = map[uint8]string{ + 0x0: "NONE", + 0x2: "5K_PD", + 0x4: "20K_PD", + 0x9: "1K_PU", + 0xa: "5K_PU", + 0xb: "2K_PU", + 0xc: "20K_PU", + 0xd: "667_PU", + 0xf: "NATIVE", + } + str, valid := pull[macro.dw().getTermination()] + if !valid { + str = "INVALID" + fmt.Println("Error", + macro.padID, + " invalid TERM value = ", + int(macro.dw().getTermination())) + } + return macro.separator().add(str) +} + +// Adds Pad GPO value to macro string as a new argument +// return: macro +func (macro *macro) val() *macro { + return macro.separator().add(strconv.Itoa(macro.dw().getGPIOTXState())) +} + +// Adds Pad GPO value to macro string as a new argument +// return: macro +func (macro *macro) trig() *macro { + var dw = macro.dw() + var trig = map[uint8]string{ + 0x0: "LEVEL", + 0x1: "EDGE_SINGLE", + 0x2: "OFF", + 0x3: "EDGE_BOTH", + } + return macro.separator().add(trig[dw.getRXLevelEdgeConfiguration()]) +} + +// Adds Pad Polarity Inversion Stage (RXINV) to macro string as a new argument +// return: macro +func (macro *macro) invert() *macro { + macro.separator() + if macro.dw().getRXLevelConfiguration() { + return macro.add("YES") + } + return macro.add("NONE") +} + +// Adds input/output buffer state +// return: macro +func (macro *macro) bufdis() *macro { + var buffDisStat = map[uint8]string{ + 0x0: "NO_DISABLE", // both buffers are enabled + 0x1: "TX_DISABLE", // output buffer is disabled + 0x2: "RX_DISABLE", // input buffer is disabled + 0x3: "TX_RX_DISABLE", // both buffers are disabled + } + state := macro.dw().getGPIORxTxDisableStatus() + return macro.separator().add(buffDisStat[state]) +} + +//Adds pad native function (PMODE) as a new argument +//return: macro +func (macro *macro) padfn() *macro { + nfnum := int(macro.dw().getPadMode()) + if nfnum != 0 { + return macro.separator().add("NF" + strconv.Itoa(nfnum)) + } + // GPIO used only for PAD_FUNC(x) macro + return macro.add("GPIO") +} + +// Adds suffix to GPI macro with arguments +func (macro *macro) addSuffixInput() { + dw := macro.dw() + isEdge := dw.getRXLevelEdgeConfiguration() + macro.add("_GPI") + switch { + case dw.getGPIOInputRouteNMI(): + // e.g. PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT), + macro.add("_NMI").add("(").id().pull().rstsrc().trig().invert() + + case dw.getGPIOInputRouteIOxAPIC(): + // e.g. PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST) + macro.add("_APIC") + if isEdge == 0 { + if dw.getRXLevelConfiguration() { + // e.g. PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP), + macro.add("_INVERT") + } + macro.add("(").id().pull().rstsrc() + } else { + // PAD_CFG_GPI_APIC_IOS(GPP_C20, NONE, DEEP, LEVEL, INVERT, + // TxDRxE, DISPUPD) macro isn't used for this chipset. But, in + // the case when SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS is + // defined in the config, this macro allows you to set trig and + // invert parameters. + macro.add("_IOS").add("(").id().pull().rstsrc().trig().invert() + // IOStandby Config will be ignored for the Sunrise PCH, so use + // any values + macro.add(", TxDRxE, DISPUPD") + } + + case dw.getGPIOInputRouteSCI(): + + // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), + if (isEdge & 0x1) != 0 { + // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), + macro.add("_ACPI") + } + macro.add("_SCI").add("(").id().pull().rstsrc() + if (isEdge & 0x1) == 0 { + macro.trig() + } + macro.invert() + + case dw.getGPIOInputRouteSMI(): + if (isEdge & 0x1) != 0 { + // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), + macro.add("_ACPI") + } + macro.add("_SMI").add("(").id().pull().rstsrc().invert() + + case isEdge != 0: + // e.g. ISH_SPI_CS# + // PAD_CFG_GPI_INT(GPP_D9, NONE, PLTRST, EDGE), + macro.add("_INT").add("(").id().pull().rstsrc().trig() + + default: + // e.g. PAD_CFG_GPI(GPP_A7, NONE, DEEP), + macro.add("(").id().pull().rstsrc() + } +} + +// Adds suffix to GPO macro with arguments +func (macro *macro) addSuffixOutput() { + term := macro.dw().getTermination() + // FIXME: don`t understand how to get PAD_CFG_GPI_GPIO_DRIVER(..) + if term != 0 { + // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + macro.add("_TERM") + } + macro.add("_GPO").add("(").id().val() + if term != 0 { + macro.pull() + } + macro.rstsrc() + + // Fix mask for RX Level/Edge Configuration (RXEVCFG) + // See https://github.com/coreboot/coreboot/commit/3820e3c + macro.dw().maskTrigFix() +} + +const ( + rxDisable uint8 = 0x2 + txDisable uint8 = 0x1 +) + +// Set common macros macros if the standard ones can't define the values from +// the DW0/1 register +func (macro *macro) common() *macro { + macro.set("_PAD_CFG_STRUCT(").id(). + add(",\n\t\tPAD_FUNC(").padfn(). + add(") | PAD_RESET(").rstsrc().add(") |\n\t\t") + + var str string + var argument = true + switch dw := macro.dw(); { + case dw.getGPIOInputRouteIOxAPIC(): + str = "IOAPIC" + case dw.getGPIOInputRouteSCI(): + str = "SCI" + case dw.getGPIOInputRouteSMI(): + str = "SMI" + case dw.getGPIOInputRouteNMI(): + str = "NMI" + default: + argument = false + } + + if argument { + macro.add("PAD_IRQ_CFG(").add(str).trig().invert().add(")") + } else { + macro.add("PAD_CFG0_TRIG_").trig().add(" | PAD_CFG0_RX_POL_").invert() + } + + macro.add(" |\n\t\t").add("PAD_BUF(").bufdis().add(")") + if macro.dw().getGPIOTXState() != 0 { + macro.add(" | 1") + } + return macro.add(",\n\t\tPAD_PULL(").pull().add(")),") +} + +// Check created macro +func (macro *macro) check() { + if !macro.dw().maskCheck(0) { + macro.common() + // Debug message about this + fmt.Printf( + "\nCoreboot macros can't define the configuration for pad: %s\n", + macro.padID) + fmt.Printf("Use %s\n", macro.get()) + } +} + +// Gets base string of current macro +// return: string of macro +// error +func (macro *macro) generate(id string, dw0 uint32, dw1 uint32) string { + macro.dwcfg.reg[0] = dw0 + macro.dwcfg.reg[1] = dw1 + dw := &macro.dwcfg + + macro.set("PAD_CFG") + if dw.getPadMode() == 0 { + // GPIO + switch dw.getGPIORxTxDisableStatus() { + case rxDisable: + // GPI + macro.addSuffixInput() + + case txDisable: + // GPO + macro.addSuffixOutput() + + case rxDisable | txDisable: + // NC + macro.set("PAD_NC").add("(").id().pull() + // Fix mask for RX Level/Edge Configuration (RXEVCFG) + // and Pad Reset Config (PADRSTCFG) + // There is no need to check these fields if the pad + // is in the NC state + macro.dw().maskResetFix().maskTrigFix() + + default: + // In case the rule isn't found, a common macro is used + // to create the pad configuration + return macro.common().get() + } + } else { + isEdge := dw.getRXLevelEdgeConfiguration() != 0 + isTxRxBufDis := dw.getGPIORxTxDisableStatus() != 0 + // e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1) + macro.add("_NF") + if isEdge || isTxRxBufDis { + // e.g. PCHHOT# + // PAD_CFG_NF_BUF_TRIG(GPP_B23, 20K_PD, PLTRST, NF2, RX_DIS, OFF), + macro.add("_BUF_TRIG") + } + macro.add("(").id().pull().rstsrc().padfn() + if isEdge || isTxRxBufDis { + macro.bufdis().trig() + } + } + macro.add("),") + macro.check() + return macro.get() +} + +// GetMacro - get pad macro +// dw0 : DW0 config register value +// dw1 : DW1 config register value +// return: string of macro +// error +func GetMacro(id string, dw0 uint32, dw1 uint32) string { + macro := macro{padID : id} + return macro.generate(id, dw0, dw1) +} -- To view, visit https://review.coreboot.org/c/coreboot/+/35643 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3e3b523c4f63dc2f91e9ccd16934e3a1b6e21fa Gerrit-Change-Number: 35643 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

10 61

Change in coreboot[master]: arch/x86: Top align bootblock program
by Kyösti Mälkki (Code Review) 28 Jul '20

28 Jul '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37895 ) Change subject: arch/x86: Top align bootblock program ...................................................................... arch/x86: Top align bootblock program Change-Id: If32518b1c19d08935727330314904b52a246af3c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/bootblock_crt0.S M src/arch/x86/memlayout.ld D src/arch/x86/prologue.inc M src/arch/x86/walkcbfs.S M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/microcode/microcode_asm.S M src/cpu/x86/16bit/entry16.inc M src/cpu/x86/16bit/reset16.ld M src/drivers/amd/agesa/cache_as_ram.S M src/soc/amd/common/block/cpu/car/cache_as_ram.S 13 files changed, 68 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/37895/1 diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S index 3256731..d4dbf28 100644 --- a/src/arch/x86/bootblock_crt0.S +++ b/src/arch/x86/bootblock_crt0.S @@ -25,7 +25,9 @@ * Include the old code for reset vector and protected mode entry. That code has * withstood the test of time. */ -#include <arch/x86/prologue.inc> + +.section ".bootblock.top", "ax", @progbits + #include <cpu/x86/16bit/entry16.inc> #include <cpu/x86/16bit/reset16.inc> #include <cpu/x86/32bit/entry32.inc> @@ -69,3 +71,5 @@ /* We're done. Now it's up to platform-specific code */ jmp bootblock_pre_c_entry + +.previous diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld index eff3738..38c4664 100644 --- a/src/arch/x86/memlayout.ld +++ b/src/arch/x86/memlayout.ld @@ -49,8 +49,6 @@ #include EARLY_MEMLAYOUT #elif ENV_BOOTBLOCK - BOOTBLOCK(CONFIG_X86_RESET_VECTOR - CONFIG_C_ENV_BOOTBLOCK_SIZE + 0x10, - CONFIG_C_ENV_BOOTBLOCK_SIZE) #include EARLY_MEMLAYOUT diff --git a/src/arch/x86/prologue.inc b/src/arch/x86/prologue.inc deleted file mode 100644 index 4036ff9..0000000 --- a/src/arch/x86/prologue.inc +++ /dev/null @@ -1,17 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cpu/x86/post_code.h> - -.section ".rom.data", "a", @progbits -.section ".rom.text", "ax", @progbits diff --git a/src/arch/x86/walkcbfs.S b/src/arch/x86/walkcbfs.S index ded6558..82fd077 100644 --- a/src/arch/x86/walkcbfs.S +++ b/src/arch/x86/walkcbfs.S @@ -31,7 +31,7 @@ #define CBFS_FILE_STRUCTSIZE (CBFS_FILE_OFFSET + 4) -.section .text +.section ".bootblock.top" .global walkcbfs_asm /* @@ -131,3 +131,5 @@ filemagic: .ascii "LARCHIVE" + +.previous diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index 73618d9..65db322 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -23,6 +23,7 @@ #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +.section ".bootblock.top" .global bootblock_pre_c_entry .code32 @@ -210,3 +211,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 4dee0a8..00e7b4f 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -22,6 +22,7 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e +.section ".bootblock.top" .global bootblock_pre_c_entry .code32 @@ -254,3 +255,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 5262b18..94540ca 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -23,6 +23,7 @@ #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +.section ".bootblock.top" .global bootblock_pre_c_entry .code32 @@ -198,3 +199,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fdeb0af..8a21b48 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -27,6 +27,7 @@ #endif #define XIP_ROM_SIZE CONFIG_C_ENV_BOOTBLOCK_SIZE +.section ".bootblock.top" .global bootblock_pre_c_entry .code32 @@ -409,3 +410,4 @@ fixed_mtrr_list_size = . - fixed_mtrr_list _cache_as_ram_setup_end: +.previous diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 647f67c..2458185 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -54,7 +54,7 @@ * if the revision of the update is newer than what is installed */ -.section .text +.section ".bootblock.top" .global update_bsp_microcode update_bsp_microcode: @@ -162,3 +162,5 @@ .string "cpu_microcode_blob.bin" _update_bsp_microcode_end: + +.previous diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 40c0e99..b1aaa10 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -28,11 +28,11 @@ */ #include <arch/rom_segs.h> +#include <cpu/x86/post_code.h> -/* Symbol _start16bit must be aligned to 4kB to start AP CPUs with - * Startup IPI message without RAM. +/* Symbol _start16bit must reachable from the reset vector, and be aligned to + * 4kB to start AP CPUs with Startup IPI message without RAM. */ -.align 4096 .code16 .globl _start16bit .type _start16bit, @function diff --git a/src/cpu/x86/16bit/reset16.ld b/src/cpu/x86/16bit/reset16.ld index ec01810..56672e8 100644 --- a/src/cpu/x86/16bit/reset16.ld +++ b/src/cpu/x86/16bit/reset16.ld @@ -14,9 +14,35 @@ /* _RESET_VECTOR: typically the top of the ROM */ SECTIONS { - /* Trigger an error if I have an unuseable start address */ - _TOO_LOW = CONFIG_X86_RESET_VECTOR - 0xfff0; - _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); + + /* + * Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs + * with Startup IPI message without RAM. Align .rom to next 4 byte + * boundary anyway. + */ + + .bogus ROMLOC_MIN : { + . = ALIGN(4); + } + + INCLUDE "bootblock/lib/program.ld" + + .bootblock_top . : { + . = CONFIG(SIPI_VECTOR_IN_ROM) ? ALIGN(4096) : ALIGN(4); + _realmode = .; + *(.bootblock.top); + _erealmode = .; + } + + PROGRAM_SZ = (_eprogram - _program + 16); + EARLYASM_SZ = (_erealmode - _realmode + 16) + (CONFIG(SIPI_VECTOR_IN_ROM) ? 4096 : 0); + + /* + * Allocation reserves extra 16 bytes here. Alignment requirements + * may cause the total size of a section to change when the start + * address gets applied. + */ + ROMLOC_MIN = CONFIG_X86_RESET_VECTOR - 0xf0 - (PROGRAM_SZ + EARLYASM_SZ); . = CONFIG_X86_RESET_VECTOR; .reset . : { diff --git a/src/drivers/amd/agesa/cache_as_ram.S b/src/drivers/amd/agesa/cache_as_ram.S index 1034992..d436805 100644 --- a/src/drivers/amd/agesa/cache_as_ram.S +++ b/src/drivers/amd/agesa/cache_as_ram.S @@ -21,16 +21,19 @@ ****************************************************************************** */ -#include "gcccar.inc" #include <cpu/x86/lapic_def.h> #include <cpu/x86/post_code.h> +.section ".bootblock.top" + .code32 .globl _cache_as_ram_setup, _cache_as_ram_setup_end .global bootblock_pre_c_entry _cache_as_ram_setup: +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -84,3 +87,4 @@ jmp stop _cache_as_ram_setup_end: +.previous diff --git a/src/soc/amd/common/block/cpu/car/cache_as_ram.S b/src/soc/amd/common/block/cpu/car/cache_as_ram.S index 402da3a..e64b6d2 100644 --- a/src/soc/amd/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/amd/common/block/cpu/car/cache_as_ram.S @@ -21,10 +21,18 @@ ****************************************************************************** */ -#include "gcccar.inc" #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +.section ".bootblock.top" + +.code32 +.globl _cache_as_ram_setup, _cache_as_ram_setup_end + +_cache_as_ram_setup: + +#include "gcccar.inc" + /* * on entry: * mm0: BIST (ignored) @@ -57,3 +65,6 @@ post_code(POST_DEAD_CODE) hlt jmp .halt_forever + +_cache_as_ram_setup_end: +.previous -- To view, visit https://review.coreboot.org/c/coreboot/+/37895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If32518b1c19d08935727330314904b52a246af3c Gerrit-Change-Number: 37895 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

7 29

Change in coreboot[master]: [TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m
by Maxim Polyakov (Code Review) 24 Jul '20

24 Jul '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35679 ) Change subject: [TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m ...................................................................... [TEST] mb/supermicro/x11-lga1151-series: rewrite gpio.h using intelp2m gpio.h was generated using the Intel Pad 2 Macro utility (intelp2m) [1] Please review and test coreboot image with this patch [1] https://review.coreboot.org/c/coreboot/+/35643 These changes are not tested on real hardware. Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h 1 file changed, 213 insertions(+), 213 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/35679/1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index a5eed6b..5320298 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -21,210 +21,210 @@ #ifndef __ACPI__ static const struct pad_config gpio_table[] = { -/* RCIN# */ _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x00000000), -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* PIRQA# */ _PAD_CFG_STRUCT(GPP_A7, 0x44000702, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), -/* PME# */ _PAD_CFG_STRUCT(GPP_A11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A12, 0x80080201, 0x00000000), -/* SUSWARN# */ _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x00000000), -/* SUS_STAT# */ _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x00000000), -/* SUS_ACK# */ _PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x00000000), -/* CLKOUT_48 */ _PAD_CFG_STRUCT(GPP_A16, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A18, 0x84000100, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B4, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B5, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B6, 0x84000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B7, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B8, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B9, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B10, 0x44000301, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B11, 0x44000200, 0x00000000), -/* SLP_S0# */ _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x00000000), -/* PLTRST# */ _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x00000000), -/* SPKR */ _PAD_CFG_STRUCT(GPP_B14, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_B22, 0x44000300, 0x00000000), -/* PCHHOT# */ _PAD_CFG_STRUCT(GPP_B23, 0x40000b00, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C2, 0x44000300, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C5, 0x44000201, 0x00000000), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */ //_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C8, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C9, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C10, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C14, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C22, 0x42040102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_C23, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D0, 0x84000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D1, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D2, 0x42020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D4, 0x84000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D12, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D18, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D21, 0x44000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D22, 0x04000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x00000000), -/* SATAXPCIE0 */ _PAD_CFG_STRUCT(GPP_E0, 0x44000502, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E6, 0x82020102, 0x00003000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x00000000), -/* SATA_LED# */ _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x00000000), -/* USB_OC0# */ _PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x00000000), -/* USB_OC1# */ _PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x00000000), -/* USB_OC2# */ _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x00000000), -/* USB_OC3# */ _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F0, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F1, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F2, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F3, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F5, 0x80100102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F9, 0x84000102, 0x00000000), -/* SATA_SCLOCK */ _PAD_CFG_STRUCT(GPP_F10, 0x44000700, 0x00000000), -/* SATA_SLOAD */ _PAD_CFG_STRUCT(GPP_F11, 0x44000700, 0x00000000), -/* SATA_SDATAOUT1 */ _PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x00000000), -/* SATA_SDATAOUT2 */ _PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x00000000), -/* USB_OC4# */ _PAD_CFG_STRUCT(GPP_F15, 0x44000702, 0x00000000), -/* USB_OC5# */ _PAD_CFG_STRUCT(GPP_F16, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_F23, 0x04000200, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G0, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G1, 0x44000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G2, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G3, 0x44000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G8, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G9, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G10, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G11, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G12, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G13, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G14, 0x84000102, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G15, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G16, 0x84000100, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G17, 0x44000300, 0x00000000), -/* NMI# */ _PAD_CFG_STRUCT(GPP_G18, 0x44000700, 0x00000000), -/* SMI# */ _PAD_CFG_STRUCT(GPP_G19, 0x44000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G20, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G21, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G22, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_G23, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H0, 0x44000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H1, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H2, 0x44000201, 0x00000000), -/* SRCCLKREQ9# */ _PAD_CFG_STRUCT(GPP_H3, 0x44000602, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H4, 0x84000103, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H5, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H6, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H7, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H8, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H9, 0x84000201, 0x00000000), -/* SML2CLK */ _PAD_CFG_STRUCT(GPP_H10, 0x44000702, 0x00000000), -/* SML2DATA */ _PAD_CFG_STRUCT(GPP_H11, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H12, 0x44000300, 0x00000000), -/* SML3CLK */ _PAD_CFG_STRUCT(GPP_H13, 0x44000702, 0x00000000), -/* SML3DATA */ _PAD_CFG_STRUCT(GPP_H14, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x00000000), -/* SML4CLK */ _PAD_CFG_STRUCT(GPP_H16, 0x44000702, 0x00000000), -/* SML4DATA */ _PAD_CFG_STRUCT(GPP_H17, 0x44000702, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H20, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H21, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_H23, 0x84000201, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD0, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD1, 0x04000300, 0x00000000), -/* LAN_WAKE# */ _PAD_CFG_STRUCT(GPD2, 0x04000702, 0x00000000), -/* PWRBTN# */ _PAD_CFG_STRUCT(GPD3, 0x04000702, 0x00000000), -/* SLP_S3# */ _PAD_CFG_STRUCT(GPD4, 0x04000700, 0x00000000), -/* SLP_S4# */ _PAD_CFG_STRUCT(GPD5, 0x04000700, 0x00000000), -/* SLP_A# */ _PAD_CFG_STRUCT(GPD6, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD7, 0x04000301, 0x00000000), -/* SUSCLK */ _PAD_CFG_STRUCT(GPD8, 0x04000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD9, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD10, 0x04000300, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPD11, 0x04000300, 0x00000000), -/* DDPB_HPD0 */ _PAD_CFG_STRUCT(GPP_I0, 0x44000700, 0x00000000), -/* DDPC_HPD1 */ _PAD_CFG_STRUCT(GPP_I1, 0x44000700, 0x00000000), -/* DDPD_HPD2 */ _PAD_CFG_STRUCT(GPP_I2, 0x44000700, 0x00000000), -/* DDPE_HPD3 */ _PAD_CFG_STRUCT(GPP_I3, 0x84000700, 0x00000000), -/* GPIO */ _PAD_CFG_STRUCT(GPP_I4, 0x44000300, 0x00000000), -/* DDPB_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I5, 0x44000700, 0x00000000), -/* DDPB_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I6, 0x44000700, 0x00000000), -/* DDPC_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I7, 0x44000700, 0x00000000), -/* DDPC_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I8, 0x44000700, 0x00000000), -/* DDPD_CTRLCLK */ _PAD_CFG_STRUCT(GPP_I9, 0x44000700, 0x00000000), -/* DDPD_CTRLDATA */ _PAD_CFG_STRUCT(GPP_I10, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_A0, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* RCIN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A7, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PIRQA# */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PME# */ + PAD_CFG_GPO(GPP_A12, 1, PLTRST), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_A13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUSWARN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A14, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUS_STAT# */ + PAD_CFG_NF_BUF_TRIG(GPP_A15, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SUS_ACK# */ + PAD_CFG_NF_BUF_TRIG(GPP_A16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_48 */ + PAD_NC(GPP_A17, NONE), /* GPIO */ + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), /* GPIO */ + _PAD_CFG_STRUCT(GPP_A19, 0xffffffff, 0xffffff00) /* RESERVED */ + PAD_NC(GPP_A20, NONE), /* GPIO */ + PAD_NC(GPP_A21, NONE), /* GPIO */ + PAD_NC(GPP_A22, NONE), /* GPIO */ + PAD_NC(GPP_A23, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B0, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B1, 1, DEEP), /* GPIO */ + PAD_NC(GPP_B2, NONE), /* GPIO */ + PAD_NC(GPP_B3, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + _PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_B12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SLP_S0# */ + PAD_CFG_NF_BUF_TRIG(GPP_B13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* PLTRST# */ + PAD_CFG_NF_BUF_TRIG(GPP_B14, NONE, PLTRST, NF1, TX_RX_DISABLE, OFF), /* SPKR */ + PAD_NC(GPP_B15, NONE), /* GPIO */ + PAD_NC(GPP_B16, NONE), /* GPIO */ + PAD_NC(GPP_B17, NONE), /* GPIO */ + PAD_NC(GPP_B18, NONE), /* GPIO */ + PAD_NC(GPP_B19, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_B20, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_B21, NONE), /* GPIO */ + PAD_NC(GPP_B22, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_B23, NONE, DEEP, NF2, TX_RX_DISABLE, LEVEL), /* PCHHOT# */ + _PAD_CFG_STRUCT(GPP_C0, 0xffffffff, 0xffffff00) /* RESERVED */ + _PAD_CFG_STRUCT(GPP_C1, 0xffffffff, 0xffffff00) /* RESERVED */ + PAD_NC(GPP_C2, NONE), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C3, 0xffffffff, 0xffffff00) /* RESERVED */ + _PAD_CFG_STRUCT(GPP_C4, 0xffffffff, 0xffffff00) /* RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00) /* RESERVED */ + _PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00) /* RESERVED */ + PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), /* GPIO */ + PAD_NC(GPP_C11, NONE), /* GPIO */ + PAD_NC(GPP_C12, NONE), /* GPIO */ + PAD_NC(GPP_C13, NONE), /* GPIO */ + PAD_NC(GPP_C14, NONE), /* GPIO */ + PAD_NC(GPP_C15, NONE), /* GPIO */ + PAD_NC(GPP_C16, NONE), /* GPIO */ + PAD_NC(GPP_C17, NONE), /* GPIO */ + PAD_NC(GPP_C18, NONE), /* GPIO */ + PAD_NC(GPP_C19, NONE), /* GPIO */ + PAD_NC(GPP_C20, NONE), /* GPIO */ + PAD_NC(GPP_C21, NONE), /* GPIO */ + PAD_CFG_GPI_ACPI_SMI(GPP_C22, 20K_PU, DEEP, NONE), /* GPIO */ + PAD_NC(GPP_C23, NONE), /* GPIO */ + PAD_NC(GPP_D0, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_NMI(GPP_D2, 20K_PU, DEEP, EDGE_SINGLE, NONE), /* GPIO */ + PAD_NC(GPP_D3, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), /* GPIO */ + PAD_NC(GPP_D5, NONE), /* GPIO */ + PAD_NC(GPP_D6, NONE), /* GPIO */ + PAD_NC(GPP_D7, NONE), /* GPIO */ + PAD_NC(GPP_D8, NONE), /* GPIO */ + PAD_NC(GPP_D9, NONE), /* GPIO */ + PAD_NC(GPP_D10, NONE), /* GPIO */ + PAD_NC(GPP_D11, NONE), /* GPIO */ + PAD_NC(GPP_D12, NONE), /* GPIO */ + PAD_NC(GPP_D13, NONE), /* GPIO */ + PAD_NC(GPP_D14, NONE), /* GPIO */ + PAD_NC(GPP_D15, NONE), /* GPIO */ + PAD_NC(GPP_D16, NONE), /* GPIO */ + PAD_NC(GPP_D17, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D18, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_D19, 1, PLTRST), /* GPIO */ + PAD_NC(GPP_D20, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_D21, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_INT(GPP_D22, NONE, PWROK, OFF), /* GPIO */ + PAD_NC(GPP_D23, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_E0, NONE, DEEP, NF1, TX_DISABLE, OFF), /* SATAXPCIE0 */ + PAD_NC(GPP_E1, NONE), /* GPIO */ + PAD_NC(GPP_E2, NONE), /* GPIO */ + PAD_NC(GPP_E3, NONE), /* GPIO */ + PAD_NC(GPP_E4, NONE), /* GPIO */ + PAD_NC(GPP_E5, NONE), /* GPIO */ + PAD_CFG_GPI_NMI(GPP_E6, 20K_PU, PLTRST, EDGE_SINGLE, NONE), /* GPIO */ + PAD_NC(GPP_E7, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_E8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_LED# */ + PAD_CFG_NF_BUF_TRIG(GPP_E9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC0# */ + PAD_CFG_NF_BUF_TRIG(GPP_E10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC1# */ + PAD_CFG_NF_BUF_TRIG(GPP_E11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC2# */ + PAD_CFG_NF_BUF_TRIG(GPP_E12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC3# */ + PAD_NC(GPP_F0, NONE), /* GPIO */ + PAD_NC(GPP_F1, NONE), /* GPIO */ + PAD_NC(GPP_F2, NONE), /* GPIO */ + PAD_NC(GPP_F3, NONE), /* GPIO */ + PAD_NC(GPP_F4, NONE), /* GPIO */ + PAD_CFG_GPI_APIC(GPP_F5, NONE, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F6, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_F8, 1, PLTRST), /* GPIO */ + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_F10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SCLOCK */ + PAD_CFG_NF_BUF_TRIG(GPP_F11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SLOAD */ + PAD_CFG_NF_BUF_TRIG(GPP_F12, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SDATAOUT1 */ + PAD_CFG_NF_BUF_TRIG(GPP_F13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SATA_SDATAOUT2 */ + PAD_NC(GPP_F14, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_F15, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC4# */ + PAD_CFG_NF_BUF_TRIG(GPP_F16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* USB_OC5# */ + PAD_NC(GPP_F17, NONE), /* GPIO */ + PAD_NC(GPP_F18, NONE), /* GPIO */ + PAD_NC(GPP_F19, NONE), /* GPIO */ + PAD_NC(GPP_F20, NONE), /* GPIO */ + PAD_NC(GPP_F21, NONE), /* GPIO */ + PAD_NC(GPP_F22, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, PWROK), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), /* GPIO */ + PAD_NC(GPP_G4, NONE), /* GPIO */ + PAD_NC(GPP_G5, NONE), /* GPIO */ + PAD_NC(GPP_G6, NONE), /* GPIO */ + PAD_NC(GPP_G7, NONE), /* GPIO */ + PAD_NC(GPP_G8, NONE), /* GPIO */ + PAD_NC(GPP_G9, NONE), /* GPIO */ + PAD_NC(GPP_G10, NONE), /* GPIO */ + PAD_NC(GPP_G11, NONE), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), /* GPIO */ + PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), /* GPIO */ + PAD_NC(GPP_G17, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_G18, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* NMI# */ + PAD_CFG_NF_BUF_TRIG(GPP_G19, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SMI# */ + PAD_NC(GPP_G20, NONE), /* GPIO */ + PAD_NC(GPP_G21, NONE), /* GPIO */ + PAD_NC(GPP_G22, NONE), /* GPIO */ + PAD_NC(GPP_G23, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_H0, 1, DEEP), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H1, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + PAD_CFG_GPO(GPP_H2, 1, DEEP), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_H3, NONE, DEEP, NF1, RX_DISABLE, OFF), /* SRCCLKREQ9# */ + _PAD_CFG_STRUCT(GPP_H4, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + PAD_CFG_GPO(GPP_H5, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H6, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H7, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H8, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H9, 1, PLTRST), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_H10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML2CLK */ + PAD_CFG_NF_BUF_TRIG(GPP_H11, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML2DATA */ + PAD_NC(GPP_H12, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_H13, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML3CLK */ + PAD_CFG_NF_BUF_TRIG(GPP_H14, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML3DATA */ + PAD_NC(GPP_H15, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_H16, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML4CLK */ + PAD_CFG_NF_BUF_TRIG(GPP_H17, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SML4DATA */ + PAD_NC(GPP_H18, NONE), /* GPIO */ + PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H20, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H21, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPIO */ + PAD_CFG_GPO(GPP_H23, 1, PLTRST), /* GPIO */ + PAD_NC(GPD0, NONE), /* GPIO */ + PAD_NC(GPD1, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPD2, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* LAN_WAKE# */ + PAD_CFG_NF_BUF_TRIG(GPD3, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* PWRBTN# */ + PAD_CFG_NF_BUF_TRIG(GPD4, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_S3# */ + PAD_CFG_NF_BUF_TRIG(GPD5, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_S4# */ + PAD_CFG_NF_BUF_TRIG(GPD6, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(PWROK) | PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_POL_NONE | PAD_BUF(TX_RX_DISABLE) | 1, PAD_PULL(NONE)), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPD8, NONE, PWROK, NF1, TX_RX_DISABLE, OFF), /* SUSCLK */ + PAD_NC(GPD9, NONE), /* GPIO */ + PAD_NC(GPD10, NONE), /* GPIO */ + PAD_NC(GPD11, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_I0, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_HPD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_I1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_HPD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_I2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_HPD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_I3, NONE, PLTRST, NF1, TX_RX_DISABLE, OFF), /* DDPE_HPD3 */ + PAD_NC(GPP_I4, NONE), /* GPIO */ + PAD_CFG_NF_BUF_TRIG(GPP_I5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPB_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I7, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPC_CTRLDATA */ + PAD_CFG_NF_BUF_TRIG(GPP_I9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_CTRLCLK */ + PAD_CFG_NF_BUF_TRIG(GPP_I10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* DDPD_CTRLDATA */ }; @@ -233,15 +233,15 @@ static const struct pad_config early_gpio_table[] = { /* LPC */ -/* LAD0 */ _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x00000000), -/* LAD1 */ _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x00000000), -/* LAD2 */ _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x00000000), -/* LAD3 */ _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x00000000), -/* LFRAME# */ _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x00000000), -/* SERIRQ */ _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x00000000), -/* CLKRUN# */ _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x00000000), -/* CLKOUT_LPC0 */ _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x00000000), -/* CLKOUT_LPC1 */ _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x00000000), + PAD_CFG_NF_BUF_TRIG(GPP_A1, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A2, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD1 */ + PAD_CFG_NF_BUF_TRIG(GPP_A3, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD2 */ + PAD_CFG_NF_BUF_TRIG(GPP_A4, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LAD3 */ + PAD_CFG_NF_BUF_TRIG(GPP_A5, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* LFRAME# */ + PAD_CFG_NF_BUF_TRIG(GPP_A6, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* SERIRQ */ + PAD_CFG_NF_BUF_TRIG(GPP_A8, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKRUN# */ + PAD_CFG_NF_BUF_TRIG(GPP_A9, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC0 */ + PAD_CFG_NF_BUF_TRIG(GPP_A10, NONE, DEEP, NF1, TX_RX_DISABLE, OFF), /* CLKOUT_LPC1 */ }; #endif /* __ACPI__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35679 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059 Gerrit-Change-Number: 35679 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[4.11_branch]: src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake platform
by Morgan Jang (Code Review) 24 Jul '20

24 Jul '20

Morgan Jang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37233 ) Change subject: src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake platform ...................................................................... src/mainboard/ocp/monolake: Create SMBIOS type 16 for Monolake platform Create SMBIOS type 16 for Monolake platform, but the memory ECC setting can`t be enabled by the FSP, so it`s hardcoded to MEMORY_ARRAY_ECC_SINGLE_BIT. Change-Id: Ie057742112f14447b226d432417d9301d4aea958 Signed-off-by: Morgan Jang <Morgan_Jang(a)wiwynn.com> --- M src/mainboard/ocp/monolake/mainboard.c 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/37233/1 diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index dffd19f..3a11b55 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -30,6 +30,8 @@ #define VPD_LEN 10 /* Default countdown is 15 minutes. */ #define DEFAULT_COUNTDOWN 9000 +#define MAX_IMC 1 +#define MAX_DIMM_SIZE_GB (32UL << 20) static void init_frb2_wdt(void) { @@ -60,6 +62,41 @@ } } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int write_smbios_type16(struct device *dev, int *handle, unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + u32 maximum_capacity; + int len = sizeof(struct smbios_type16); + + printk(BIOS_INFO, "Create SMBIOS type 16\n"); + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + /* The ECC setting can`t be confirmed in FSP, so hardcode it. */ + t->memory_error_correction = MEMORY_ARRAY_ECC_SINGLE_BIT; + t->memory_error_information_handle = 0xFFFE; + t->number_of_memory_devices = CONFIG_DIMM_MAX/MAX_IMC; + + maximum_capacity = (u32)(CONFIG_DIMM_MAX * MAX_DIMM_SIZE_GB); + if (maximum_capacity >= 0x80000000) { + t->maximum_capacity = 0x80000000; + t->extended_maximum_capacity = maximum_capacity << 10; + } else { + t->maximum_capacity = (u32)maximum_capacity; + t->extended_maximum_capacity = 0; + } + + *current += len; + t->handle = *handle; + *handle += 1; + t->length = len - 2; + return len; +} +#endif + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. @@ -76,6 +113,10 @@ clear_ipmi_flags(&rsp); system_reset(); } + +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_data = write_smbios_type16; +#endif } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/37233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: Ie057742112f14447b226d432417d9301d4aea958 Gerrit-Change-Number: 37233 Gerrit-PatchSet: 1 Gerrit-Owner: Morgan Jang Gerrit-MessageType: newchange

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coreboot-gerrit February 2020