coreboot-gerrit February 2020

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Change in coreboot[master]: [WIP] soc/amd/common: Access ACPI MMIO via proper symbols
by Kyösti Mälkki (Code Review) 28 Jun '20

28 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37324 ) Change subject: [WIP] soc/amd/common: Access ACPI MMIO via proper symbols ...................................................................... [WIP] soc/amd/common: Access ACPI MMIO via proper symbols Using proper symbols for base addresses, it is possible to only define the symbols for base addesses implemented in the platform. TBD: Check for bad aliasing effects when immediate value changes to memory reference. Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/acpimmio/mmio_util.c M src/soc/amd/common/block/include/amdblocks/acpimmio.h M src/soc/amd/common/block/include/amdblocks/acpimmio_map.h 3 files changed, 125 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/37324/1 diff --git a/src/soc/amd/common/block/acpimmio/mmio_util.c b/src/soc/amd/common/block/acpimmio/mmio_util.c index 04d5e4a..51e661d 100644 --- a/src/soc/amd/common/block/acpimmio/mmio_util.c +++ b/src/soc/amd/common/block/acpimmio/mmio_util.c @@ -18,6 +18,28 @@ #include <amdblocks/acpimmio_map.h> #include <amdblocks/acpimmio.h> +uint8_t *const acpimmio_sm_pci = (void *)ACPIMMIO_SM_PCI_BASE; +uint8_t *const acpimmio_smi = (void *)ACPIMMIO_SMI_BASE; +uint8_t *const acpimmio_pmio = (void *)ACPIMMIO_PMIO_BASE; +uint8_t *const acpimmio_pmio2 = (void *)ACPIMMIO_PMIO2_BASE; +uint8_t *const acpimmio_biosram = (void *)ACPIMMIO_BIOSRAM_BASE; +uint8_t *const acpimmio_cmosram = (void *)ACPIMMIO_CMOSRAM_BASE; +uint8_t *const acpimmio_cmos = (void *)ACPIMMIO_CMOS_BASE; +uint8_t *const acpimmio_acpi = (void *)ACPIMMIO_ACPI_BASE; +uint8_t *const acpimmio_asf = (void *)ACPIMMIO_ASF_BASE; +uint8_t *const acpimmio_smbus = (void *)ACPIMMIO_SMBUS_BASE; +uint8_t *const acpimmio_wdt = (void *)ACPIMMIO_WDT_BASE; +uint8_t *const acpimmio_hpet = (void *)ACPIMMIO_HPET_BASE; +uint8_t *const acpimmio_iomux = (void *)ACPIMMIO_IOMUX_BASE; +uint8_t *const acpimmio_misc = (void *)ACPIMMIO_MISC_BASE; +uint8_t *const acpimmio_dpvga = (void *)ACPIMMIO_DPVGA_BASE; +uint8_t *const acpimmio_gpio0 = (void *)ACPIMMIO_GPIO0_BASE; +uint8_t *const acpimmio_gpio1 = (void *)ACPIMMIO_GPIO1_BASE; +uint8_t *const acpimmio_gpio2 = (void *)ACPIMMIO_GPIO2_BASE; +uint8_t *const acpimmio_xhci_pm = (void *)ACPIMMIO_XHCIPM_BASE; +uint8_t *const acpimmio_acdc_tmr = (void *)ACPIMMIO_ACDCTMR_BASE; +uint8_t *const acpimmio_aoac = (void *)ACPIMMIO_AOAC_BASE; + void enable_acpimmio_decode(void) { uint32_t dw; diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 57d24db..9df47d1 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -121,272 +121,272 @@ static inline uint8_t sm_pci_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SM_PCI_BASE + reg)); + return read8(acpimmio_sm_pci + reg); } static inline uint16_t sm_pci_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SM_PCI_BASE + reg)); + return read16(acpimmio_sm_pci + reg); } static inline uint32_t sm_pci_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_SM_PCI_BASE + reg)); + return read32(acpimmio_sm_pci + reg); } static inline void sm_pci_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); + write8(acpimmio_sm_pci + reg, value); } static inline void sm_pci_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); + write16(acpimmio_sm_pci + reg, value); } static inline void sm_pci_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_SM_PCI_BASE + reg), value); + write32(acpimmio_sm_pci + reg, value); } static inline uint8_t smi_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SMI_BASE + reg)); + return read8(acpimmio_smi + reg); } static inline uint16_t smi_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SMI_BASE + reg)); + return read16(acpimmio_smi + reg); } static inline uint32_t smi_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_SMI_BASE + reg)); + return read32(acpimmio_smi + reg); } static inline void smi_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SMI_BASE + reg), value); + write8(acpimmio_smi + reg, value); } static inline void smi_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SMI_BASE + reg), value); + write16(acpimmio_smi + reg, value); } static inline void smi_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_SMI_BASE + reg), value); + write32(acpimmio_smi + reg, value); } static inline uint8_t pm_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read8(acpimmio_pmio + reg); } static inline uint16_t pm_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read16(acpimmio_pmio + reg); } static inline uint32_t pm_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_PMIO_BASE + reg)); + return read32(acpimmio_pmio + reg); } static inline void pm_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_PMIO_BASE + reg), value); + write8(acpimmio_pmio + reg, value); } static inline void pm_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_PMIO_BASE + reg), value); + write16(acpimmio_pmio + reg, value); } static inline void pm_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_PMIO_BASE + reg), value); + write32(acpimmio_pmio + reg, value); } static inline uint8_t biosram_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_BIOSRAM_BASE + reg)); + return read8(acpimmio_biosram + reg); } static inline void biosram_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_BIOSRAM_BASE + reg), value); + write8(acpimmio_biosram + reg, value); } static inline uint8_t acpi_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_ACPI_BASE + reg)); + return read8(acpimmio_acpi + reg); } static inline uint16_t acpi_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_ACPI_BASE + reg)); + return read16(acpimmio_acpi + reg); } static inline uint32_t acpi_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_ACPI_BASE + reg)); + return read32(acpimmio_acpi + reg); } static inline void acpi_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_ACPI_BASE + reg), value); + write8(acpimmio_acpi + reg, value); } static inline void acpi_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_ACPI_BASE + reg), value); + write16(acpimmio_acpi + reg, value); } static inline void acpi_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_ACPI_BASE + reg), value); + write32(acpimmio_acpi + reg, value); } static inline uint8_t asf_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_ASF_BASE + reg)); + return read8(acpimmio_asf + reg); } static inline uint16_t asf_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_ASF_BASE + reg)); + return read16(acpimmio_asf + reg); } static inline void asf_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_ASF_BASE + reg), value); + write8(acpimmio_asf + reg, value); } static inline void asf_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_ASF_BASE + reg), value); + write16(acpimmio_asf + reg, value); } static inline uint8_t smbus_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_SMBUS_BASE + reg)); + return read8(acpimmio_smbus + reg); } static inline uint16_t smbus_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_SMBUS_BASE + reg)); + return read16(acpimmio_smbus + reg); } static inline void smbus_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_SMBUS_BASE + reg), value); + write8(acpimmio_smbus + reg, value); } static inline void smbus_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_SMBUS_BASE + reg), value); + write16(acpimmio_smbus + reg, value); } static inline uint8_t iomux_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_IOMUX_BASE + reg)); + return read8(acpimmio_iomux + reg); } static inline uint16_t iomux_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_IOMUX_BASE + reg)); + return read16(acpimmio_iomux + reg); } static inline uint32_t iomux_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_IOMUX_BASE + reg)); + return read32(acpimmio_iomux + reg); } static inline void iomux_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_IOMUX_BASE + reg), value); + write8(acpimmio_iomux + reg, value); } static inline void iomux_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_IOMUX_BASE + reg), value); + write16(acpimmio_iomux + reg, value); } static inline void iomux_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_IOMUX_BASE + reg), value); + write32(acpimmio_iomux + reg, value); } static inline uint8_t misc_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_MISC_BASE + reg)); + return read8(acpimmio_misc + reg); } static inline uint16_t misc_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_MISC_BASE + reg)); + return read16(acpimmio_misc + reg); } static inline uint32_t misc_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_MISC_BASE + reg)); + return read32(acpimmio_misc + reg); } static inline void misc_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_MISC_BASE + reg), value); + write8(acpimmio_misc + reg, value); } static inline void misc_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_MISC_BASE + reg), value); + write16(acpimmio_misc + reg, value); } static inline void misc_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_MISC_BASE + reg), value); + write32(acpimmio_misc + reg, value); } static inline uint8_t xhci_pm_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + return read8(acpimmio_xhci_pm + reg); } static inline uint16_t xhci_pm_read16(uint8_t reg) { - return read16((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + return read16(acpimmio_xhci_pm + reg); } static inline uint32_t xhci_pm_read32(uint8_t reg) { - return read32((void *)(ACPIMMIO_XHCIPM_BASE + reg)); + return read32(acpimmio_xhci_pm + reg); } static inline void xhci_pm_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write8(acpimmio_xhci_pm + reg, value); } static inline void xhci_pm_write16(uint8_t reg, uint16_t value) { - write16((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write16(acpimmio_xhci_pm + reg, value); } static inline void xhci_pm_write32(uint8_t reg, uint32_t value) { - write32((void *)(ACPIMMIO_XHCIPM_BASE + reg), value); + write32(acpimmio_xhci_pm + reg, value); } static inline uint8_t aoac_read8(uint8_t reg) { - return read8((void *)(ACPIMMIO_AOAC_BASE + reg)); + return read8(acpimmio_aoac + reg); } static inline void aoac_write8(uint8_t reg, uint8_t value) { - write8((void *)(ACPIMMIO_AOAC_BASE + reg), value); + write8(acpimmio_aoac + reg, value); } #endif /* __AMDBLOCKS_ACPIMMIO_H__ */ diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h index 755af52..4f64ee6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio_map.h @@ -42,26 +42,56 @@ */ #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000 -#define ACPIMMIO_SM_PCI_BASE 0xfed80000 -#define ACPIMMIO_SMI_BASE 0xfed80200 -#define ACPIMMIO_PMIO_BASE 0xfed80300 -#define ACPIMMIO_PMIO2_BASE 0xfed80400 -#define ACPIMMIO_BIOSRAM_BASE 0xfed80500 -#define ACPIMMIO_CMOSRAM_BASE 0xfed80600 -#define ACPIMMIO_CMOS_BASE 0xfed80700 -#define ACPIMMIO_ACPI_BASE 0xfed80800 -#define ACPIMMIO_ASF_BASE 0xfed80900 -#define ACPIMMIO_SMBUS_BASE 0xfed80a00 -#define ACPIMMIO_WDT_BASE 0xfed80b00 -#define ACPIMMIO_HPET_BASE 0xfed80c00 -#define ACPIMMIO_IOMUX_BASE 0xfed80d00 + +#ifndef __ACPI__ +#define ACPIMMIO_SM_PCI_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0000) +#define ACPIMMIO_SMI_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0200) +#define ACPIMMIO_PMIO_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0300) +#define ACPIMMIO_PMIO2_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0400) +#define ACPIMMIO_BIOSRAM_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0500) +#define ACPIMMIO_CMOSRAM_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0600) +#define ACPIMMIO_CMOS_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0700) +#define ACPIMMIO_ACPI_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0800) +#define ACPIMMIO_ASF_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0900) +#define ACPIMMIO_SMBUS_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0a00) +#define ACPIMMIO_WDT_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0b00) +#define ACPIMMIO_HPET_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0c00) +#define ACPIMMIO_IOMUX_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0d00) +#define ACPIMMIO_MISC_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x0e00) +#define ACPIMMIO_DPVGA_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1400) +#define ACPIMMIO_GPIO0_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1500) +#define ACPIMMIO_GPIO1_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1600) +#define ACPIMMIO_GPIO2_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1700) +#define ACPIMMIO_XHCIPM_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1c00) +#define ACPIMMIO_ACDCTMR_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1d00) +#define ACPIMMIO_AOAC_BASE (AMD_SB_ACPI_MMIO_ADDR + 0x1e00) + +extern uint8_t *const acpimmio_sm_pci; +extern uint8_t *const acpimmio_smi; +extern uint8_t *const acpimmio_pmio; +extern uint8_t *const acpimmio_pmio2; +extern uint8_t *const acpimmio_biosram; +extern uint8_t *const acpimmio_cmosram; +extern uint8_t *const acpimmio_cmos; +extern uint8_t *const acpimmio_acpi; +extern uint8_t *const acpimmio_asf; +extern uint8_t *const acpimmio_smbus; +extern uint8_t *const acpimmio_wdt; +extern uint8_t *const acpimmio_hpet; +extern uint8_t *const acpimmio_iomux; +extern uint8_t *const acpimmio_misc; +extern uint8_t *const acpimmio_dpvga; +extern uint8_t *const acpimmio_gpio0; +extern uint8_t *const acpimmio_gpio1; +extern uint8_t *const acpimmio_gpio2; +extern uint8_t *const acpimmio_xhci_pm; +extern uint8_t *const acpimmio_acdc_tmr; +extern uint8_t *const acpimmio_aoac; +#else + +/* Damn, ASL fails on additions. */ #define ACPIMMIO_MISC_BASE 0xfed80e00 -#define ACPIMMIO_DPVGA_BASE 0xfed81400 #define ACPIMMIO_GPIO0_BASE 0xfed81500 -#define ACPIMMIO_GPIO1_BASE 0xfed81600 -#define ACPIMMIO_GPIO2_BASE 0xfed81700 -#define ACPIMMIO_XHCIPM_BASE 0xfed81c00 -#define ACPIMMIO_ACDCTMR_BASE 0xfed81d00 -#define ACPIMMIO_AOAC_BASE 0xfed81e00 +#endif #endif /* __AMDBLOCKS_ACPIMMIO_MAP_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/37324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8599ee93bfb1c2d6d9b4accfca1ebbefe758e09 Gerrit-Change-Number: 37324 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

8 37

Change in ...coreboot[master]: drivers/intel/mipi_camera: add functionality
by Matt Delco (Code Review) 26 Jun '20

26 Jun '20

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31163 Change subject: drivers/intel/mipi_camera: add functionality ...................................................................... drivers/intel/mipi_camera: add functionality Some boards & variants are using raw asl files to define the ACPI devices (and related properties) required by Linux MIPI camera drivers. These asl files lack the SSDB property that's required by Windows MIPI camera drivers. The mipi_camera driver can provide a SSDB property, but it's missing some properties needed for Linux (and my scan of the source code didn't find any current users of it). This change updates the mipi_camera driver so it can provide a combined superset of what's required by Linux and Windows. I've also expanded the support so it has support for the IMGU and CIO2 devices. BUG=none BRANCH=none TEST=Verified that the ACPI state generated by the driver (with appropriate devicetree changes) is extremely comparible to what's generated by the asl files. Verified that the camera still works in CrOS on Atlas. Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08 Signed-off-by: Matt Delco <delco(a)chromium.org> --- M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/mipi_camera/chip.h M src/mainboard/google/poppy/dsdt.asl 3 files changed, 624 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/31163/1 diff --git a/src/drivers/intel/mipi_camera/camera.c b/src/drivers/intel/mipi_camera/camera.c index 0cea0ba..8844206 100644 --- a/src/drivers/intel/mipi_camera/camera.c +++ b/src/drivers/intel/mipi_camera/camera.c @@ -15,69 +15,599 @@ #include <arch/acpi.h> #include <arch/acpi_device.h> +#include <arch/acpi_pld.h> #include <arch/acpigen.h> #include <console/console.h> #include <device/i2c_simple.h> #include <device/device.h> #include <device/path.h> +#include <device/pci_def.h> #include <string.h> #include "chip.h" +#define CIO2_PCI_DEV 0x14 +#define CIO2_PCI_FN 0x3 + +/* + * This implementation assumes there is only 1 endpoint at each end of every + * data port. It also assumes there are no clock lanes. It also assumes + * that any VCM or NVM for a CAM is on the same I2C bus as the CAM. + */ + +/* + * Adds settings for a CIO2 device (typically at "\_SB.PCI0.CIO2"). A _DSD is + * added that specifies a child table for each port (e.g., PRT0 for "port0" + * and PRT1 for "port1"). Each PRTx table specifies a table for each endpoint + * (though only 1 endpoint is supported by this implementation so the table + * only has an "endpoint0" that points to a EPx0 table). The EPx0 table + * primarily describes the # of lanes in "data-lines" and specifies the name + * of the other side in "remote-endpoint" (the name is usually of the form + * "\_SB.PCI0.I2Cx.CAM0" for the first port/cam and "\_SB.PCI0.I2Cx.CAM1" + * if there's a second port/cam). + */ +static void camera_fill_cio2(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + char *ep_table_name[MAX_PORT_ENTRIES] = {NULL}; + char *port_table_name[MAX_PORT_ENTRIES] = {NULL}; + char *port_name[MAX_PORT_ENTRIES] = {NULL}; + uint32_t i = 0; + char name[BUS_PATH_MAX]; + + if (!dsd) + return; + + for (i = 0; i < config->cio2_num_ports; ++i) { + struct acpi_dp *ep_table = NULL; + struct acpi_dp *port_table = NULL; + snprintf(name, sizeof(name), "EP%u0", i); + ep_table_name[i] = strdup(name); + if (!ep_table_name[i]) + break; + ep_table = acpi_dp_new_table(ep_table_name[i]); + if (!ep_table) + break; + acpi_dp_add_integer(ep_table, "endpoint", 0); + acpi_dp_add_integer(ep_table, "clock-lanes", 0); + if (config->cio2_lanes_used[i] > 0) { + struct acpi_dp *lanes = acpi_dp_new_table("data-lanes"); + if (lanes) { + uint32_t j; + for (j = 1; j <= config->cio2_lanes_used[i]; + ++j) { + acpi_dp_add_integer(lanes, NULL, j); + } + acpi_dp_add_array(ep_table, lanes); + } + } + if (config->cio2_lane_endpoint[i]) { + struct acpi_dp *remote = + acpi_dp_new_table("remote-endpoint"); + if (remote) { + acpi_dp_add_reference(remote, NULL, + config->cio2_lane_endpoint[i]); + acpi_dp_add_integer(remote, NULL, 0); + acpi_dp_add_integer(remote, NULL, 0); + acpi_dp_add_array(ep_table, remote); + } + } + snprintf(name, sizeof(name), "PRT%u", i); + port_table_name[i] = strdup(name); + if (!port_table_name[i]) { + // acpi_dp_free(ep_table); + break; + } + port_table = acpi_dp_new_table(port_table_name[i]); + if (!port_table) { + // acpi_dp_free(ep_table); + break; + } + acpi_dp_add_integer(port_table, "port", i); + acpi_dp_add_child(port_table, "endpoint0", ep_table); + + snprintf(name, sizeof(name), "port%u", i); + port_name[i] = strdup(name); + if (!port_name[i]) { + // acpi_dp_free(port_table); + break; + } + acpi_dp_add_child(dsd, port_name[i], port_table); + } + acpi_dp_write(dsd); + + for (i = 0; i < config->cio2_num_ports; ++i) { + free(ep_table_name[i]); + free(port_table_name[i]); + free(port_name[i]); + } +} + +/* + * Adds settings for a camera sensor device (typically at + * "\_SB.PCI0.I2Cx.CAMy"). The drivers for Linux tends to expect the camera + * sensor device and any related nvram / vcm devices to be separate ACPI + * devices, while the drivers for Windows want all of these to be grouped + * together in the camera sensor ACPI device. This implementation tries to + * satisfy both, though the unfortunate tradeoff is that the same I2C address + * for nvram and vcm is advertised by multiple devices in ACPI (via "_CRS"). + * The Windows driver can use the "_DSM" method to disambiguate the I2C + * resources in the camera sensor ACPI device. Drivers for Windows typically + * query "SSDB" for configuration information (represented as a binary blob + * dump of struct), while Linux drivers typically consult individual parameters + * in "_DSD". + * + * The tree of tables in "_DSD" is analogous to what's used for the "CIO2" + * device. The _DSD specifies a child table for the sensor's port (e.g., PRT0 + * for "port0"--this implementation assumes a camera only has 1 port). The + * PRT0 table specifies a table for each endpoint (though only 1 endpoint is + * supported by this implementation so the table only has an "endpoint0" that + * points to a EP00 table). The EP00 table primarily describes the # of lanes + * in "data-lines", a list of frequencies in "list-frequencies", and specifies + * the name of the other side in "remote-endpoint" (typically "\_SB.PCI0.CIO2"). + */ +static void camera_fill_sensor(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *ep00 = NULL; + struct acpi_dp *prt0 = NULL; + struct acpi_dp *dsd = NULL; + uint16_t i2c_bus = dev->bus ? dev->bus->secondary : 0xFFFF; + uint16_t i2c_addr = dev->path.i2c.device; + + if (config->use_pld && !config->disable_pld_defaults) { + if (!config->pld.ignore_color) + config->pld.ignore_color = 1; + if (!config->pld.visible) + config->pld.visible = 1; + if (!config->pld.vertical_offset) + config->pld.vertical_offset = 0xffff; + if (!config->pld.horizontal_offset) + config->pld.horizontal_offset = 0xffff; + /* + * PLD_PANEL_TOP has a value of zero, so the following + * will change any instance of PLD_PANEL_TOP to + * PLD_PANEL_FRONT unless disable_pld_defaults is set. + */ + if (!config->pld.panel) + config->pld.panel = PLD_PANEL_FRONT; + /* + * PLD_HORIZONTAL_POSITION_LEFT has a value of zero, so + * the following will change any instance of that value + * to PLD_HORIZONTAL_POSITION_CENTER unless + * disable_pld_defaults is set. + */ + if (!config->pld.horizontal_position) { + config->pld.horizontal_position = + PLD_HORIZONTAL_POSITION_CENTER; + } + /* + * The desired default for |vertical_position| is + * PLD_VERTICAL_POSITION_UPPER, which has a value of + * zero so no work is needed to set a default. The + * same applies for setting |shape| to PLD_SHAPE_ROUND. + */ + } + if (config->use_pld) + acpigen_write_pld(&config->pld); + + if (!config->disable_ssdb_defaults) { + if (!config->ssdb.bdf_value) { + config->ssdb.bdf_value = (CIO2_PCI_DEV << 3) | + CIO2_PCI_FN; + } + if (!config->ssdb.platform) + config->ssdb.platform = 9; + if (!config->ssdb.flash_support) + config->ssdb.flash_support = 2; + if (!config->ssdb.privacy_led) + config->ssdb.privacy_led = 1; + if (!config->ssdb.mipi_define) + config->ssdb.mipi_define = 1; + if (!config->ssdb.mclk_speed) + config->ssdb.mclk_speed = 19200000; + if (!config->ssdb.lanes_used) { + struct device *cio2 = pcidev_on_root(CIO2_PCI_DEV, + CIO2_PCI_FN); + struct drivers_intel_mipi_camera_config *cio2_config; + cio2_config = cio2 ? cio2->chip_info : NULL; + if (!cio2_config) { + printk(BIOS_ERR, "Failed to get CIO2 config\n"); + } else if (cio2_config->device_type != + INTEL_ACPI_CAMERA_CIO2) { + printk(BIOS_ERR, "Device type isn't CIO2: %u\n", + (u32)cio2_config->device_type); + } else if (config->ssdb.link_used >= + cio2_config->cio2_num_ports) { + printk(BIOS_ERR, "%u exceeds CIO2's %u links\n", + (u32)config->ssdb.link_used, + (u32)cio2_config->cio2_num_ports); + } else { + config->ssdb.lanes_used = + cio2_config->cio2_lanes_used[ + config->ssdb.link_used]; + } + } + } + + /* Method (_DSM, 4, NotSerialized) */ + acpigen_write_method("_DSM", 0x4); + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid("822ace8f-2814-4174-a56b-5f029fe079ee"); + acpigen_write_return_string(config->sensor_name ? + config->sensor_name : "UNKNOWN"); + acpigen_pop_len(); /* If */ + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid("26257549-9271-4ca4-bb43-c4899d5a4881"); + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + + /* If (LEqual (Local1, 1)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 1); + acpigen_write_return_integer((config->ssdb.vcm_type ? 1 : 0) + + (config->ssdb.rom_type ? 1 : 0) + 1); + acpigen_pop_len(); /* If Arg2=1 */ + + /* If (LEqual (Local1, 2)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 2); + acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | + ((uint32_t)i2c_addr) << 8 | + 0x0); /* type 0 for sensor */ + acpigen_pop_len(); /* If Arg2=2 */ + + if (config->ssdb.vcm_type) { + /* If (LEqual (Local1, 3)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3); + acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | + ((uint32_t)config->vcm_address) + << 8 | + 0x01); /* type 1 for vcm */ + acpigen_pop_len(); /* If Arg2=3 */ + } + if (config->ssdb.rom_type) { + /* If (LEqual (Local1, 3 or 4)) */ + acpigen_write_if_lequal_op_int(LOCAL1_OP, 3 + + (config->ssdb.vcm_type ? 1 : 0)); + acpigen_write_return_integer(((uint32_t)i2c_bus) << 24 | + ((uint32_t)config->rom_address) + << 8 | + 0x02); /* type 2 for rom */ + acpigen_pop_len(); /* If Arg2=3 or 4 */ + } + + acpigen_pop_len(); /* If uuid */ + + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + acpigen_pop_len(); /* Method _DSM */ + + /* end of _dsm */ + + ep00 = acpi_dp_new_table("EP00"); + if (ep00) { + struct acpi_dp *remote = NULL; + acpi_dp_add_integer(ep00, "endpoint", 0); + acpi_dp_add_integer(ep00, "clock-lanes", 0); + if (config->ssdb.lanes_used > 0) { + struct acpi_dp *lanes = acpi_dp_new_table("data-lanes"); + if (lanes) { + uint32_t i; + for (i = 1; i <= config->ssdb.lanes_used; ++i) + acpi_dp_add_integer(lanes, NULL, i); + acpi_dp_add_array(ep00, lanes); + } + } + if (config->num_freq_entries > 0) { + struct acpi_dp *freq = + acpi_dp_new_table("link-frequencies"); + if (freq) { + uint32_t i; + for (i = 0; i < config->num_freq_entries && + i < MAX_LINK_FREQ_ENTRIES; ++i) { + acpi_dp_add_integer(freq, NULL, + config->link_freq[i]); + } + acpi_dp_add_array(ep00, freq); + } + } + remote = acpi_dp_new_table("remote-endpoint"); + if (remote) { + const char *remote_name = NULL; + struct device *cio2 = NULL; + if (config->remote_name) { + remote_name = config->remote_name; + } else { + cio2 = pcidev_on_root(CIO2_PCI_DEV, + CIO2_PCI_FN); + if (cio2) + remote_name = acpi_device_path(cio2); + else + remote_name = "\\_SB.PCI0.CIO2"; + } + acpi_dp_add_reference(remote, NULL, remote_name); + acpi_dp_add_integer(remote, NULL, + config->ssdb.link_used); + acpi_dp_add_integer(remote, NULL, 0); /* endpoint? */ + acpi_dp_add_array(ep00, remote); + } + prt0 = acpi_dp_new_table("PRT0"); + } + if (!prt0) { + // acpi_dp_free(ep00); + } else { + acpi_dp_add_integer(prt0, "port", 0); + acpi_dp_add_child(prt0, "endpoint0", ep00); + dsd = acpi_dp_new_table("_DSD"); + } + if (!dsd) { + // acpi_dp_free(prt0); + } else { + const char *vcm_name = NULL; + acpi_dp_add_integer(dsd, "clock-frequency", + config->ssdb.mclk_speed); + if (config->ssdb.degree) + acpi_dp_add_integer(dsd, "rotation", 180); + if (config->ssdb.vcm_type) { + if (config->vcm_name) { + vcm_name = config->vcm_name; + } else { + const struct device_path path = { + .type = DEVICE_PATH_I2C, + .i2c.device = config->vcm_address, + }; + struct device *vcm_dev = find_dev_path(dev->bus, + &path); + struct drivers_intel_mipi_camera_config * + vcm_config; + vcm_config = vcm_dev ? vcm_dev->chip_info : + NULL; + if (!vcm_config) { + printk(BIOS_ERR, "Failed to get VCM\n"); + } else if (vcm_config->device_type != + INTEL_ACPI_CAMERA_VCM) { + printk(BIOS_ERR, "Device isn't VCM\n"); + } else { + vcm_name = acpi_device_path(vcm_dev); + } + } + } + if (vcm_name) + acpi_dp_add_reference(dsd, "lens-focus", vcm_name); + acpi_dp_add_child(dsd, "port0", prt0); + acpi_dp_write(dsd); + } + + acpigen_write_method_serialized("SSDB", 0); + acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb, + sizeof(config->ssdb)); + acpigen_pop_len(); /* Method */ + + /* Fill Power Sequencing Data */ + if (config->num_pwdb_entries > 0) { + acpigen_write_method_serialized("PWDB", 0); + acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb, + sizeof(struct intel_pwdb) * + config->num_pwdb_entries); + acpigen_pop_len(); /* Method */ + } +} + +static void camera_fill_nvm(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd = acpi_dp_new_table("_DSD"); + if (!dsd) + return; + + /* It might be possible to default size or width based on type. */ + if (!config->disable_nvm_defaults && !config->nvm_pagesize) + config->nvm_pagesize = 1; + if (!config->disable_nvm_defaults && !config->nvm_readonly) + config->nvm_readonly = 1; + + if (config->nvm_size) + acpi_dp_add_integer(dsd, "size", config->nvm_size); + if (config->nvm_pagesize) + acpi_dp_add_integer(dsd, "pagesize", config->nvm_pagesize); + if (config->nvm_readonly) + acpi_dp_add_integer(dsd, "read-only", config->nvm_readonly); + if (config->nvm_width) + acpi_dp_add_integer(dsd, "address-width", config->nvm_width); + acpi_dp_write(dsd); +} + +static void camera_fill_vcm(struct device *dev) +{ + struct drivers_intel_mipi_camera_config *config = dev->chip_info; + struct acpi_dp *dsd; + + if (!config->vcm_compat) + return; + + dsd = acpi_dp_new_table("_DSD"); + if (!dsd) + return; + acpi_dp_add_string(dsd, "compatible", config->vcm_compat); + acpi_dp_write(dsd); +} + static void camera_fill_ssdt(struct device *dev) { struct drivers_intel_mipi_camera_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); - struct acpi_i2c i2c = { - .address = dev->path.i2c.device, - .mode_10bit = dev->path.i2c.mode_10bit, - .speed = I2C_SPEED_FAST, - .resource = scope, - }; if (!dev->enabled || !scope) return; /* Device */ - acpigen_write_scope(scope); - acpigen_write_device(acpi_device_name(dev)); - acpigen_write_name_string("_HID", config->acpi_hid); - acpigen_write_name_integer("_UID", config->acpi_uid); - acpigen_write_name_string("_DDN", config->chip_name); - acpigen_write_STA(acpi_device_status(dev)); + if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || + config->device_type == INTEL_ACPI_CAMERA_IMGU) { + u32 address; - /* Resources */ - acpigen_write_name("_CRS"); - acpigen_write_resourcetemplate_header(); - acpi_device_write_i2c(&i2c); - acpigen_write_resourcetemplate_footer(); + if (dev->path.type != DEVICE_PATH_PCI) { + printk(BIOS_ERR, "CIO2/IMGU devices require PCI\n"); + return; + } + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + acpigen_write_name_string("_DDN", + config->device_type == INTEL_ACPI_CAMERA_CIO2 ? + "Camera and Imaging Subsystem" : "Imaging Unit"); + } else { + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; - /* Mark it as Camera related device */ - acpigen_write_name_integer("CAMD", config->device_type); + if (dev->path.type != DEVICE_PATH_I2C) { + printk(BIOS_ERR, "Non-CIO2/IMGU devices require I2C\n"); + return; + } - /* Create Device specific data */ - if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) { - acpigen_write_method_serialized("SSDB", 0); - acpigen_write_return_byte_buffer((uint8_t *)&config->ssdb, - sizeof(config->ssdb)); - acpigen_pop_len(); /* Method */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) + acpigen_write_name_integer("_ADR", 0); + if (config->acpi_hid) + acpigen_write_name_string("_HID", config->acpi_hid); + else if (config->device_type == INTEL_ACPI_CAMERA_VCM) + acpigen_write_name_string("_HID", + ACPI_DT_NAMESPACE_HID); + else if (config->device_type == INTEL_ACPI_CAMERA_NVM) + acpigen_write_name_string("_HID", "INT3499"); + acpigen_write_name_integer("_UID", config->acpi_uid); + acpigen_write_name_string("_DDN", config->chip_name); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + /* + * The optional vcm/nvram devices are presumed to be on the + * same I2C bus as the camera sensor. + */ + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR && + config->ssdb.vcm_type) { + struct acpi_i2c i2c_vcm = i2c; + i2c_vcm.address = config->vcm_address; + acpi_device_write_i2c(&i2c_vcm); + } + if (config->device_type == INTEL_ACPI_CAMERA_SENSOR && + config->ssdb.rom_type) { + struct acpi_i2c i2c_rom = i2c; + i2c_rom.address = config->rom_address; + acpi_device_write_i2c(&i2c_rom); + } + acpigen_write_resourcetemplate_footer(); } - /* Fill Power Sequencing Data */ - acpigen_write_method_serialized("PWDB", 0); - acpigen_write_return_byte_buffer((uint8_t *)&config->pwdb, - (sizeof(struct intel_pwdb) * config->num_pwdb_entries)); - acpigen_pop_len(); /* Method */ + /* Mark it as Camera related device */ + if (config->device_type == INTEL_ACPI_CAMERA_CIO2 || + config->device_type == INTEL_ACPI_CAMERA_IMGU || + config->device_type == INTEL_ACPI_CAMERA_SENSOR || + config->device_type == INTEL_ACPI_CAMERA_VCM) { + acpigen_write_name_integer("CAMD", config->device_type); + } + + if (config->dep) { + acpigen_write_name("_DEP"); + acpigen_write_package(1); + acpigen_emit_namestring(config->dep); + acpigen_pop_len(); + } + if (config->pr0) { + acpigen_write_name("_PR0"); + acpigen_write_package(1); + acpigen_emit_namestring(config->pr0); + acpigen_pop_len(); + } + /* It's very unlikely you need _PR3 for any camera device */ + if (config->pr3) { + acpigen_write_name("_PR3"); + acpigen_write_package(1); + acpigen_emit_namestring(config->pr3); + acpigen_pop_len(); + } + + if (config->device_type == INTEL_ACPI_CAMERA_CIO2) + camera_fill_cio2(dev); + else if (config->device_type == INTEL_ACPI_CAMERA_SENSOR) + camera_fill_sensor(dev); + else if (config->device_type == INTEL_ACPI_CAMERA_NVM) + camera_fill_nvm(dev); + else if (config->device_type == INTEL_ACPI_CAMERA_VCM) + camera_fill_vcm(dev); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ - printk(BIOS_INFO, "%s: %s address 0%xh\n", acpi_device_path(dev), - dev->chip_ops->name, dev->path.i2c.device); + if (dev->path.type == DEVICE_PATH_PCI) { + printk(BIOS_INFO, "%s: %s PCI address 0%x\n", + acpi_device_path(dev), + dev->chip_ops->name, dev->path.pci.devfn); + } else { + printk(BIOS_INFO, "%s: %s I2C address 0%xh\n", + acpi_device_path(dev), + dev->chip_ops->name, dev->path.i2c.device); + } } static const char *camera_acpi_name(const struct device *dev) { + const char *prefix = NULL; + static char name[BUS_PATH_MAX]; struct drivers_intel_mipi_camera_config *config = dev->chip_info; - return config->acpi_name; + if (config->acpi_name) + return config->acpi_name; + if (config->device_type == INTEL_ACPI_CAMERA_CIO2) + return "CIO2"; + else if (config->device_type == INTEL_ACPI_CAMERA_IMGU) + return "IMGU"; + else if (config->device_type == INTEL_ACPI_CAMERA_PMIC) + return "PMIC"; + + switch (config->device_type) { + case INTEL_ACPI_CAMERA_SENSOR: + prefix = "CAM"; + break; + case INTEL_ACPI_CAMERA_VCM: + prefix = "VCM"; + break; + case INTEL_ACPI_CAMERA_NVM: + prefix = "NVM"; + break; + default: + prefix = "ERR"; /* Error */ + break; + } + /* + * The cameras know which link # they use, so that's used + * as the basis for the instance #. The VCM and NVM don't + * have this information, so the best we can go on is the + * _UID. + */ + snprintf(name, sizeof(name), "%s%u", prefix, + config->device_type == INTEL_ACPI_CAMERA_SENSOR ? + config->ssdb.link_used : config->acpi_uid); + return name; } static struct device_operations camera_ops = { diff --git a/src/drivers/intel/mipi_camera/chip.h b/src/drivers/intel/mipi_camera/chip.h index 741ae8e..50b757c 100644 --- a/src/drivers/intel/mipi_camera/chip.h +++ b/src/drivers/intel/mipi_camera/chip.h @@ -17,14 +17,19 @@ #define __INTEL_MIPI_CAMERA_CHIP_H__ #include <stdint.h> +#include <arch/acpi_pld.h> #define MAX_PWDB_ENTRIES 12 +#define MAX_PORT_ENTRIES 4 +#define MAX_LINK_FREQ_ENTRIES 4 enum intel_camera_device_type { INTEL_ACPI_CAMERA_CIO2, INTEL_ACPI_CAMERA_IMGU, INTEL_ACPI_CAMERA_SENSOR, INTEL_ACPI_CAMERA_VCM, + /* Value for NVM might might not be appropriate for CAMD */ + INTEL_ACPI_CAMERA_NVM, INTEL_ACPI_CAMERA_PMIC = 100, }; @@ -77,12 +82,14 @@ uint8_t degree; /* Camera Orientation */ uint8_t mipi_define; /* MIPI info defined in ACPI or sensor driver */ - uint32_t mclk; /* Clock info for sensor */ + uint32_t mclk_speed; /* Clock info for sensor */ uint8_t control_logic_id; /* PMIC device node used for the camera sensor */ uint8_t mipi_data_format; /* MIPI data format */ uint8_t silicon_version; /* Silicon version */ uint8_t customer_id; /* Customer ID */ + uint8_t mclk_port; + uint8_t reserved[13]; } __packed; struct intel_pwdb { @@ -95,14 +102,59 @@ } __packed; struct drivers_intel_mipi_camera_config { + /* Generic settings */ + enum intel_camera_device_type device_type; + + /* Settings that should not need to be set since defaults sane. */ + const char *acpi_name; /* defaults: CIO2,IMGU,PMIC,CAMx,VCMx,NVMx */ + + /* + * General settings that can be used for any type (but doesn't + * necessarily need to be used/specified for each device. + */ + const char *chip_name; + const char *acpi_hid; /* vcm and nvm have defaults */ + unsigned int acpi_uid; + const char *dep; + const char *pr0; + const char *pr3; /* _PR3 shouldn't be needed */ + + /* Settings specific to CIO2 device */ + uint32_t cio2_num_ports; + uint32_t cio2_lanes_used[MAX_PORT_ENTRIES]; + const char *cio2_lane_endpoint[MAX_PORT_ENTRIES]; + + /* Settings specific to camera sensor */ + bool disable_ssdb_defaults; struct intel_ssdb ssdb; struct intel_pwdb pwdb[MAX_PWDB_ENTRIES]; - enum intel_camera_device_type device_type; uint8_t num_pwdb_entries; - const char *acpi_hid; - const char *acpi_name; - const char *chip_name; - unsigned int acpi_uid; + uint8_t num_freq_entries; /* # of elements in link_freq */ + uint32_t link_freq[MAX_LINK_FREQ_ENTRIES]; + const char *sensor_name; /* default "UNKNOWN" */ + const char *remote_name; /* default "\_SB.PCI0.CIO2" */ + const char *vcm_name; /* defaults to |vcm_address| device */ + bool use_pld; + bool disable_pld_defaults; + struct acpi_pld pld; + uint16_t rom_address; /* I2C to use if ssdb.rom_type != 0 */ + uint16_t vcm_address; /* I2C to use if ssdb.vcm_type != 0 */ + + /* + * Settings specific to nvram. Many values, if left as zero, + * will be assigned a default. Set disable_nvm_defaults to + * non-zero if you want to disable the defaulting behavior so + * you can use zero for a value. + */ + + bool disable_nvm_defaults; + uint32_t nvm_size; + uint32_t nvm_pagesize; + uint32_t nvm_readonly; + uint32_t nvm_width; + + /* Settings specific to vcm */ + const char *vcm_compat; }; #endif diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 0001867..d923ba5 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -39,8 +39,10 @@ { Device (PCI0) { - /* Image processing unit */ +#if !IS_ENABLED(CONFIG_DRIVERS_INTEL_MIPI_CAMERA) + /* Image processing unit, if not using MIPI driver */ #include <soc/intel/skylake/acpi/ipu.asl> +#endif #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/31163 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9d84519eae1333eeb67107281a2deafc24e8a08 Gerrit-Change-Number: 31163 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: [WIP] device/smbus_host: Declare common early SMBUS prototypes
by Kyösti Mälkki (Code Review) 22 Jun '20

22 Jun '20

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38233 ) Change subject: [WIP] device/smbus_host: Declare common early SMBUS prototypes ...................................................................... [WIP] device/smbus_host: Declare common early SMBUS prototypes Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/smbus.h M src/include/device/smbus_host.h M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/asus/p2b-ds/romstage.c M src/mainboard/asus/p2b-ls/romstage.c M src/mainboard/asus/p2b/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/nehalem/raminit.c M src/northbridge/intel/x4x/raminit.c M src/southbridge/intel/bd82x6x/early_smbus.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801dx/early_smbus.c M src/southbridge/intel/i82801dx/i82801dx.h M src/southbridge/intel/i82801gx/early_smbus.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801ix/early_smbus.c M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801jx/early_smbus.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/ibexpeak/early_smbus.c M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/early_smbus.c M src/southbridge/intel/lynxpoint/pch.h 27 files changed, 39 insertions(+), 139 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/38233/1 diff --git a/src/include/device/smbus.h b/src/include/device/smbus.h index cae4f3f..5782d5e 100644 --- a/src/include/device/smbus.h +++ b/src/include/device/smbus.h @@ -29,6 +29,7 @@ struct bus *get_pbus_smbus(struct device *dev); +#if !DEVTREE_EARLY static inline int smbus_recv_byte(struct device *const dev) { return i2c_dev_readb(dev); @@ -51,5 +52,6 @@ int smbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buffer); int smbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *buffer); +#endif #endif /* DEVICE_SMBUS_H */ diff --git a/src/include/device/smbus_host.h b/src/include/device/smbus_host.h index 4d67e18..0236c5c 100644 --- a/src/include/device/smbus_host.h +++ b/src/include/device/smbus_host.h @@ -51,4 +51,36 @@ printk(BIOS_DEBUG, "SMBus controller enabled\n"); } +#if DEVTREE_EARLY +static inline int smbus_read_byte(u8 device, u8 address) +{ + uintptr_t base = smbus_base(); + return do_smbus_read_byte(base, device, address); +} + +static inline int smbus_write_byte(u8 device, u8 address, u8 data) +{ + uintptr_t base = smbus_base(); + return do_smbus_write_byte(base, device, address, data); +} + +static inline int smbus_block_read(u8 device, u8 cmd, size_t max_bytes, u8 *buf) +{ + uintptr_t base = smbus_base(); + return do_smbus_block_read(base, device, cmd, max_bytes, buf); +} + +static inline int smbus_block_write(u8 device, u8 cmd, size_t bytes, const u8 *buf) +{ + uintptr_t base = smbus_base(); + return do_smbus_block_write(base, device, cmd, bytes, buf); +} + +static inline int i2c_eeprom_read(u8 device, u8 offset, size_t bytes, u8 *buf) +{ + uintptr_t base = smbus_base(); + return do_i2c_eeprom_read(base, device, offset, bytes, buf); +} +#endif + #endif diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index ebbcc15..c647f96 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -20,7 +20,6 @@ #include <device/smbus_host.h> #include <arch/romstage.h> -#include <southbridge/intel/i82801dx/i82801dx.h> #include <northbridge/intel/e7505/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index b885f86..5fed7c5 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index bbf53bc..4e5c355 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 8ec579c..971255a4 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <southbridge/intel/i82371eb/i82371eb.h> #include <device/smbus_host.h> #include <northbridge/intel/i440bx/raminit.h> #include <arch/romstage.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7bab957..e5f511d 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -19,8 +19,8 @@ #include <stdint.h> #include <arch/io.h> #include <ec/acpi/ec.h> +#include <device/smbus_host.h> -#include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c index 2acbc57..6361a58 100644 --- a/src/northbridge/intel/i945/debug.c +++ b/src/northbridge/intel/i945/debug.c @@ -17,6 +17,7 @@ #include <spd.h> #include <device/pci_ops.h> #include <device/pci_def.h> +#include <device/smbus_host.h> #include <console/console.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index f0ea142..b6d9e6f 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -18,6 +18,7 @@ #include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <cf9_reset.h> #include <device/mmio.h> #include <device/device.h> diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 215e9b8..42e6ebe 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <cpu/x86/msr.h> #include <cbmem.h> #include <cf9_reset.h> diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index df2d31e..0809998 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -15,17 +15,13 @@ */ #include <device/pci_ops.h> +#include <device/smbus_host.h> #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> -#if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) -#include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ -#else -#include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */ -#endif #include <spd.h> #include <string.h> #include <device/dram/ddr2.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index 91f1bc3..7fa6f88 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -45,8 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 5348478..67dbf69 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -64,10 +64,6 @@ void enable_usb_bar(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index 99fe128..1775706 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -52,8 +52,3 @@ return 0; } - -int smbus_read_byte(u8 device, u8 address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index ea7efef..9076829 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -21,10 +21,6 @@ void enable_pm(void); -#if ENV_ROMSTAGE -int smbus_read_byte(u8 device, u8 address); -#endif - #endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 6e1f1f7..51110c4 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -37,8 +37,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index 9895de1..06f0f57 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -32,10 +32,8 @@ #if !defined(__ASSEMBLER__) #include <device/device.h> -#include "chip.h" void i82801dx_enable(struct device *dev); -int smbus_read_byte(unsigned int device, unsigned int address); void aseg_smm_lock(void); #endif diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index b89e57d..54aaa4f 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -45,24 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) -{ - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 688f1c3..7c326a7 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -41,15 +41,7 @@ void i82801gx_setup_bars(void); void i82801gx_early_init(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); void ich7_setup_cir(void); -#endif #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 60f49d2..f6ce713 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -47,8 +47,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index f60aad3..667bd50 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -213,10 +213,6 @@ void i82801ix_dmi_setup(void); void i82801ix_dmi_poll_vc1(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - #endif #endif diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c index 8e3329c..18a61b7 100644 --- a/src/southbridge/intel/i82801jx/early_smbus.c +++ b/src/southbridge/intel/i82801jx/early_smbus.c @@ -42,24 +42,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int i2c_eeprom_read(unsigned int device, unsigned int offset, u32 bytes, u8 *buf) -{ - return do_i2c_eeprom_read(SMBUS_IO_BASE, device, offset, bytes, buf); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index abf6187..2372014 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -225,14 +225,6 @@ } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, - u8 *buf); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, - const u8 *buf); -#endif void i82801jx_lpc_setup(void); void i82801jx_setup_bars(void); void i82801jx_early_init(void); diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c index 52d483d..7fa6f88 100644 --- a/src/southbridge/intel/ibexpeak/early_smbus.c +++ b/src/southbridge/intel/ibexpeak/early_smbus.c @@ -45,23 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} - -int smbus_write_byte(unsigned int device, unsigned int address, u8 data) -{ - return do_smbus_write_byte(SMBUS_IO_BASE, device, address, data); -} - -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf) -{ - return do_smbus_block_read(SMBUS_IO_BASE, device, cmd, bytes, buf); -} - -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf) -{ - return do_smbus_block_write(SMBUS_IO_BASE, device, cmd, bytes, buf); -} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 424bf42..8ac506d 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -54,13 +54,6 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -int smbus_write_byte(unsigned int device, unsigned int address, u8 data); -int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); -int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -#endif - void early_pch_init(void); void early_thermal_init(void); diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index 91f1bc3..7fa6f88 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -45,8 +45,3 @@ return 0; } - -int smbus_read_byte(unsigned int device, unsigned int address) -{ - return do_smbus_read_byte(SMBUS_IO_BASE, device, address); -} diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9622c67..b6bf00b 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -174,11 +174,6 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); - -#if ENV_ROMSTAGE -int smbus_read_byte(unsigned int device, unsigned int address); -#endif - void enable_usb_bar(void); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); -- To view, visit https://review.coreboot.org/c/coreboot/+/38233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1157cf391178a27db437d1d08ef5cb9333e976d0 Gerrit-Change-Number: 38233 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: cpu/x86/lapic: Cleanup code
by Patrick Rudolph (Code Review) 22 Jun '20

22 Jun '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36777 ) Change subject: cpu/x86/lapic: Cleanup code ...................................................................... cpu/x86/lapic: Cleanup code * Don't use long as it compiles to 64bit on x86_64, which breaks interrupts in qemu and thus SeaBIOS wouldn't time out the boot menu * Get rid of unused defines * Get rid of unused atomic xchg code Tested on Qemu Q35 with x86_64 enabled: Interrupts working again. Tested on Qemu Q35 with x86_32 enabled: Interrupts are still working. Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/cpu/x86/lapic/lapic.c M src/cpu/x86/lapic/lapic_cpu_init.c M src/include/cpu/x86/lapic.h 3 files changed, 18 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/36777/1 diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 755fbe2..6eb72f9 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -58,6 +58,6 @@ LAPIC_DELIVERY_MODE_NMI) ); - printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid()); + printk(BIOS_DEBUG, " apic_id: 0x%02x ", lapicid()); printk(BIOS_INFO, "done.\n"); } diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index e7dfc57..1e5c96a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -101,7 +101,7 @@ static int lapic_start_cpu(unsigned long apicid) { int timeout; - unsigned long send_status, accept_status; + uint32_t send_status, accept_status; int j, maxlvt; /* @@ -133,11 +133,11 @@ printk(BIOS_ERR, "CPU %ld: First APIC write timed out. " "Disabling\n", apicid); // too bad. - printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); + printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk(BIOS_ERR, "Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk(BIOS_ERR, "ESR is 0x%lx\n", + printk(BIOS_ERR, "ESR is 0x%x\n", lapic_read(LAPIC_ESR)); } return 0; @@ -230,7 +230,7 @@ if (send_status) printk(BIOS_WARNING, "APIC never delivered???\n"); if (accept_status) - printk(BIOS_WARNING, "APIC delivery error (%lx).\n", + printk(BIOS_WARNING, "APIC delivery error (%x).\n", accept_status); if (send_status || accept_status) return 0; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 6fd1997..8800ad2 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -6,14 +6,14 @@ #include <halt.h> #include <smp/node.h> -static __always_inline unsigned long lapic_read(unsigned long reg) +static __always_inline uint32_t lapic_read(unsigned long reg) { - return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)); + return *((volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg)); } -static __always_inline void lapic_write(unsigned long reg, unsigned long v) +static __always_inline void lapic_write(unsigned long reg, uint32_t v) { - *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v; + *((volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg)) = v; } static __always_inline void lapic_wait_icr_idle(void) @@ -40,7 +40,7 @@ wrmsr(LAPIC_BASE_MSR, msr); } -static __always_inline unsigned long lapicid(void) +static __always_inline uint32_t lapicid(void) { return lapic_read(LAPIC_ID) >> 24; } @@ -58,58 +58,19 @@ void stop_this_cpu(void); #endif -#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \ - sizeof(*(ptr)))) - -struct __xchg_dummy { unsigned long a[100]; }; -#define __xg(x) ((struct __xchg_dummy *)(x)) - -/* - * Note: no "lock" prefix even on SMP: xchg always implies lock anyway - * Note 2: xchg has side effect, so that attribute volatile is necessary, - * but generally the primitive is invalid, *ptr is output argument. --ANK - */ -static inline unsigned long __xchg(unsigned long x, volatile void *ptr, - int size) +static inline void lapic_write_atomic(unsigned long reg, volatile uint32_t v) { - switch (size) { - case 1: - __asm__ __volatile__("xchgb %b0,%1" - : "=q" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - case 2: - __asm__ __volatile__("xchgw %w0,%1" - : "=r" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - case 4: - __asm__ __volatile__("xchgl %0,%1" - : "=r" (x) - : "m" (*__xg(ptr)), "0" (x) - : "memory"); - break; - } - return x; + volatile uint32_t *ptr; + + ptr = (volatile uint32_t *)(LAPIC_DEFAULT_BASE+reg); + + asm volatile ("xchgl %0, %1\n" + : "+r" (v), "+m" (*(ptr)) + : : "memory", "cc"); } -static inline void lapic_write_atomic(unsigned long reg, unsigned long v) -{ - (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v); -} - - -#ifdef X86_GOOD_APIC -# define FORCE_READ_AROUND_WRITE 0 -# define lapic_read_around(x) lapic_read(x) -# define lapic_write_around(x, y) lapic_write((x), (y)) -#else -# define FORCE_READ_AROUND_WRITE 1 # define lapic_read_around(x) lapic_read(x) # define lapic_write_around(x, y) lapic_write_atomic((x), (y)) -#endif void do_lapic_init(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/36777 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaed1ad956d090625c7bb5cd9cf55cbae16dd82bd Gerrit-Change-Number: 36777 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

7 16

Change in ...coreboot[master]: _WIP_ mb/amd/mandolin: Add Picasso CRB
by Marshall Dawson (Code Review) 21 Jun '20

21 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33772 Change subject: _WIP_ mb/amd/mandolin: Add Picasso CRB ...................................................................... _WIP_ mb/amd/mandolin: Add Picasso CRB We can get into ramstage with the state of Mandolin. Still no AGESA running, and therefore we hang when trying to scan the PCI bus. Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- A src/mainboard/amd/mandolin/Kconfig A src/mainboard/amd/mandolin/Kconfig.name A src/mainboard/amd/mandolin/Makefile.inc A src/mainboard/amd/mandolin/acpi/gpe.asl A src/mainboard/amd/mandolin/acpi/mainboard.asl A src/mainboard/amd/mandolin/acpi/routing.asl A src/mainboard/amd/mandolin/acpi/sleep.asl A src/mainboard/amd/mandolin/acpi/usb_oc.asl A src/mainboard/amd/mandolin/acpi_tables.c A src/mainboard/amd/mandolin/board_info.txt A src/mainboard/amd/mandolin/devicetree.cb A src/mainboard/amd/mandolin/dsdt.asl A src/mainboard/amd/mandolin/gpio.c A src/mainboard/amd/mandolin/gpio.h A src/mainboard/amd/mandolin/irq_tables.c A src/mainboard/amd/mandolin/mainboard.c A src/mainboard/amd/mandolin/mptable.c A src/mainboard/amd/mandolin/romstage.c 18 files changed, 1,242 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/33772/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig new file mode 100644 index 0000000..5d1c287 --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig @@ -0,0 +1,98 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_AMD_MANDOLIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_PICASSO + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select GFXUMA + +config AMD_LPC_DEBUG_CARD + bool "Enable LPC-Serial debug card on the debug header" + default n + select SUPERIO_SMSC_SIO1036 + help + AMD's debug card contains an SMSC SIO1036 device which provides + an I/O-based UART in the system. This feature is not compatible with + CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset. + Note that Kconfig does not currently enforce this restriction. + +config CBFS_SIZE + default 0x400000 + help + TODO: Adjust this! Right now it's simply making a lot of room for + amdfw.rom and EC firmware. + +config MAINBOARD_DIR + string + default amd/mandolin + +config MAINBOARD_PART_NUMBER + string + default "MANDOLIN" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config PICASSO_LEGACY_FREE + bool + default y + +config MANDOLIN_HAVE_APCB_BLOB + bool "Have AGESA PSP Customization Block file?" + default n + help + The PSP requires the APCB file to know how to configure memory, as + well as other settings it will initialize. To build an image that + will get to POST, select 'y' and provide the file path/name. The + default of 'n' allows the board to build successfully but it avoids + redistributing the APCB blob extracted from UEFI. + TODO: Add the ability to construct APCB on the fly for any mainboard. + +config PSP_APCB_FILE + string "APCB file" + depends on MANDOLIN_HAVE_APCB_BLOB + default "3rdparty/blobs/mainboard/amd/mandolin/apcb.bin" + help + The name of the AGESA Parameter Customization Block. TODO: will we + be able to generate this at build-time? Build it offline for + inclusion? + +config MANDOLIN_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + select AMDFW_OUTSIDE_CBFS + # todo: fix build the "inside" build. + +config MANDOLIN_MCHP_FW_FILE + string + depends on MANDOLIN_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/mandolin/mchp.bin" + +endif # BOARD_AMD_MANDOLIN diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name new file mode 100644 index 0000000..7dbfc3f --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_MANDOLIN + bool "Mandolin" diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc new file mode 100644 index 0000000..fe17e8e --- /dev/null +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -0,0 +1,41 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +romstage-y += gpio.c +ramstage-y += gpio.c + +PHONY+=add_mchp_fw +INTERMEDIATE+=add_mchp_fw + +ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y) + +MANDOLIN_MICROCHIP_FW_OFFSET=0 +add_mchp_fw: + printf " DD Adding Microchip firmware at ROM offset 0x%x\n" \ + "$(MANDOLIN_MICROCHIP_FW_OFFSET)" + dd if=$(CONFIG_MANDOLIN_MCHP_FW_FILE) \ + of=$(obj)/coreboot.pre conv=notrunc bs=1 \ + seek=$(MANDOLIN_MICROCHIP_FW_OFFSET) >/dev/null 2>&1 + +else +files_added:: warn_no_mchp +endif # CONFIG_MANDOLIN_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an the Microchip EC.\n" + printf "Do not flash this image. Your Mandolin's power button\n" + printf "will not respond when you press it.\n\n" diff --git a/src/mainboard/amd/mandolin/acpi/gpe.asl b/src/mainboard/amd/mandolin/acpi/gpe.asl new file mode 100644 index 0000000..d3c89fd --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/gpe.asl @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/mandolin/acpi/mainboard.asl b/src/mainboard/amd/mandolin/acpi/mainboard.asl new file mode 100644 index 0000000..d73fbea --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/mainboard.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/mandolin/acpi/routing.asl b/src/mainboard/amd/mandolin/acpi/routing.asl new file mode 100644 index 0000000..969def7 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/routing.asl @@ -0,0 +1,173 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015, 2016 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1, Func 0 - PCI Bridge for Internal Graphics(IGP) */ + /* Bus 0, Dev 1, Func 1 - HDMI Audio Controller */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + + /* Bus 0, Dev 2 Func 0,1,2,3,4,5 - PCIe Bridges */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* FCH devices */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + +}) + +Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 43 }, + Package(){0x0001FFFF, 1, 0, 40 }, + + /* Bus 0, Dev 2 - PCIe Bridges */ + Package(){0x0002FFFF, 0, 0, 44 }, + Package(){0x0002FFFF, 1, 0, 45 }, + Package(){0x0002FFFF, 2, 0, 46 }, + Package(){0x0002FFFF, 3, 0, 47 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 20 - F0:SMBus/ACPI;F3:LPC;F7:SD */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 18 Func 0 - USB: EHCI */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 10 Func 0 - USB: xHCI */ + Package(){0x0010FFFF, 0, 0, 18}, + Package(){0x0010FFFF, 1, 0, 17}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, +}) + + +/* GPP 0 */ +Name(PS4, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 24 }, + Package(){0x0000FFFF, 1, 0, 25 }, + Package(){0x0000FFFF, 2, 0, 26 }, + Package(){0x0000FFFF, 3, 0, 27 }, +}) + +/* GPP 1 */ +Name(PS5, Package(){ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, +}) +Name(APS5, Package(){ + Package(){0x0000FFFF, 0, 0, 28 }, + Package(){0x0000FFFF, 1, 0, 29 }, + Package(){0x0000FFFF, 2, 0, 30 }, + Package(){0x0000FFFF, 3, 0, 31 }, +}) + +/* GPP 2 */ +Name(PS6, Package(){ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, +}) +Name(APS6, Package(){ + Package(){0x0000FFFF, 0, 0, 32 }, + Package(){0x0000FFFF, 1, 0, 33 }, + Package(){0x0000FFFF, 2, 0, 34 }, + Package(){0x0000FFFF, 3, 0, 35 }, +}) + +/* GPP 3 */ +Name(PS7, Package(){ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, +}) +Name(APS7, Package(){ + Package(){0x0000FFFF, 0, 0, 36 }, + Package(){0x0000FFFF, 1, 0, 37 }, + Package(){0x0000FFFF, 2, 0, 38 }, + Package(){0x0000FFFF, 3, 0, 39 }, +}) + +/* GPP 4 */ +Name(PS8, Package(){ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, +}) +Name(APS8, Package(){ + Package(){0x0000FFFF, 0, 0, 40 }, + Package(){0x0000FFFF, 1, 0, 41 }, + Package(){0x0000FFFF, 2, 0, 42 }, + Package(){0x0000FFFF, 3, 0, 43 }, +}) diff --git a/src/mainboard/amd/mandolin/acpi/sleep.asl b/src/mainboard/amd/mandolin/acpi/sleep.asl new file mode 100644 index 0000000..baf3ca5 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/sleep.asl @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/mandolin/acpi/usb_oc.asl b/src/mainboard/amd/mandolin/acpi/usb_oc.asl new file mode 100644 index 0000000..ea7bd27 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/usb_oc.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// - file had a todo to update for Gardenia +// +// +// + +/* simple name description */ +/* +#include <arch/acpi.h> +DefinitionBlock ("DSDT.AML", "DSDT", 0x01, OEM_ID, ACPI_TABLE_CREATOR, 0x00010001 + ) + { + #include "usb.asl" + } +*/ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) + +/* USB Overcurrent GPEs */ diff --git a/src/mainboard/amd/mandolin/acpi_tables.c b/src/mainboard/amd/mandolin/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/amd/mandolin/board_info.txt b/src/mainboard/amd/mandolin/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/mandolin/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb new file mode 100644 index 0000000..8cb7da9 --- /dev/null +++ b/src/mainboard/amd/mandolin/devicetree.cb @@ -0,0 +1,60 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2019 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/picasso + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.2 on end # Bridge + device pci 1.3 on end # Bridge + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on end # Bridge + device pci 8.2 on end # Bridge + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + device i2c 51 on end + end + chip superio/smsc/sio1036 # optional debug card + end + end # SM + device pci 14.3 on end # LPC + device pci 14.6 on end # + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain + # todo: on a separate bus now: + # 2:0.0 15D8 display controller + # 2:0.1 15DE HD Audio + # 2:0.2 15DF Crypto Coprocessor + # 2:0.3 15E0 serial + # 2:0.4 15E1 serial + # 2:0.5 15E2 Audio Processor + # 2:0.6 15E3 Audio Processor - HD Audio Controller + # 2:0.7 15E6 Non-Sensor Fusion hub device + # 3:0.0 7901 SATA + # 3:0.1 1458 10GbE (per HDT) + # 3:0.2 1458 10GbE (per HDT) +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl new file mode 100644 index 0000000..25c0e78 --- /dev/null +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// +// +// +// todo: check file for accuracy +// +// +// + +#define MAINBOARD_HAS_SPEAKER 1 + +/* DefinitionBlock Statement */ +#include <arch/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* IRQ Routing mapping for this platform (in \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + /* Describe the SOC */ + #include <soc.asl> + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c new file mode 100644 index 0000000..aa16826 --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/southbridge.h> +#include <stdlib.h> +#include <soc/gpio.h> + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC5_L */ + PAD_GPI(GPIO_13, PULL_UP), + /* not USB_OC4_L */ + PAD_GPI(GPIO_14, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + /* PCIe SSD power enable */ + PAD_GPO(GPIO_23, HIGH), + /* PCIe Reset to DP0, DP1, J2105, TP, FP */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* SSD DEVSLP */ + PAD_NF(GPIO_5, DEVSLP0_S5, PULL_NONE), + /* SATA Express DEVSLP */ + PAD_NF(GPIO_6, DEVSLP1_S5, PULL_NONE), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* Blink */ + PAD_NF(GPIO_11, BLINK, PULL_NONE), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* Finger print CS# */ + PAD_GPO(GPIO_31, HIGH), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* Rear camera power enable */ + PAD_GPO(GPIO_89, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} diff --git a/src/mainboard/amd/mandolin/gpio.h b/src/mainboard/amd/mandolin/gpio.h new file mode 100644 index 0000000..1d3a8a2 --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +const struct soc_amd_gpio *early_gpio_table(size_t *size); +const struct soc_amd_gpio *gpio_table(size_t *size); + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/mandolin/irq_tables.c b/src/mainboard/amd/mandolin/irq_tables.c new file mode 100644 index 0000000..bf1daec --- /dev/null +++ b/src/mainboard/amd/mandolin/irq_tables.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) + pirq->checksum = sum; + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c new file mode 100644 index 0000000..6f2d1d9 --- /dev/null +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/acpi.h> +#include <amdblocks/amd_pci_util.h> +#include <soc/southbridge.h> + +#include "gpio.h" +// +// +// +// todo: check file for accuracy +// +// +// + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[] = { + [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x0A, 0x1F, 0x1F, + [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x1F, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x1F, + [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, + [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +}; + +const u8 mainboard_intr_data[] = { + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, + [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, + [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, + [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, + [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, + [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, + [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +static void mainboard_init(void *chip_info) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); +} + +/************************************************* + * enable the dedicated function in mandolin board. + *************************************************/ +static void mandolin_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " + CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mandolin_enable, +}; diff --git a/src/mainboard/amd/mandolin/mptable.c b/src/mainboard/amd/mandolin/mptable.c new file mode 100644 index 0000000..4e80ce1 --- /dev/null +++ b/src/mainboard/amd/mandolin/mptable.c @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +// +// +// +// todo: check file for accuracy +// +// +// + +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <string.h> +#include <stdint.h> +#include <cpu/x86/lapic.h> +#include <soc/southbridge.h> +#include <amdblocks/amd_pci_util.h> + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), \ + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ + (intr), (apicid), (pin)) + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, \ + MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ + (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + struct device *dev = pcidev_on_root(0x14, 4); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_pci, 0x6, 0x0, 0x15); + PCI_INT(bus_pci, 0x6, 0x1, 0x16); + PCI_INT(bus_pci, 0x6, 0x2, 0x17); + PCI_INT(bus_pci, 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_pci, 0x7, 0x0, 0x16); + PCI_INT(bus_pci, 0x7, 0x1, 0x17); + PCI_INT(bus_pci, 0x7, 0x2, 0x14); + PCI_INT(bus_pci, 0x7, 0x3, 0x15); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/amd/mandolin/romstage.c b/src/mainboard/amd/mandolin/romstage.c new file mode 100644 index 0000000..1741a39 --- /dev/null +++ b/src/mainboard/amd/mandolin/romstage.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <superio/smsc/sio1036/sio1036.h> +#include <soc/gpio.h> +#include "gpio.h" + +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) + +void romstage_mainboard_early_init(void) +{ + size_t num_gpios; + const struct soc_amd_gpio *gpios; + gpios = early_gpio_table(&num_gpios); + program_gpios(gpios, num_gpios); + + if (CONFIG(SUPERIO_SMSC_SIO1036)) + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Gerrit-Change-Number: 33772 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

6 65

Change in ...coreboot[master]: google_chromeec_command: makes the error status consistent
by YH Lin (Code Review) 20 Jun '20

20 Jun '20

YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31626 Change subject: google_chromeec_command: makes the error status consistent ...................................................................... google_chromeec_command: makes the error status consistent Currently various google_chromeec_command() implementation the error can be returned differently (LPC: -1 for v3, 1 for v1, SPI: -1/1, I2C: 1). This patch attempts to make it consistent across all implementations by using only negative number as error. All direct/indirect callers of google_chromeec_command() have also been modified accordingly as well. BRANCH=None BUG=chromium:935038 Signed-off-by: YH Lin <yueherngl(a)google.com> Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29 --- M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/smihandler.c M src/ec/google/chromeec/vboot_storage.c M src/ec/google/chromeec/vstore.c M src/mainboard/google/gru/mainboard.c M src/security/vboot/vboot_logic.c 10 files changed, 35 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31626/1 diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 2043347..603f1df 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -246,7 +246,7 @@ int rv = send_command_proto3(cec_command, crosec_io, context); if (rv < 0) { cec_command->cmd_code = rv; - return 1; + return -1; } return 0; } diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 09357b0..897dceb 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -363,7 +363,7 @@ cmd.cmd_size_out = sizeof(rsp); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) == 0) + if (google_chromeec_command(&cmd) >= 0) return rsp.event_mask; return 0; } @@ -404,7 +404,7 @@ cmd.cmd_size_out = sizeof(rsp); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) == 0) + if (google_chromeec_command(&cmd) >= 0) return rsp.event_mask; return 0; } @@ -507,7 +507,7 @@ cmd.cmd_size_out = sizeof(r); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return -1; if (feature >= 8 * sizeof(r.flags)) @@ -531,7 +531,7 @@ cmd.cmd_size_out = 0; cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return -1; return 0; @@ -550,7 +550,7 @@ cmd.cmd_size_out = sizeof(r); cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return -1; return rtc_to_tm(r.time, time); @@ -658,7 +658,7 @@ cmd.cmd_data_out = &board_v; cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd)) + if (google_chromeec_command(&cmd) < 0) return -1; *version = board_v.board_version; @@ -677,7 +677,7 @@ cmd.cmd_data_out = &sku_v; cmd.cmd_dev_index = 0; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return 0; return sku_v.sku_id; @@ -708,7 +708,7 @@ if (!is_read) memcpy(&cmd_vbnvcontext.block, data, EC_VBNV_BLOCK_SIZE); - if (google_chromeec_command(&cec_cmd)) { + if (google_chromeec_command(&cec_cmd) < 0) { printk(BIOS_ERR, "ERROR: failed to %s vbnv_ec context: %d\n", is_read ? "read" : "write", (int)cec_cmd.cmd_code); mdelay(10); /* just in case */ @@ -792,7 +792,7 @@ cmd.cmd_size_out = sizeof(*r) + read_len; cmd.cmd_dev_index = 0; rv = google_chromeec_command(&cmd); - if (rv != 0) + if (rv < 0) return rv; /* Parse response */ @@ -875,7 +875,7 @@ }; struct usb_chg_measures m; int rv = google_chromeec_command(&cmd); - if (rv != 0) + if (rv < 0) return rv; /* values are given in milliAmps and milliVolts */ *type = rsp.type; diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 7a38336..51124f6 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -108,7 +108,7 @@ * * @param type charger type * @param max_watts charger max wattage - * @return non-zero for error, otherwise 0. + * @return 0 on success or negative integer for errors. */ int google_chromeec_get_usb_pd_power_info(enum usb_chg_type *type, u32 *max_watts); @@ -118,7 +118,7 @@ * * @param current_lim Max current in mA * @param voltage_lim Max voltage in mV - * @return non-zero for error, otherwise 0. + * @return 0 on success or negative integer for errors. */ int google_chromeec_override_dedicated_charger_limit(u16 current_lim, u16 voltage_lim); @@ -150,6 +150,8 @@ * The lower level transport works on the buffers handed out to the * upper level. Therefore, only the size of the request and response * are required. + * + * @return 0 on success or negative integer for errors. */ typedef int (*crosec_io_t)(size_t req_size, size_t resp_size, void *context); int crosec_command_proto(struct chromeec_command *cec_command, @@ -159,7 +161,7 @@ * Send a command to a CrOS EC * * @param cec_command: CrOS EC command to send - * @return 0 for success. Non-zero for error. + * @return 0 on success or negative integer for errors. */ int google_chromeec_command(struct chromeec_command *cec_command); diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index 22b491a..7f2ead5 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -205,7 +205,7 @@ __func__, cec_command->cmd_size_in, cec_command->cmd_size_out); cec_command->cmd_code = EC_RES_INVALID_PARAM; - return 1; + return -1; } /* Construct command. */ @@ -221,13 +221,13 @@ printk(BIOS_ERR, "%s: Cannot complete write to i2c-%d:%#x\n", __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; - return 1; + return -1; } if (i2c_read_raw(bus, chip, (uint8_t *)&resp, size_i2c_resp) != 0) { printk(BIOS_ERR, "%s: Cannot complete read from i2c-%d:%#x\n", __func__, bus, chip); cec_command->cmd_code = EC_RES_ERROR; - return 1; + return -1; } /* Verify and return response */ @@ -235,17 +235,17 @@ if (resp.response != EC_RES_SUCCESS) { printk(BIOS_DEBUG, "%s: Received bad result code %d\n", __func__, (int)resp.response); - return 1; + return -1; } if (resp.length > cec_command->cmd_size_out) { printk(BIOS_ERR, "%s: Received len %#02x too large\n", __func__, (int)resp.length); cec_command->cmd_code = EC_RES_INVALID_RESPONSE; - return 1; + return -1; } if (!ec_verify_checksum(&resp)) { cec_command->cmd_code = EC_RES_INVALID_CHECKSUM; - return 1; + return -1; } cec_command->cmd_size_out = resp.length; memcpy(cec_command->cmd_data_out, resp.data, resp.length); diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 61005d3..097b1b4 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -330,13 +330,13 @@ if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) { printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n", cec_command->cmd_code); - return 1; + return -1; } /* Check result */ cec_command->cmd_code = read_byte(EC_LPC_ADDR_HOST_DATA); if (cec_command->cmd_code) - return 1; + return -1; /* Read back args */ read_bytes(EC_LPC_ADDR_HOST_ARGS, sizeof(args), (u8*)&args, NULL); @@ -348,12 +348,12 @@ */ if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) { printk(BIOS_ERR, "EC protocol mismatch\n"); - return 1; + return -1; } if (args.data_size > cec_command->cmd_size_out) { printk(BIOS_ERR, "EC returned too much data\n"); - return 1; + return -1; } cec_command->cmd_size_out = args.data_size; @@ -369,7 +369,7 @@ /* Verify checksum */ if (args.checksum != csum) { printk(BIOS_ERR, "EC response has invalid checksum\n"); - return 1; + return -1; } return 0; diff --git a/src/ec/google/chromeec/smihandler.c b/src/ec/google/chromeec/smihandler.c index cab7192..3f703f9 100644 --- a/src/ec/google/chromeec/smihandler.c +++ b/src/ec/google/chromeec/smihandler.c @@ -54,7 +54,7 @@ ; printk(BIOS_DEBUG,"Clearing pending EC events. Error code 1 is expected.\n"); - while (google_chromeec_get_mkbp_event(&mkbp_event) == 0) + while (google_chromeec_get_mkbp_event(&mkbp_event) >= 0) ; } diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c index f47c2f1..08af2f6 100644 --- a/src/ec/google/chromeec/vboot_storage.c +++ b/src/ec/google/chromeec/vboot_storage.c @@ -30,7 +30,7 @@ /* Ensure the digests being saved match the EC's slot size. */ assert(digest_size == EC_VSTORE_SLOT_SIZE); - if (google_chromeec_vstore_write(slot, digest, digest_size)) + if (google_chromeec_vstore_write(slot, digest, digest_size) < 0) return -1; /* Assert the slot is locked on successful write. */ diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 28c2603..39e59f8 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -42,7 +42,7 @@ .cmd_data_out = &info, }; - if (google_chromeec_command(&cmd) != 0) + if (google_chromeec_command(&cmd) < 0) return 0; if (locked) diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 41307c7..245a70e 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -257,12 +257,14 @@ static void usb_power_cycle(int port) { - if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK)) + if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_FORCE_SINK) + < 0) printk(BIOS_ERR, "ERROR: Cannot force USB%d PD sink\n", port); mdelay(10); /* Make sure USB stick is fully depowered. */ - if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON)) + if (google_chromeec_set_usb_pd_role(port, USB_PD_CTRL_ROLE_TOGGLE_ON) + < 0) printk(BIOS_ERR, "ERROR: Cannot restore USB%d PD mode\n", port); } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 00bbae6..c379463 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -141,7 +141,7 @@ printk(BIOS_DEBUG, "Platform is resuming.\n"); - if (vboot_retrieve_hash(saved_hash, saved_hash_sz)) { + if (vboot_retrieve_hash(saved_hash, saved_hash_sz) < 0) { printk(BIOS_ERR, "Couldn't retrieve saved hash.\n"); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/31626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39f12502bc6982670dd200dcef0724e7eed2ed29 Gerrit-Change-Number: 31626 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mainboard/google: Split Hatch mainboard_memory_init_params() on spd path
by Edward O'Callaghan (Code Review) 19 Jun '20

19 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36495 ) Change subject: mainboard/google: Split Hatch mainboard_memory_init_params() on spd path ...................................................................... mainboard/google: Split Hatch mainboard_memory_init_params() on spd path The follow bifurcates mainboard_memory_init_params() in Hatch's romstage depending on if the SPD data path is either derived from CBFS or over SMBus. This restructure allows for variant boards that need to configure the SMBus path to do it via their own custom variant_memory_params() that implements the SMBus path. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I430853270bdc2a3d8916d23fb6f085a28890518a Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/romstage.c 2 files changed, 28 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/36495/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 004cc28..fbc41df 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -58,6 +58,10 @@ int default 512 +config ROMSTAGE_SPD_SMBUS + bool + default n + config DRIVER_TPM_SPI_BUS default 0x1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 07864e6..b264d66d 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -32,26 +32,33 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; - int is_single_ch_mem; variant_memory_params(&memcfg); - /* - * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single - * channel skus and 0 for dual channel skus. - */ - is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); - /* - * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. - * Dual-DIMM memory is not used in hatch family, so we only - * fill in spd_info for CH0D0 and CH1D0 here. - */ - int mem_sku = variant_memory_sku(); - memcfg.spd[0].read_type = READ_SPD_CBFS; - memcfg.spd[0].spd_spec.spd_index = mem_sku; - if (!is_single_ch_mem) { - memcfg.spd[2].read_type = READ_SPD_CBFS; - memcfg.spd[2].spd_spec.spd_index = mem_sku; + if (CONFIG(ROMSTAGE_SPD_SMBUS)) { + const FSPM_ARCH_UPD *arch_upd = &memupd->FspmArchUpd; + /* SPD was saved in S0/S5 path, skips it when resumes from S3 */ + if (arch_upd->BootMode == FSP_BOOT_ON_S3_RESUME) + return; + } else { + /* + * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single + * channel skus and 0 for dual channel skus. + */ + int is_single_ch_mem = gpio_get(GPIO_MEM_CH_SEL); + + /* + * spd[0]-spd[3] map to CH0D0, CH0D1, CH1D0, CH1D1 respectively. + * Dual-DIMM memory is not used in hatch family, so we only + * fill in spd_info for CH0D0 and CH1D0 here. + */ + int mem_sku = variant_memory_sku(); + memcfg.spd[0].read_type = READ_SPD_CBFS; + memcfg.spd[0].spd_spec.spd_index = mem_sku; + if (!is_single_ch_mem) { + memcfg.spd[2].read_type = READ_SPD_CBFS; + memcfg.spd[2].spd_spec.spd_index = mem_sku; + } } cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); -- To view, visit https://review.coreboot.org/c/coreboot/+/36495 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I430853270bdc2a3d8916d23fb6f085a28890518a Gerrit-Change-Number: 36495 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mainboard/google: Move memory_variant_sku() call site
by Edward O'Callaghan (Code Review) 19 Jun '20

19 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36494 ) Change subject: mainboard/google: Move memory_variant_sku() call site ...................................................................... mainboard/google: Move memory_variant_sku() call site Move the call site down to be local to where it is needed. This makes it easier to split the function into two variants, one for handling the SPD data sourced from CBFS or from SMBus. BRANCH=none BUG=b:143134702 TEST=./util/abuild/abuild -p none -t google/hatch -x -a Change-Id: I4b04fe392539e799f491ffc77d8a79a42724f052 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/36494/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 50d9066..07864e6 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -32,11 +32,9 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; - int mem_sku; int is_single_ch_mem; variant_memory_params(&memcfg); - mem_sku = variant_memory_sku(); /* * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single * channel skus and 0 for dual channel skus. @@ -48,6 +46,7 @@ * Dual-DIMM memory is not used in hatch family, so we only * fill in spd_info for CH0D0 and CH1D0 here. */ + int mem_sku = variant_memory_sku(); memcfg.spd[0].read_type = READ_SPD_CBFS; memcfg.spd[0].spd_spec.spd_index = mem_sku; if (!is_single_ch_mem) { -- To view, visit https://review.coreboot.org/c/coreboot/+/36494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b04fe392539e799f491ffc77d8a79a42724f052 Gerrit-Change-Number: 36494 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mainboard/google: Move variant_memory_sku() to baseboard/
by Edward O'Callaghan (Code Review) 19 Jun '20

19 Jun '20

Edward O'Callaghan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36492 ) Change subject: mainboard/google: Move variant_memory_sku() to baseboard/ ...................................................................... mainboard/google: Move variant_memory_sku() to baseboard/ The variant_memory_sku() symbol within romstage.c unreasonably depends on pre-processor #define's in variants that may not define them. Provide a default symbol and configuration within the basebase in the form of a weak symbol and allow the two variants that differ to override using a strong symbol. In the case of variants that do not need this symbol they can override with a strong symbol that is a nop. Change-Id: I41532e3067a989db5776887fac0459a000d07ff0 Signed-off-by: Edward O'Callaghan <quasisec(a)chromium.org> --- M src/mainboard/google/hatch/romstage.c M src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h M src/mainboard/google/hatch/variants/baseboard/memory.c M src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h M src/mainboard/google/hatch/variants/hatch/Makefile.inc M src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h A src/mainboard/google/hatch/variants/hatch/memory.c M src/mainboard/google/hatch/variants/helios/include/variant/gpio.h M src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h M src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h M src/mainboard/google/hatch/variants/kohaku/memory.c 11 files changed, 76 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/36492/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index a94fab5..50d9066 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -29,18 +29,6 @@ */ #define GPIO_MEM_CH_SEL GPP_F2 -int __weak variant_memory_sku(void) -{ - const gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} - void mainboard_memory_init_params(FSPM_UPD *memupd) { struct cnl_mb_cfg memcfg; diff --git a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h index b257589..5d69eed 100644 --- a/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/akemi/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index bcfc49f..ada20a8 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -15,9 +15,28 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> +/* Default memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_H19 +#define GPIO_MEM_CONFIG_1 GPP_H22 +#define GPIO_MEM_CONFIG_2 GPP_F10 +#define GPIO_MEM_CONFIG_3 GPP_F3 + +int __weak variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + static const struct cnl_mb_cfg baseboard_memcfg = { /* Baseboard uses 121, 81 and 100 rcomp resistors */ .rcomp_resistor = {121, 81, 100}, diff --git a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h index 92f9d41..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/dratini/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index a990b5a..47ca158 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 +romstage-y += memory.c + ramstage-y += gpio.c bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h index e7d8a75..5d69eed 100644 --- a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 - #endif diff --git a/src/mainboard/google/hatch/variants/hatch/memory.c b/src/mainboard/google/hatch/variants/hatch/memory.c new file mode 100644 index 0000000..2712b24 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/memory.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <baseboard/gpio.h> +#include <gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +int variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h index 92f9d41..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/helios/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h index 92f9d41..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kindred/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_H19 -#define GPIO_MEM_CONFIG_1 GPP_H22 -#define GPIO_MEM_CONFIG_2 GPP_F10 -#define GPIO_MEM_CONFIG_3 GPP_F3 - #endif diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h index 29e5904..d99e2bb 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/gpio.h @@ -18,10 +18,4 @@ #include <baseboard/gpio.h> -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_F20 -#define GPIO_MEM_CONFIG_1 GPP_F21 -#define GPIO_MEM_CONFIG_2 GPP_F11 -#define GPIO_MEM_CONFIG_3 GPP_F22 - #endif diff --git a/src/mainboard/google/hatch/variants/kohaku/memory.c b/src/mainboard/google/hatch/variants/kohaku/memory.c index 4901247..de33ead 100644 --- a/src/mainboard/google/hatch/variants/kohaku/memory.c +++ b/src/mainboard/google/hatch/variants/kohaku/memory.c @@ -15,9 +15,28 @@ #include <baseboard/variants.h> #include <baseboard/gpio.h> +#include <gpio.h> #include <soc/cnl_memcfg_init.h> #include <string.h> +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +int variant_memory_sku(void) +{ + const gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + static const struct cnl_mb_cfg baseboard_memcfg = { /* * The dqs_map arrays map the SoC pins to the lpddr3 pins -- To view, visit https://review.coreboot.org/c/coreboot/+/36492 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41532e3067a989db5776887fac0459a000d07ff0 Gerrit-Change-Number: 36492 Gerrit-PatchSet: 1 Gerrit-Owner: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: cpu/x86: Cache stages for RESET_VECTOR_IN_RAM
by Marshall Dawson (Code Review) 18 Jun '20

18 Jun '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38728 ) Change subject: cpu/x86: Cache stages for RESET_VECTOR_IN_RAM ...................................................................... cpu/x86: Cache stages for RESET_VECTOR_IN_RAM Implement the platform_prog_run() hook to allocate and program a variable MTRR for the program about to run. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I57caccceac8550efe33f7273d279275cd6af6a68 --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/nonxip_cache.c 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/38728/1 diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..72572a0 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -11,3 +11,7 @@ bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c + +bootblock-$(CONFIG_RESET_VECTOR_IN_RAM) += nonxip_cache.c +verstage-$(CONFIG_RESET_VECTOR_IN_RAM) += nonxip_cache.c +romstage-$(CONFIG_RESET_VECTOR_IN_RAM) += nonxip_cache.c diff --git a/src/cpu/x86/mtrr/nonxip_cache.c b/src/cpu/x86/mtrr/nonxip_cache.c new file mode 100644 index 0000000..334e829 --- /dev/null +++ b/src/cpu/x86/mtrr/nonxip_cache.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/x86/mtrr.h> +#include <console/console.h> +#include <program_loading.h> + +void reserve_non_xip_prog(struct prog *prog); // move me + +/* Set a variable MTRR to WB for the program about to run. + * It is up to the designer to ensure ranges are chosen carefully to avoid + * overlapping MTRRs + * TODO: consider creating a function for inserting ranges into existing + * var. MTRR settings instead. + */ +void platform_prog_run(struct prog *prog) +{ + const uint32_t base = region_device_offset(&prog->rdev); + const uint32_t size = region_device_sz(&prog->rdev); + const uint32_t end = base + size; + int mtrr_num; + uint32_t mtrr_base; + uint32_t mtrr_size = 4 * KiB; + + mtrr_num = get_free_var_mtrr(); + if (mtrr_num == -1) { + printk(BIOS_NOTICE, + "PROG_RUN: No MTRR available to cache ROM!\n" + "The next stage will run slowly!\n"); + return; + } + + while (1) { + if (ALIGN_DOWN(base, mtrr_size) + mtrr_size >= end) + break; + mtrr_size *= 2; + } + + mtrr_base = ALIGN_DOWN(base, mtrr_size); + if (mtrr_base + mtrr_size < end) { + printk(BIOS_NOTICE, "PROG_RUN: Limiting cache to %uKiB!\n", + mtrr_size / KiB); + /* Check if we can cover a bigger range by aligning up. */ + const uint32_t alt_base = ALIGN_UP(base, mtrr_size); + const uint32_t lower_coverage = mtrr_base + mtrr_size - base; + const uint32_t upper_coverage = MIN(alt_base + mtrr_size, end) - alt_base; + if (upper_coverage > lower_coverage) + mtrr_base = alt_base; + } + + printk(BIOS_DEBUG, "PROG_RUN: Setting MTRR to cache stage. base: 0x%08x, size: 0x%08x\n", + mtrr_base, mtrr_size); + + set_var_mtrr(mtrr_num, mtrr_base, mtrr_size, MTRR_TYPE_WRBACK); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/38728 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57caccceac8550efe33f7273d279275cd6af6a68 Gerrit-Change-Number: 38728 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2020