Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34453 )
Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ......................................................................
sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT
Both fields are ignored if WBINVD is set, which is true for all processors since i486.
Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 2 files changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34453/1
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 8794602..e656a37 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -766,8 +766,9 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; fadt->duty_offset = 1; if (chip->p_cnt_throttling_supported) { fadt->duty_width = 3; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index fa1ca92..c829707 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -678,8 +678,9 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; fadt->duty_offset = 1; if (chip->p_cnt_throttling_supported) { fadt->duty_width = 3;
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34453 )
Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ......................................................................
Patch Set 1: Code-Review+1
Christian Walter has uploaded a new patch set (#2) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/34453 )
Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ......................................................................
sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT
Both fields are ignored if WBINVD is set, which is true for all processors since i486.
Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Christian Walter christian.walter@9elements.com --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 2 files changed, 6 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/34453/2
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34453 )
Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ......................................................................
Patch Set 2: Code-Review+2
Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34453 )
Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ......................................................................
sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT
Both fields are ignored if WBINVD is set, which is true for all processors since i486.
Change-Id: Ibad56046e2c1b8595dc31e5861b9fd1fd7d2d6f3 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Signed-off-by: Christian Walter christian.walter@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34453 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/ibexpeak/lpc.c 2 files changed, 6 insertions(+), 6 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 987db36..55e2573 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -726,12 +726,12 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; - fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x00; diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 0d15b5d..54b2621 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -620,12 +620,12 @@ } fadt->p_lvl2_lat = c2_latency; fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; + /* flush_* is ignored if ACPI_FADT_WBINVD is set */ + fadt->flush_size = 0; + fadt->flush_stride = 0; /* P_CNT not supported */ fadt->duty_offset = 0; fadt->duty_width = 0; - fadt->day_alrm = 0xd; fadt->mon_alrm = 0x00; fadt->century = 0x32;
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34453 )
Change subject: sb/intel/{bd82x6x|ibexpeak}: Clear flush_* in FADT ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4282 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4281 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4280 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4279
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Arthur Heymans (Code Review)
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Christian Walter (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)