Jonathan Kollasch has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Still has ME issues near the end of raminit. ME firmware fails to run completely, and somehow inhibits further progress out of romstage. This condition impacts both the NRI and MRC code paths.
This can be partially worked around: - short JPME1 for Recovery mode; - power on, wait for boot to hang; - power off (including ATX standby); - unshort JPME1; - power on; however, rebooting after that doesn't always work. But it's enough to boot and possibly explore getting the ME going more.
- Slot 7 (x8 on 0:01.0) works as x8 of x16 - Slot 6 (x8 on 0:01.1) does not work (these lanes may be bundled for Slot 7) - Slot 5 (x4 on 0:06.0) is untested (only applicable to X9SCM, testing performed on X9SCL) - Slot 4 (x4 on 0:1c.0) works
FIXME: - ME firmware startup issue - PEG PCIe lanes - SuperIO ASL in DSDT - SuperIO hardware monitor setup for PECI - fan control
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 765 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/1
diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig new file mode 100644 index 0000000..01bc702 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -0,0 +1,53 @@ +if BOARD_SUPERMICRO_X9SCL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SUPERIO_NUVOTON_WPCM450 + select MAINBOARD_USES_IFD_GBE_REGION + +config MAINBOARD_DIR + string + default supermicro/x9scl + +config MAINBOARD_PART_NUMBER + string + default "X9SCL/X9SCM" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config VGA_BIOS_FILE + string + default "pci102b,0532.rom" + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "102b,0532" + +config PXE_ROM_ID + string + depends on PXE + default "8086:10d3" + +config CBFS_SIZE + hex + default 0x400000 + +config SUPERMICRO_BOARDID + string + default "0624" + +endif diff --git a/src/mainboard/supermicro/x9scl/Kconfig.name b/src/mainboard/supermicro/x9scl/Kconfig.name new file mode 100644 index 0000000..e0e91f1 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SCL + bool "X9SCL/X9SCM" diff --git a/src/mainboard/supermicro/x9scl/Makefile.inc b/src/mainboard/supermicro/x9scl/Makefile.inc new file mode 100644 index 0000000..3465dfe --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c diff --git a/src/mainboard/supermicro/x9scl/acpi/ec.asl b/src/mainboard/supermicro/x9scl/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/ec.asl diff --git a/src/mainboard/supermicro/x9scl/acpi/platform.asl b/src/mainboard/supermicro/x9scl/acpi/platform.asl new file mode 100644 index 0000000..0222986 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/platform.asl @@ -0,0 +1,8 @@ +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/supermicro/x9scl/acpi/superio.asl b/src/mainboard/supermicro/x9scl/acpi/superio.asl new file mode 100644 index 0000000..f248ca1 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/superio.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Finish this. */ +#if 0 +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#undef NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> +#endif diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c new file mode 100644 index 0000000..6727616 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi_tables.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/supermicro/x9scl/board_info.txt b/src/mainboard/supermicro/x9scl/board_info.txt new file mode 100644 index 0000000..a14680e --- /dev/null +++ b/src/mainboard/supermicro/x9scl/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb new file mode 100644 index 0000000..0057a1e --- /dev/null +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -0,0 +1,150 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x15d9 0x0624 inherit + device pci 00.0 on # Host bridge + end + device pci 01.0 on # PEG + end + device pci 01.1 on # PEG + end + device pci 06.0 on # PEG + end + device pci 02.0 off # iGPU + end + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) + register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) + register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) + register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 off # Management Engine Interface 1 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F) + subsystemid 0x15d9 0x1502 + end + device pci 1a.0 on # USB2 EHCI #2 + end + device pci 1b.0 off # High Definition Audio + end + device pci 1c.0 on # PCIe Port #1 + end + device pci 1c.1 off # PCIe Port #2 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 on # PCIe Port #5 (primary 574 GigE) + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 on # PCIe Port #7 (secondary 574 GigE on X9SCL+-F) + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + end + device pci 1e.0 on # PCI bridge + end + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + io 0x62 = 0x064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.307 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIOBASE + io 0x60 = 0xa80 + end + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 on # GPIO2 + end + device pnp 2e.309 on # GPIO3 + end + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0xa30 + io 0x62 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + chip drivers/ipmi + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 on end # IPMI KCS + end + chip superio/nuvoton/wpcm450 + device pnp 164e.2 on + io 0x60 = 0x03e8 + irq 0x70 = 10 + end + device pnp 164e.3 off end + device pnp 164e.6 off end + end + end + device pci 1f.2 on # SATA Controller 1 + end + device pci 1f.3 on # SMBus + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + end +end diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl new file mode 100644 index 0000000..b00a7ff --- /dev/null +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -0,0 +1,29 @@ +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 + + +#include <arch/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI 2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c new file mode 100644 index 0000000..8887c0f --- /dev/null +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#if CONFIG(USE_NATIVE_RAMINIT) +#include <northbridge/intel/sandybridge/raminit_native.h> +#else +#include <northbridge/intel/sandybridge/raminit.h> +#endif +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/wpcm450/wpcm450.h> +#include "superio.h" + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* 0:1d.0? */ + { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ + { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ + { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ + { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ + { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ + { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ + /* 0:1a.0? */ + { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ + { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ + { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ + { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ + { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ + { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +static const u16 superio_initvals[] = { + /* Global config registers */ + SUPERIO_INITVAL(0x1a, 0xc8), + SUPERIO_INITVAL(0x1b, 0x68), + SUPERIO_INITVAL(0x1c, 0x83), + SUPERIO_INITVAL(0x24, 0x24), + SUPERIO_INITVAL(0x2a, 0x00), + SUPERIO_INITVAL(0x2b, 0x42), + SUPERIO_INITVAL(0x2c, 0x80), + + SUPERIO_BANK(8), + SUPERIO_INITVAL(0x30, 0x0a), + SUPERIO_INITVAL(0x60, GPIO_PORT >> 8), + SUPERIO_INITVAL(0x61, GPIO_PORT & 0xff), + SUPERIO_INITVAL(0xe1, 0xf9), + + SUPERIO_BANK(9), + SUPERIO_INITVAL(0x30, 0x0c), + SUPERIO_INITVAL(0xe0, 0xcf), + SUPERIO_INITVAL(0xe4, 0xbd), + SUPERIO_INITVAL(0xe5, 0x42), + SUPERIO_INITVAL(0xe9, 0x10), + SUPERIO_INITVAL(0xea, 0x40), + + SUPERIO_BANK(0xa), + SUPERIO_INITVAL(0xe4, 0x60), + + SUPERIO_BANK(0xb), /* HWM & LED */ + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0x60, HWM_PORT >> 8), + SUPERIO_INITVAL(0x61, HWM_PORT & 0xff), + SUPERIO_INITVAL(0xf7, 0x07), +}; + + +static void superio_init(void) +{ + SUPERIO_UNLOCK; + for (int i = 0; i < ARRAY_SIZE(superio_initvals); i++) + SUPERIO_WRITE_INITVAL(superio_initvals[i]); + SUPERIO_LOCK; +} + +void bootblock_mainboard_early_init(void) +{ + superio_init(); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + //wpcm450_enable_dev(WPCM450_SP2, 0x164e, 0x03e8); +} + +#if CONFIG(USE_NATIVE_RAMINIT) +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} +#endif + + +void mainboard_early_init(int s3resume) +{ + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, + pci_read_config32(PCI_DEV(0, 0, 0), DEVEN) | + DEVEN_PEG10 | DEVEN_PEG11 | DEVEN_PEG60); +} + +#if !CONFIG(USE_NATIVE_RAMINIT) +int mainboard_should_reset_usb(int s3resume) +{ + return !s3resume; +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + struct pei_data pd = { + .pei_version = PEI_VERSION, + .mchbar = (uintptr_t)DEFAULT_MCHBAR, + .dmibar = (uintptr_t)DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = (uintptr_t)DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 1, /* 0=Mobile, 1=Desktop/Server */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 0, + .gbe_enable = 1, /* Boards sometimes uses PCH Intel GbE */ + .dimm_channel0_disabled = 0, /* Both DIMM enabled */ + .dimm_channel1_disabled = 0, /* Both DIMM enabled */ + .max_ddr3_freq = 1333, /* 1333=Sandy; 1600=Ivy */ + .usb_port_config = { + /* {enabled, oc_pin, cable len 0x0080=<8inches/20cm} */ + { 1, 0, 0x0040 }, + { 1, 0, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 1, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 2, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 3, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 4, 0x0040 }, + { 1, 6, 0x0040 }, + { 1, 5, 0x0040 }, + { 1, 5, 0x0040 }, + { 1, 6, 0x0040 } + }, + /* PCIe 3.0 support. As we use Ivy Bridge, let's enable it, + * but might cause some system instability ! + */ + .pcie_init = 1, + }; + + /* copy the data to output PEI */ + *pei_data = pd; + +} +#endif diff --git a/src/mainboard/supermicro/x9scl/gpio.c b/src/mainboard/supermicro/x9scl/gpio.c new file mode 100644 index 0000000..5824720 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/gpio.c @@ -0,0 +1,197 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio7 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9scl/hda_verb.c b/src/mainboard/supermicro/x9scl/hda_verb.c new file mode 100644 index 0000000..dff7f11 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/hda_verb.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9scl/superio.h b/src/mainboard/supermicro/x9scl/superio.h new file mode 100644 index 0000000..2ce69e2 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/superio.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef X9SCL_SUPERIO_H +#define X9SCL_SUPERIO_H + +#include <arch/io.h> +#include <superio/hwm5_conf.h> + +#define NUVOTON_PORT 0x2e +#define HWM_PORT 0x0a30 +#define GPIO_PORT 0x0a80 + +#define SUPERIO_BANK(x) (0x0700 | x) +#define SUPERIO_INITVAL(reg, data) ((reg << 8) | (data)) +#define HWM_BANK(x) (0x4e00 | x) +#define HWM_INITVAL SUPERIO_INITVAL + +#define SUPERIO_UNLOCK do { \ + outb(0x87, NUVOTON_PORT); \ + outb(0x87, NUVOTON_PORT); \ +} while (0) + +#define SUPERIO_LOCK do { \ + outb(0xaa, NUVOTON_PORT); \ +} while (0) + +#define SUPERIO_WRITE(reg, data) do { \ + outb((reg), NUVOTON_PORT); \ + outb((data), NUVOTON_PORT + 1); \ +} while (0) + +#define SUPERIO_WRITE_INITVAL(val) SUPERIO_WRITE((val) >> 8, (val) & 0xff) + +#define HWM_WRITE_INITVAL(val) pnp_write_hwm5_index(HWM_PORT, (val) >> 8, (val) & 0xff) + +#endif /* X9SCL_SUPERIO_H */
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#2).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Still has ME issues near the end of raminit. ME firmware fails to run completely, and somehow inhibits further progress out of romstage. This condition impacts both the NRI and MRC code paths.
This can be partially worked around: - short JPME1 for Recovery mode; - power on, wait for boot to hang; - power off (including ATX standby); - unshort JPME1; - power on; however, rebooting after that doesn't always work. But it's enough to boot and possibly explore getting the ME going more.
- Slot 7 (x8 on 0:01.0) works as x8 of x16 - Slot 6 (x8 on 0:01.1) does not work (these lanes may be bundled for Slot 7) - Slot 5 (x4 on 0:06.0) is untested (only applicable to X9SCM, testing performed on X9SCL) - Slot 4 (x4 on 0:1c.0) works
FIXME: - ME firmware startup issue - PEG PCIe lanes - SuperIO ASL in DSDT - SuperIO hardware monitor setup for PECI - fan control
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 794 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 2:
(11 comments)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 2: 0x0 0
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 11: end You should "pick up" these lone `end` (put them on the previous line)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 16: 0x0 0
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 19: end Same here, but also make sure the various `end` are aligned. It just takes an extra space after any `on`:
device pci 00.0 on end # Host bridge device pci 01.0 on end # PEG device pci 01.1 on end # PEG device pci 06.0 on end # PEG device pci 02.0 off end # iGPU
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 30: register "docking_supported" = "0" Can be dropped
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 35: register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" Can be dropped
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 41: off Why is this device off?
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 33: Scope (_SB) : { : Device (PCI0) You can collapse this:
Device (_SB.PCI0)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/early_init.c:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 45: /* 0:1d.0? */ As written on the devicetree comments, EHCI 1 is 1d.0 and EHCI2 is 1a.0
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 63: static const u16 superio_initvals[] = { Why, just why?
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/superio.h:
PS2: I'm pretty sure you can use things in src/superio/ instead.
Jonathan Kollasch has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 41: off
Why is this device off?
It is off in the OEM firmware. The ME firmware for these boards doesn't seem to provide much external functionality. Is it possible this would be a problem in romstage? If not, I'd like to defer a decision on this until I've successfully booted coreboot without any weird tricks.
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#3).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Still has ME issues near the end of raminit. ME firmware fails to run completely, and somehow inhibits further progress out of romstage. This condition impacts both the NRI and MRC code paths.
This can be partially worked around: - short JPME1 for Recovery mode; - power on, wait for boot to hang; - power off (including ATX standby); - unshort JPME1; - power on; however, rebooting after that doesn't always work. But it's enough to boot and possibly explore getting the ME going more.
- Slot 7 (x8 on 0:01.0) works as x8 of x16 - Slot 6 (x8 on 0:01.1) does not work (these lanes may be bundled for Slot 7) - Slot 5 (x4 on 0:06.0) is untested (only applicable to X9SCM, testing performed on X9SCL) - Slot 4 (x4 on 0:1c.0) works
FIXME: - ME firmware startup issue - PEG PCIe lanes - SuperIO ASL in DSDT - SuperIO hardware monitor setup for PECI - fan control
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 766 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/3
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#4).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Still has ME issues near the end of raminit. ME firmware fails to run completely, and somehow inhibits further progress out of romstage. This condition impacts both the NRI and MRC code paths.
This can be partially worked around: - short JPME1 for Recovery mode; - power on, wait for boot to hang; - power off (including ATX standby); - unshort JPME1; - power on; however, rebooting after that doesn't always work. But it's enough to boot and possibly explore getting the ME going more.
- Slot 7 (x8 on 0:01.0) works as x8 of x16 - Slot 6 (x8 on 0:01.1) does not work (these lanes may be bundled for Slot 7) - Slot 5 (x4 on 0:06.0) is untested (only applicable to X9SCM, testing performed on X9SCL) - Slot 4 (x4 on 0:1c.0) works
FIXME: - ME firmware startup issue - PEG PCIe lanes - SuperIO ASL in DSDT - SuperIO hardware monitor setup for PECI - fan control
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 764 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/4
Jonathan Kollasch has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 4:
(10 comments)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 2: 0x0
0
Done
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 11: end
You should "pick up" these lone `end` (put them on the previous line)
Done
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 16: 0x0
0
Done
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 19: end
Same here, but also make sure the various `end` are aligned. […]
Done
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 30: register "docking_supported" = "0"
Can be dropped
Done
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 35: register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
Can be dropped
Done
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 33: Scope (_SB) : { : Device (PCI0)
You can collapse this: […]
Done
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/early_init.c:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 45: /* 0:1d.0? */
As written on the devicetree comments, EHCI 1 is 1d.0 and EHCI2 is 1a. […]
Yes, I saw that. It's not quite clear (I admittedly haven't looked at PCH documentation) which of these 14 array members correspond to which of the USB balls on the PCH. I know where most ports on the integrated rate matching hub associated with each EHCI go, but I don't know exactly which array member those correspond to. These were done by autoport though, so I should probably just drop the un-validated comments.
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 63: static const u16 superio_initvals[] = {
Why, just why?
Mostly to assure myself that I've matched the configuration to the OEM firmware closely, so as to have fewer things in as much question when debugging the ME issue.
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/superio.h:
PS2:
I'm pretty sure you can use things in src/superio/ instead.
Ack
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#5).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) - Interrupt routing for G200e graphics on legacy PCI
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 697 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/5
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#6).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) - Interrupt routing for G200e graphics on legacy PCI
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 698 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/6
Hello Angel Pons, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#7).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) - Interrupt routing for G200e graphics on legacy PCI
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/superio.h 14 files changed, 698 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#8).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7)
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/x9scl.h 14 files changed, 747 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#9).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7)
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/x9scl.h 14 files changed, 769 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 9: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/early_init.c:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 45: /* 0:1d.0? */
Yes, I saw that. […]
Ack
https://review.coreboot.org/c/coreboot/+/38346/9/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/early_init.c:
https://review.coreboot.org/c/coreboot/+/38346/9/src/mainboard/supermicro/x9... PS9, Line 2: * This file is part of the coreboot project. : * : * Copyright (C) 2008-2009 coresystems GmbH : * Copyright (C) 2014 Vladimir Serbinenko : * : * This program is free software; you can redistribute it and/or : * modify it under the terms of the GNU General Public License as : * published by the Free Software Foundation; version 2 of : * the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. We use SPDX now
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/superio.h:
PS2:
Ack
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#10).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7)
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/x9scl.h 14 files changed, 700 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/10
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 10: Code-Review+1
(8 comments)
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/acpi/platform.asl:
PS10: /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/acpi/superio.asl:
PS10: /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 41: off
It is off in the OEM firmware. […]
Any updates?
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... PS10, Line 122: end Maybe pick these up?
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/dsdt.asl:
PS10: /* SPDX-License-Identifier: GPL-2.0-or-later */ /* This file is part of the coreboot project. */
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... PS10, Line 36: #include <drivers/intel/gma/acpi/default_brightness_levels.asl> Not needed anymore
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/early_init.c:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 63: static const u16 superio_initvals[] = {
Mostly to assure myself that I've matched the configuration to the OEM firmware closely, so as to ha […]
Ack
https://review.coreboot.org/c/coreboot/+/38346/9/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/early_init.c:
https://review.coreboot.org/c/coreboot/+/38346/9/src/mainboard/supermicro/x9... PS9, Line 2: * This file is part of the coreboot project. : * : * Copyright (C) 2008-2009 coresystems GmbH : * Copyright (C) 2014 Vladimir Serbinenko : * : * This program is free software; you can redistribute it and/or : * modify it under the terms of the GNU General Public License as : * published by the Free Software Foundation; version 2 of : * the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details.
We use SPDX now
Done
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/38346
to look at the new patch set (#11).
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7)
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/x9scl.h 14 files changed, 656 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/38346/11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 11: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/acpi/platform.asl:
PS10:
/* SPDX-License-Identifier: GPL-2.0-or-later */ […]
Done
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/acpi/superio.asl:
PS10:
/* SPDX-License-Identifier: GPL-2.0-or-later */ […]
Done
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... PS10, Line 122: end
Maybe pick these up?
Done
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... File src/mainboard/supermicro/x9scl/dsdt.asl:
PS10:
/* SPDX-License-Identifier: GPL-2.0-or-later */ […]
Done
https://review.coreboot.org/c/coreboot/+/38346/10/src/mainboard/supermicro/x... PS10, Line 36: #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
Not needed anymore
Done
Jonathan Kollasch has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 41: off
Any updates?
The firmware running on the ME appears to be SPS. The Supermicro UEFI/BIOS has hidden the ME PCI device by the time the OS is running. The visibility of the device does not appear to make any functional difference to romstage or ramstage code.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... File src/mainboard/supermicro/x9scl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38346/2/src/mainboard/supermicro/x9... PS2, Line 41: off
The firmware running on the ME appears to be SPS. […]
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
Patch Set 12: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38346 )
Change subject: mainboard: add Supermicro X9SCL/X9SCM ......................................................................
mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux.
Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7
To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7)
Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants)
Signed-off-by: Jonathan A. Kollasch jakllsch@kollasch.net Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- A src/mainboard/supermicro/x9scl/Kconfig A src/mainboard/supermicro/x9scl/Kconfig.name A src/mainboard/supermicro/x9scl/Makefile.inc A src/mainboard/supermicro/x9scl/acpi/ec.asl A src/mainboard/supermicro/x9scl/acpi/platform.asl A src/mainboard/supermicro/x9scl/acpi/superio.asl A src/mainboard/supermicro/x9scl/acpi_tables.c A src/mainboard/supermicro/x9scl/board_info.txt A src/mainboard/supermicro/x9scl/devicetree.cb A src/mainboard/supermicro/x9scl/dsdt.asl A src/mainboard/supermicro/x9scl/early_init.c A src/mainboard/supermicro/x9scl/gpio.c A src/mainboard/supermicro/x9scl/hda_verb.c A src/mainboard/supermicro/x9scl/x9scl.h 14 files changed, 656 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/supermicro/x9scl/Kconfig b/src/mainboard/supermicro/x9scl/Kconfig new file mode 100644 index 0000000..df6308e --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig @@ -0,0 +1,55 @@ +if BOARD_SUPERMICRO_X9SCL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select RAMINIT_ENABLE_ECC + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select SUPERIO_NUVOTON_WPCM450 + select MAINBOARD_USES_IFD_GBE_REGION + +config MAINBOARD_DIR + string + default supermicro/x9scl + +config MAINBOARD_PART_NUMBER + string + default "X9SCL/X9SCM" + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 1 + +config VGA_BIOS_FILE + string + default "pci102b,0532.rom" + +config VGA_BIOS_ID + string + depends on VGA_BIOS + default "102b,0532" + +config PXE_ROM_ID + string + depends on PXE + default "8086:10d3" + +config CBFS_SIZE + hex + default 0x400000 + +#config SUPERMICRO_BOARDID +# string +# default "0624" +# +endif diff --git a/src/mainboard/supermicro/x9scl/Kconfig.name b/src/mainboard/supermicro/x9scl/Kconfig.name new file mode 100644 index 0000000..e0e91f1 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SUPERMICRO_X9SCL + bool "X9SCL/X9SCM" diff --git a/src/mainboard/supermicro/x9scl/Makefile.inc b/src/mainboard/supermicro/x9scl/Makefile.inc new file mode 100644 index 0000000..3465dfe --- /dev/null +++ b/src/mainboard/supermicro/x9scl/Makefile.inc @@ -0,0 +1,4 @@ +bootblock-y += early_init.c +bootblock-y += gpio.c +romstage-y += early_init.c +romstage-y += gpio.c diff --git a/src/mainboard/supermicro/x9scl/acpi/ec.asl b/src/mainboard/supermicro/x9scl/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/ec.asl diff --git a/src/mainboard/supermicro/x9scl/acpi/platform.asl b/src/mainboard/supermicro/x9scl/acpi/platform.asl new file mode 100644 index 0000000..4c72ad8 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/platform.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +Method(_WAK, 1) +{ + Return (Package() { 0, 0 }) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/supermicro/x9scl/acpi/superio.asl b/src/mainboard/supermicro/x9scl/acpi/superio.asl new file mode 100644 index 0000000..0fffbe8 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#undef NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#undef NCT6776_SHOW_GPIO +#define NCT6776_SHOW_HWM + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c new file mode 100644 index 0000000..3851d04 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/acpi_tables.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/supermicro/x9scl/board_info.txt b/src/mainboard/supermicro/x9scl/board_info.txt new file mode 100644 index 0000000..a14680e --- /dev/null +++ b/src/mainboard/supermicro/x9scl/board_info.txt @@ -0,0 +1,7 @@ +Category: server +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb new file mode 100644 index 0000000..9236f6f --- /dev/null +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -0,0 +1,127 @@ +chip northbridge/intel/sandybridge + device cpu_cluster 0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0 on + subsystemid 0x15d9 0x0624 inherit + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PEG + device pci 01.1 on end # PEG + device pci 02.0 off end # iGPU + device pci 06.0 on end # PEG + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) + register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) + register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3) + register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff) + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3f" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F) + subsystemid 0x15d9 0x1502 + end + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 on # PCIe Port #5 + device pci 00.0 on end # primary 574 GigE + end + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on # PCIe Port #7 + device pci 00.0 on end # secondary 574 GigE on X9SCL+-F + end + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 on # PCI bridge + device pci 03.0 on end # Matrox G200e in BMC + end + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2, IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x060 + io 0x62 = 0x064 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.307 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 on end # GPIO0 + device pnp 2e.208 off end # GPIOA + device pnp 2e.308 on # GPIOBASE + io 0x60 = 0xa80 + end + device pnp 2e.109 off end # GPIO1 + device pnp 2e.209 on # GPIO2 + end + device pnp 2e.309 on # GPIO3 + end + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 off end # GPIO5 + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 off end # GPIO7 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, front panel LED + io 0x60 = 0xa30 + io 0x62 = 0 + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f off end # GPIO + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 off end # GPIOA + end + chip drivers/ipmi + register "wait_for_bmc" = "1" + register "bmc_boot_timeout" = "60" + device pnp ca2.0 off end # IPMI KCS + end + chip superio/nuvoton/wpcm450 + device pnp 164e.2 on + io 0x60 = 0x03e8 + irq 0x70 = 10 + end + device pnp 164e.3 off end + device pnp 164e.6 off end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/supermicro/x9scl/dsdt.asl b/src/mainboard/supermicro/x9scl/dsdt.asl new file mode 100644 index 0000000..b6c8930 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/dsdt.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT Revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20171231 /* OEM Revision */ +) +{ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + Device (PCIB) + { + Name (_ADR, 0x001E0000) + Name (_PRW, Package(){ 13, 4 }) + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0003ffff, 0, 0, 0x17 }, + }) + } + Return (Package() { + Package() { 0x0003ffff, 0, _SB.PCI0.LPCB.LNKH, 0 }, + }) + } + } + } + + Scope (_SB.PCI0.PEGP.DEV0) + { + Name (_SUN, 7) + } + + Scope (_SB.PCI0.PEG1.DEV0) + { + Name (_SUN, 6) + } + + Scope (_SB.PCI0.PEG6.DEV0) + { + Name (_SUN, 5) + } + + Scope (_SB.PCI0.RP01) + { + Device (DEV0) + { + Name (_ADR, 0x00000000) + Name (_SUN, 4) + } + } +} diff --git a/src/mainboard/supermicro/x9scl/early_init.c b/src/mainboard/supermicro/x9scl/early_init.c new file mode 100644 index 0000000..b4a39fe --- /dev/null +++ b/src/mainboard/supermicro/x9scl/early_init.c @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_def.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <bootblock_common.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <superio/nuvoton/wpcm450/wpcm450.h> +#include "x9scl.h" + +#define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1) +#define KCS_DEV PNP_DEV(X9SCL_WPCM450_PNP_BASE, 0x11) + +#define SUPERIO_INITVAL(reg, data) {(reg), (data)} +#define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x)) + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, /* ? USB0 1d.0 port 1 */ + { 1, 0, 0 }, /* ? USB1 1d.0 port 2 */ + { 1, 0, 1 }, /* ? USB2 1d.0 port 3 */ + { 1, 0, 1 }, /* ? USB3 1d.0 port 4 */ + { 1, 0, 2 }, /* ? USB4 1d.0 port 5 */ + { 1, 0, 2 }, /* ? USB5 1d.0 port 6 */ + { 1, 0, 3 }, /* ? ??? 1a.0 port 1 */ + { 1, 0, 3 }, /* ? BMC 1a.0 port 2 */ + { 1, 0, 4 }, /* ? ??? 1a.0 port 3 */ + { 1, 0, 4 }, /* ? USB11 1a.0 port 4 */ + { 1, 0, 6 }, /* ? USB12 1a.0 port 5 */ + { 1, 0, 5 }, /* ? USB13 1a.0 port 6 */ + { 1, 0, 5 }, + { 1, 0, 6 }, +}; + +static const uint8_t superio_initvals[][2] = { + /* Global config registers */ + SUPERIO_INITVAL(0x1a, 0xc8), + SUPERIO_INITVAL(0x1b, 0x68), + SUPERIO_INITVAL(0x1c, 0x83), + SUPERIO_INITVAL(0x24, 0x24), + //SUPERIO_INITVAL(0x27, 0x00), + SUPERIO_INITVAL(0x2a, 0x00), + SUPERIO_INITVAL(0x2b, 0x42), + SUPERIO_INITVAL(0x2c, 0x80), + + SUPERIO_BANK(0x9), /* GPIO[2345] */ + SUPERIO_INITVAL(0x30, 0x0c), + SUPERIO_INITVAL(0xe0, 0xcf), + SUPERIO_INITVAL(0xe4, 0xbd), + SUPERIO_INITVAL(0xe5, 0x42), + SUPERIO_INITVAL(0xe9, 0x10), + SUPERIO_INITVAL(0xea, 0x40), + SUPERIO_INITVAL(0xf0, 0xff), + SUPERIO_INITVAL(0xf1, 0x02), + + SUPERIO_BANK(0xb), /* HWM & LED */ + SUPERIO_INITVAL(0xf7, 0x07), + SUPERIO_INITVAL(0xf8, 0x40), + SUPERIO_INITVAL(0x30, 0x01), + SUPERIO_INITVAL(0x60, X9SCL_NCT6776_HWM_BASE >> 8), + SUPERIO_INITVAL(0x61, X9SCL_NCT6776_HWM_BASE & 0xff), + + SUPERIO_BANK(0x5), /* KBC */ + SUPERIO_INITVAL(0xf0, 0x83), + SUPERIO_INITVAL(0x30, 0x01), + + SUPERIO_BANK(0x0), /* FDC */ + SUPERIO_INITVAL(0x30, 0x80), + +#if 0 + SUPERIO_BANK(8), + SUPERIO_INITVAL(0x30, 0x0a), + SUPERIO_INITVAL(0x60, X9SCL_NCT6776_GPIO_BASE >> 8), + SUPERIO_INITVAL(0x61, X9SCL_NCT6776_GPIO_BASE & 0xff), + SUPERIO_INITVAL(0xe1, 0xf9), + + SUPERIO_BANK(0xa), + SUPERIO_INITVAL(0xe4, 0x60), +#endif +}; + + +static void superio_init(void) +{ + const pnp_devfn_t dev = PNP_DEV(X9SCL_NCT6776_PNP_BASE, 0); + + nuvoton_pnp_enter_conf_state(dev); + for (size_t i = 0; i < ARRAY_SIZE(superio_initvals); i++) + pnp_write_config(dev, superio_initvals[i][0], superio_initvals[i][1]); + nuvoton_pnp_exit_conf_state(dev); +} + +static void bmc_init(void) +{ + pnp_devfn_t dev = KCS_DEV; + + pnp_write_config(dev, 0x21, 0x11); + + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, X9SCL_WPCM450_KCS_BASE + 0); + pnp_set_iobase(dev, PNP_IDX_IO1, X9SCL_WPCM450_KCS_BASE + 1); + pnp_set_iobase(dev, PNP_IDX_IRQ0, 0); + pnp_set_enable(dev, 1); + +#if 0 + //wpcm450_enable_dev(WPCM450_SP2, X9SCL_WPCM450_PNP_BASE, 0x03e8); + //wpcm450_enable_dev(WPCM450_SP1, X9SCL_WPCM450_PNP_BASE, 0x02e8); +#endif + +#if 0 + dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x03e8); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x02e8); + pnp_set_enable(dev, 0); +#endif +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + superio_init(); + bmc_init(); +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_early_init(int s3resume) +{ + /* Disable IGD VGA decode, no GTT or GFX stolen */ + pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2); +} diff --git a/src/mainboard/supermicro/x9scl/gpio.c b/src/mainboard/supermicro/x9scl/gpio.c new file mode 100644 index 0000000..04ea482 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_OUTPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_INPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio7 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/supermicro/x9scl/hda_verb.c b/src/mainboard/supermicro/x9scl/hda_verb.c new file mode 100644 index 0000000..57c3cff --- /dev/null +++ b/src/mainboard/supermicro/x9scl/hda_verb.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = {}; +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/supermicro/x9scl/x9scl.h b/src/mainboard/supermicro/x9scl/x9scl.h new file mode 100644 index 0000000..0572314 --- /dev/null +++ b/src/mainboard/supermicro/x9scl/x9scl.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#ifndef X9SCL_H +#define X9SCL_H + +#define X9SCL_NCT6776_PNP_BASE 0x002e +#define X9SCL_NCT6776_HWM_BASE 0x0a30 +#define X9SCL_NCT6776_GPIO_BASE 0x0a80 +#define X9SCL_WPCM450_KCS_BASE 0x0ca2 +#define X9SCL_WPCM450_PNP_BASE 0x164e + +#endif /* X9SCL_H */
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