Change in coreboot[master]: [WIP]mb/intel/tglrvp: Add correct memory SPD settings

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coreboot-gerrit@coreboot.org

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  • Nick Vaccaro (Code Review)
  • Paul Menzel (Code Review)
  • Ravishankar Sarawadi (Code Review)
  • Srinidhi N Kaushik (Code Review)
  • Wonkyu Kim (Code Review)