coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/variant/elemi: config CSE LITE
by Chen Wisley (Code Review) 06 Nov '20

06 Nov '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47019 ) Change subject: mb/google/variant/elemi: config CSE LITE ...................................................................... mb/google/variant/elemi: config CSE LITE Config elemi to use CSE LITE BUG=b:170604353 TEST=emerge-volteer coreboot Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/47019/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 23e27ca..908c55b 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -71,4 +71,5 @@ config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31c7a743645d6a34ee34e750ba92c108b306ee09 Gerrit-Change-Number: 47019 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemi
by Chen Wisley (Code Review) 06 Nov '20

06 Nov '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47018 ) Change subject: mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemi ...................................................................... mb/google/variant/elemi: Select USE_CAR_NEM_ENHANCED_V2 for elemi BUG=b:170604353 TEST=emerge-volteer coreboot Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/47018/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index f59d82b..23e27ca 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -71,3 +71,4 @@ config BOARD_GOOGLE_ELEMI bool "-> Elemi" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select USE_CAR_NEM_ENHANCED_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a1ab6f3d57d5023523b85bfb00d48d8b70a6c1f Gerrit-Change-Number: 47018 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Move out getting the pcie_seg
by Arthur Heymans (Code Review) 06 Nov '20

06 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47297 ) Change subject: soc/intel/xeon_sp: Move out getting the pcie_seg ...................................................................... soc/intel/xeon_sp: Move out getting the pcie_seg The purpose will be to avoid passing the HOB pointer as function argument. Change-Id: Id1c30558e0305e9189757a04604bf15345e1c529 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/47297/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index de1edc8..6cb6828 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -180,6 +180,13 @@ return (atsr_size + pci_br_size); } +static uint32_t get_pcie_seg(int socket) +{ + const IIO_UDS *hob = get_iio_uds(); + + return hob->PlatformData.CpuQpiInfo[socket].PcieSegment; +} + static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { @@ -196,7 +203,7 @@ unsigned long tmp = current; uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t pcie_seg = get_pcie_seg(socket); uint32_t reg_base = hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", @@ -291,7 +298,7 @@ static unsigned long acpi_create_atsr(unsigned long current, const IIO_UDS *hob) { for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t pcie_seg = get_pcie_seg(socket); unsigned long tmp = current; bool first = true; IIO_RESOURCE_INSTANCE iio_resource = -- To view, visit https://review.coreboot.org/c/coreboot/+/47297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1c30558e0305e9189757a04604bf15345e1c529 Gerrit-Change-Number: 47297 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Use common cpu/intel romstage entry
by Arthur Heymans (Code Review) 06 Nov '20

06 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46658 ) Change subject: soc/intel/xeon_sp: Use common cpu/intel romstage entry ...................................................................... soc/intel/xeon_sp: Use common cpu/intel romstage entry This removes some boilerplate like starting the console and also adds a "start of romstage" timestamp. Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/Makefile.inc M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/romstage.c 4 files changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46658/1 diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index e449409..b09ea05 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -56,6 +56,7 @@ select MICROCODE_BLOB_NOT_HOOKED_UP select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR + select NO_SMM config MAINBOARD_USES_FSP2_0 bool diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index ea5f253..c2b8c40 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,6 +7,7 @@ bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c +romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 08ea732..674675d 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -2,6 +2,9 @@ #define __SIMPLE_DEVICE__ +#include <arch/romstage.h> +#include <cbmem.h> +#include <console/console.h> #include <device/pci.h> #include <cpu/x86/smm.h> #include <soc/pci_devs.h> @@ -24,3 +27,21 @@ *start = tseg_base; *size = tseg_limit - tseg_base; } + +void fill_postcar_frame(struct postcar_frame *pcf) +{ + /* + * We need to make sure ramstage will be run cached. At this + * point exact location of ramstage in cbmem is not known. + * Instruct postcar to cache 16 megs under cbmem top which is + * a safe bet to cover ramstage. + */ + uintptr_t top_of_ram = (uintptr_t) cbmem_top(); + + printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); + top_of_ram -= 16*MiB; + postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); + /* Cache the TSEG region */ + if (CONFIG(TSEG_STAGE_CACHE)) + postcar_enable_tseg_cache(pcf); +} diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index f3e32fd..2540c5c 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/romstage.h> -#include <cbmem.h> #include <intelblocks/rtc.h> #include <console/console.h> #include <cpu/x86/mtrr.h> @@ -9,14 +8,8 @@ #include <soc/romstage.h> #include <soc/util.h> -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(void) { - struct postcar_frame pcf; - uintptr_t top_of_ram; - - printk(BIOS_DEBUG, "FSP TempRamInit was successful...\n"); - - console_init(); rtc_init(); if (soc_get_rtc_failed()) mainboard_rtc_failed(); @@ -26,23 +19,7 @@ unlock_pam_regions(); - if (postcar_frame_init(&pcf, 1 * KiB)) - die("Unable to initialize postcar frame.\n"); - - /* - * We need to make sure ramstage will be run cached. At this point exact - * location of ramstage in cbmem is not known. Instruct postcar to cache - * 16 megs under cbmem top which is a safe bet to cover ramstage. - */ - top_of_ram = (uintptr_t)cbmem_top(); - printk(BIOS_DEBUG, "top_of_ram: 0x%lx\n", top_of_ram); - postcar_frame_add_mtrr(&pcf, top_of_ram - 16 * MiB, 16 * MiB, - MTRR_TYPE_WRBACK); - - /* Cache the memory-mapped boot media. */ - postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); save_dimm_info(); - run_postcar_phase(&pcf); } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/46658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie85df5d244fa37c41f0b3177ca325c607fa54593 Gerrit-Change-Number: 46658 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/intelp2m: Cleanup SCI, SMI macro generation and update comments
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Hello build bot (Jenkins), Maxim Polyakov, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47314 to look at the new patch set (#3). Change subject: util/intelp2m: Cleanup SCI, SMI macro generation and update comments ...................................................................... util/intelp2m: Cleanup SCI, SMI macro generation and update comments Simplify macro generation and fix-up "DEEP,EDGE_SINGLE" bug introduced in the previous commit. Also update legacy macro comments. Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M util/intelp2m/platforms/snr/macro.go 1 file changed, 6 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/47314/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233 Gerrit-Change-Number: 47314 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: util/intelp2m: Cleanup SCI and SMI macro generation and update comments
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47314 ) Change subject: util/intelp2m: Cleanup SCI and SMI macro generation and update comments ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie49874d4abbdc7d1a18d63a62ccbce970ce78233 Gerrit-Change-Number: 47314 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 17:55:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib
by Rizwan Qureshi (Code Review) 06 Nov '20

06 Nov '20

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46880 ) Change subject: soc/intel/common/block/cse: Add MCHI MCA group functions to cse lib ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46880/1/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/46880/1/src/soc/intel/common/block… PS1, Line 53: MCA_COMMIT_FILES 0x04 > I prefer to do it along with CSE FW Sync and avoid resetting multiple times in boot flow. This operation can only be done when CSE is booting from RW 1. The Set File and Commit file commands are not supported in RO because the MCHI client is only part of CE-RW 2. The Data files created in this operation are part of the RW data region which is deployed only when CSE boots from RW In order to avoid an extra reset we can make the DAM disabling as part of cse_fw_sync, like below 1. In cse_fw_sync 2. Check if CSE is booted from RO 2.1 if CSE not in RO set next BP to RW 2.2 Check if DAM disable is required by checking board SKU 2.3 if DAM change required then trigger a CSE only reset 2.4 Wait for CSE to boot into RW 2.5 Run Set file and commit file 3. Do global reset This flow needs to be confirmed, will update if this works -- To view, visit https://review.coreboot.org/c/coreboot/+/46880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bdb83daffc291c618f3193b5b4e159c3eff188e Gerrit-Change-Number: 46880 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Fri, 06 Nov 2020 17:51:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot: Add Kconfig symbol to set hashing block size
by Martin Roth (Code Review) 06 Nov '20

06 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46901 ) Change subject: security/vboot: Add Kconfig symbol to set hashing block size ...................................................................... security/vboot: Add Kconfig symbol to set hashing block size Generally, this size probably doesn't matter very much, but in the case of picasso's psp_verstage, the hash is being calculated by hardware using relatively expensive system calls. By increasing the block size, we can save roughly 140ms of boot and resume time. TEST=Build & boot see that boot time has decreased. BRANCH=Zork BUG=b:169217270 - Zork: SHA calculation in vboot takes too long Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I68eecbbdfadcbf14288dc6e849397724fb66e0b2 --- M src/security/vboot/Kconfig M src/security/vboot/vboot_logic.c 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/46901/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 094cbb9..024a746 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -369,6 +369,13 @@ hex "Keyblock preamble flags" default 0x0 +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x400 + help + Set the default hash size. Generally 1k is reasonable, but in some + cases it may improve hashing speed to increase the size. + endmenu # Keys endif # VBOOT endmenu # Verified Boot (vboot) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index dbaa883..54c8224 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -19,8 +19,6 @@ /* The max hash size to expect is for SHA512. */ #define VBOOT_MAX_HASH_SIZE VB2_SHA512_DIGEST_SIZE -#define TODO_BLOCK_SIZE 1024 - /* exports */ vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, @@ -144,7 +142,7 @@ { uint64_t load_ts; uint32_t remaining; - uint8_t block[TODO_BLOCK_SIZE]; + uint8_t block[CONFIG_VBOOT_HASH_BLOCK_SIZE]; uint8_t hash_digest[VBOOT_MAX_HASH_SIZE]; const size_t hash_digest_sz = sizeof(hash_digest); size_t block_size = sizeof(block); -- To view, visit https://review.coreboot.org/c/coreboot/+/46901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68eecbbdfadcbf14288dc6e849397724fb66e0b2 Gerrit-Change-Number: 46901 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: eldrid
by Ricardo Ribalda (Code Review) 06 Nov '20

06 Nov '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47303 ) Change subject: eldrid ...................................................................... eldrid Change-Id: I9b6d12ffd29247e795e1bbf1935b3d49c6cf5c6c Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47303/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index a926956..91fbbea 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -227,7 +227,7 @@ chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" - # The Linux Kernel does not allow an inverted BOTH_LEVEL irq + # The Linux Kernel does not allow an inverted BOTH_EDGE irq # So we need to use GpioIO() instead of GpioInt() # https://www.kernel.org/doc/Documentation/acpi/gpio-properties.txt register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" -- To view, visit https://review.coreboot.org/c/coreboot/+/47303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6d12ffd29247e795e1bbf1935b3d49c6cf5c6c Gerrit-Change-Number: 47303 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Karthik Ramasubramanian (Code Review) 06 Nov '20

06 Nov '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Nov 2020 17:39:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit November 2020