coreboot-gerrit November 2020

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Change in coreboot[master]: soc/amd/picasso: add Raven1 GPU PCI ID
by Felix Held (Code Review) 06 Nov '20

06 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47250 ) Change subject: soc/amd/picasso: add Raven1 GPU PCI ID ...................................................................... soc/amd/picasso: add Raven1 GPU PCI ID Change-Id: Id4460eb596b080dec1a63a20869182170c3388af Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/cpu.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47250/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index e79dd87..cbc3929 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -12,6 +12,8 @@ #define RAVEN2_A0_CPUID 0x00820f00 #define RAVEN2_A1_CPUID 0x00820f01 +#define RAVEN1_VBIOS_VID_DID 0x100215dd +#define RAVEN1_VBIOS_REV 0x81 #define PICASSO_VBIOS_VID_DID 0x100215d8 #define PICASSO_VBIOS_REV 0xc1 #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4460eb596b080dec1a63a20869182170c3388af Gerrit-Change-Number: 47250 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/cpu: add Raven1 CPUID to CPU table
by Felix Held (Code Review) 06 Nov '20

06 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47249 ) Change subject: soc/amd/picasso/cpu: add Raven1 CPUID to CPU table ...................................................................... soc/amd/picasso/cpu: add Raven1 CPUID to CPU table The RV1 CPUID is already in the cpu.h file, but was still missing from the CPU table in cpu.c. Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/cpu.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47249/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 4d6e98d..5979fc6 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -128,6 +128,7 @@ }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, RAVEN1_B0_CPUID}, { X86_VENDOR_AMD, PICASSO_B0_CPUID }, { X86_VENDOR_AMD, PICASSO_B1_CPUID }, { X86_VENDOR_AMD, RAVEN2_A0_CPUID }, -- To view, visit https://review.coreboot.org/c/coreboot/+/47249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089 Gerrit-Change-Number: 47249 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Tim Wawrzynczak (Code Review) 06 Nov '20

06 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 ) Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden : register "options.tsr[0].desc" = ""Memory"" : register "options.tsr[1].desc" = ""Ambient"" : register "options.tsr[2].desc" = ""Charger"" : register "options.tsr[3].desc" = ""5V regulator"" > Tim, do you have any suggestion here ? Please, let's know. […] They are two separate devices so it's kind of tricky to share registers between them -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 19:24:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board
by Lucas Chen (Code Review) 06 Nov '20

06 Nov '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47011 ) Change subject: zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board ...................................................................... zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board Adjust USB2 phy si setting fine tune on DVT for Ezkinil. BRANCH=zork BUG=b:156315391 TEST=Measuring scope timing and test usb detection Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d --- M src/mainboard/google/zork/variants/ezkinil/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47011/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 5ef2f0a..a15a33b 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -22,6 +22,32 @@ # End : OPN Performance Configuration + #USB 2.0 strength + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb3_port_force_gen1" = "{ .ports.xhci0_port0 = 1, .ports.xhci0_port1 = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/47011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d Gerrit-Change-Number: 47011 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/skx: Copy the cpx function to get the IIO HOB
by Arthur Heymans (Code Review) 06 Nov '20

06 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47295 ) Change subject: soc/intel/xeon_sp/skx: Copy the cpx function to get the IIO HOB ...................................................................... soc/intel/xeon_sp/skx: Copy the cpx function to get the IIO HOB Change-Id: Ia8ef415c36bd915931fcc60231aa624c75bba670 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 2 files changed, 13 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/47295/1 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index cce542a..e0d66d6 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -14,7 +14,7 @@ uint8_t get_iiostack_info(struct iiostack_resource *info); void xeonsp_init_cpu_config(void); - +const IIO_UDS *get_iio_uds(void); void config_reset_cpl3_csrs(void); void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 3af6483..853846c 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -46,6 +46,18 @@ * +-------------------------+ */ +const IIO_UDS *get_iio_uds(void) +{ + size_t hob_size; + static const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + + if (hob == NULL) + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + return hob; +} + static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { size_t hob_size; -- To view, visit https://review.coreboot.org/c/coreboot/+/47295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8ef415c36bd915931fcc60231aa624c75bba670 Gerrit-Change-Number: 47295 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_mini: Set unused GPIO pads to PAD_NC
by Matt DeVillier (Code Review) 06 Nov '20

06 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47191 ) Change subject: mb/purism/librem_mini: Set unused GPIO pads to PAD_NC ...................................................................... mb/purism/librem_mini: Set unused GPIO pads to PAD_NC Set pads A7, A16, B0, B1, B15, D8, D13, F3, H6-H9, H14, H16, H17 to PAD_NC as per board schematics. Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c 1 file changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/47191/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 04c8614..9311ca0 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -37,7 +37,7 @@ /* GPP_A7 - GPIO */ /* DW0: 0x44000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A7, 0, DEEP), + PAD_NC(GPP_A7, NONE), /* GPP_A8 - CLKRUN# */ /* DW0: 0x44000700, DW1: 0x00000000 */ @@ -73,7 +73,7 @@ /* GPP_A16 - GPIO */ /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST), + PAD_NC(GPP_A16, UP_20K), /* GPP_A17 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -107,11 +107,11 @@ /* GPP_B0 - Reserved */ /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_NC(GPP_B0, NONE), /* GPP_B1 - Reserved */ /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_NC(GPP_B1, NONE), /* GPP_B2 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -167,7 +167,7 @@ /* GPP_B15 - GSPI0_CS0# */ /* DW0: 0x00000701, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1), + PAD_NC(GPP_B15, NONE), /* GPP_B16 - GSPI0_CLK */ /* DW0: 0x84000601, DW1: 0x00000000 */ @@ -271,7 +271,7 @@ /* GPP_D8 - GPIO */ /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D8, 0, PLTRST), + PAD_NC(GPP_D8, NONE), /* GPP_D9 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -291,7 +291,7 @@ /* GPP_D13 - GPIO */ /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D13, 1, RSMRST), + PAD_NC(GPP_D13, NONE), /* GPP_D14 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -349,7 +349,7 @@ /* GPP_F3 - GPIO */ /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), + PAD_NC(GPP_F3, UP_20K), /* GPP_F4 - CNV_BRI_DT */ /* DW0: 0x44000700, DW1: 0x00003000 */ @@ -459,19 +459,19 @@ /* GPP_H6 - I2C3_SDA */ /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), /* GPP_H7 - I2C3_SCL */ /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + PAD_NC(GPP_H7, NONE), /* GPP_H8 - I2C4_SDA */ /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + PAD_NC(GPP_H8, NONE), /* GPP_H9 - I2C4_SCL */ /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + PAD_NC(GPP_H9, NONE), /* GPP_H10 - I2C5_SDA */ /* DW0: 0x84000603, DW1: 0x00000000 */ @@ -491,7 +491,7 @@ /* GPP_H14 - GPIO */ /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), + PAD_NC(GPP_H14, NONE), /* GPP_H15 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -499,11 +499,11 @@ /* GPP_H16 - GPIO */ /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H16, 1, RSMRST), + PAD_NC(GPP_H16, NONE), /* GPP_H17 - GPIO */ /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H17, 1, RSMRST), + PAD_NC(GPP_H17, NONE), /* GPP_H18 - CPU_C10_GATE# */ /* DW0: 0x44000700, DW1: 0x00000000 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47191 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c2ab936256d0031d7a127fbeac42c8951a0b39f Gerrit-Change-Number: 47191 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Michael Niewöhner (Code Review) 06 Nov '20

06 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > The current behaviour may have forced boards to enable the device to follow FSP, but this is preserv […] no, it is not. This disables the device for all boards, that don't have a devicetree entry setting it to "on". -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 19:05:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: Set vboot hashing block size to 36k
by Martin Roth (Code Review) 06 Nov '20

06 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46903 ) Change subject: soc/amd/picasso: Set vboot hashing block size to 36k ...................................................................... soc/amd/picasso: Set vboot hashing block size to 36k On picasso's psp_verstage, the vboot hash is being calculated by hardware using relatively expensive system calls. By increasing the block size, we can save roughly 150ms of boot and S3 resume time. TEST=Build & boot see that boot time has decreased. BRANCH=Zork BUG=b:169217270 - Zork: SHA calculation in vboot takes too long Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9 --- M src/soc/amd/picasso/Kconfig 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/46903/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 6a5b932..2e35a4b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -541,6 +541,22 @@ Runs verstage on the PSP. Only available on certain Chrome OS branded parts from AMD. +config VBOOT_HASH_BLOCK_SIZE + hex + default 0x9000 + depends on VBOOT_STARTS_BEFORE_BOOTBLOCK + help + Because the bulk of the time in psp_verstage to hash the RO cbfs is + spent in the overhead of doing svc calls, increasing the hash block + size significantly cuts the verstage hashing time as seen below. + + 4k takes 180ms + 16k takes 44ms + 32k takes 33.7ms + 36k takes 32.5ms + There's actually still room for an even bigger stack, but we've + reached a point of diminishing returns. + config CMOS_RECOVERY_BYTE hex default 0x51 -- To view, visit https://review.coreboot.org/c/coreboot/+/46903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9 Gerrit-Change-Number: 46903 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: Up stack size to 40k for vboot hash buffer
by Martin Roth (Code Review) 06 Nov '20

06 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46902 ) Change subject: soc/amd/picasso: Up stack size to 40k for vboot hash buffer ...................................................................... soc/amd/picasso: Up stack size to 40k for vboot hash buffer Increasing the vboot hash buffer size greatly speeds up the SHA calculations. Going from a standard 4k buffer to a 36k buffer takes ~150ms of the boot and resume time. TEST=Build & boot see that boot time has decreased. BRANCH=Zork BUG=b:169217270 - Zork: SHA calculation in vboot takes too long Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92 --- M src/soc/amd/picasso/memlayout_psp_verstage.ld M src/soc/amd/picasso/psp_verstage/Makefile.inc 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/46902/1 diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/picasso/memlayout_psp_verstage.ld index 1da07df..0036e9b 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/picasso/memlayout_psp_verstage.ld @@ -19,15 +19,15 @@ * should be sufficient. This is just for the function mapping the * actual stack. */ -#define PSP_VERSTAGE_TEMP_STACK_START 0x39000 +#define PSP_VERSTAGE_TEMP_STACK_START 0x32000 #define PSP_VERSTAGE_TEMP_STACK_SIZE 4K /* * The top of the stack must be 4k aligned, so set the bottom as 4k aligned * and make the size a multiple of 4k */ -#define PSP_VERSTAGE_STACK_START 0x3B000 -#define PSP_VERSTAGE_STACK_SIZE 8K +#define PSP_VERSTAGE_STACK_START 0x33000 +#define PSP_VERSTAGE_STACK_SIZE 40K ENTRY(_psp_vs_start) SECTIONS diff --git a/src/soc/amd/picasso/psp_verstage/Makefile.inc b/src/soc/amd/picasso/psp_verstage/Makefile.inc index 4f1642b..19083cdaf 100644 --- a/src/soc/amd/picasso/psp_verstage/Makefile.inc +++ b/src/soc/amd/picasso/psp_verstage/Makefile.inc @@ -4,6 +4,7 @@ verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/picasso/include verstage-generic-ccopts += -D__USER_SPACE__ CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/2lib/include/ +CFLAGS_arm += -Wstack-usage=40960 verstage-y += delay.c verstage-y += fch.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92 Gerrit-Change-Number: 46902 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Update gpio and devicetree
by Chen Wisley (Code Review) 06 Nov '20

06 Nov '20

Chen Wisley has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47039 ) Change subject: mb/google/volteer: Update gpio and devicetree ...................................................................... mb/google/volteer: Update gpio and devicetree Update gpio and devicetree for elemi. BUG=b:170604353 TEST=emerge-volteer coreboot and boot into kernel Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501 --- M src/mainboard/google/volteer/variants/elemi/Makefile.inc M src/mainboard/google/volteer/variants/elemi/overridetree.cb 2 files changed, 134 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/47039/1 diff --git a/src/mainboard/google/volteer/variants/elemi/Makefile.inc b/src/mainboard/google/volteer/variants/elemi/Makefile.inc index 9064208..b0bfc56 100644 --- a/src/mainboard/google/volteer/variants/elemi/Makefile.inc +++ b/src/mainboard/google/volteer/variants/elemi/Makefile.inc @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/elemi/overridetree.cb b/src/mainboard/google/volteer/variants/elemi/overridetree.cb index 32204c5..2139ad7 100644 --- a/src/mainboard/google/volteer/variants/elemi/overridetree.cb +++ b/src/mainboard/google/volteer/variants/elemi/overridetree.cb @@ -1,6 +1,134 @@ chip soc/intel/tigerlake - device domain 0 on - end + register "TcssAuxOri" = "1" + register "DdiPort1Hpd" = "0" + register "DdiPort2Hpd" = "0" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F8)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "50" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 40 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "1" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98357A"" + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "9" + register "usb3_port_number" = "1" + # SBU & HSL follow CC + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "4" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 on end + end + end + end + end # PMC + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/47039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b8880d485ed73aa4e65c1249c58f02c8f0c6501 Gerrit-Change-Number: 47039 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020