coreboot-gerrit November 2020

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Change in coreboot[4.11_branch]: sec/intel/txt/Kconfig: Remove the menu for including ACMs
by Angel Pons (Code Review) 08 Nov '20

08 Nov '20

Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45003 to review the following change. Change subject: sec/intel/txt/Kconfig: Remove the menu for including ACMs ...................................................................... sec/intel/txt/Kconfig: Remove the menu for including ACMs This is consistent with how other binaries (e.g. FSP) are added via Kconfig. This also makes it more visible that things need to be configured. Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/intel/txt/Kconfig 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/45003/1 diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index d828a9d..049705f 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -26,8 +26,6 @@ if INTEL_TXT -menu "Intel" - config INTEL_TXT_BIOSACM_FILE string "BIOS ACM file" default "3rdparty/blobs/soc/intel/fsp_broadwell_de/biosacm.bin" if SOC_INTEL_FSP_BROADWELL_DE @@ -71,6 +69,4 @@ string default "txt_sinit_acm.bin" -endmenu # Intel - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/45003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.11_branch Gerrit-Change-Id: I399de6270cc4c0ab3b8c8a9543aec0d68d3cfc03 Gerrit-Change-Number: 45003 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/intel/adlrvp: Adopt overridetree.cb for ADL RVP mainboards
by Subrata Banik (Code Review) 08 Nov '20

08 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47335 ) Change subject: mb/intel/adlrvp: Adopt overridetree.cb for ADL RVP mainboards ...................................................................... mb/intel/adlrvp: Adopt overridetree.cb for ADL RVP mainboards List of changes: 1. Keep devicetree.cb inside 'variants/baseboard' 2. Create variant directory for ADL RVP with external EC as 'adlrvp_p_ext_ec' 3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec' to override 'variants/baseboard/devicetree.cb' as applicable. TEST=Build and boot both ADLRVP with onboard/external EC. Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig A src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb A src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb R src/mainboard/intel/adlrvp/variants/baseboard/devicetree.cb 4 files changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47335/1 diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 97b4bf7..e82d8dd 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -31,7 +31,8 @@ config VARIANT_DIR string - default "adlrvp_p" + default "adlrvp_p" if BOARD_INTEL_ADLRVP_P + default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC config GBB_HWID string @@ -48,7 +49,11 @@ config DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config DIMM_SPD_SIZE int diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb new file mode 100644 index 0000000..e58e9fb --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb new file mode 100644 index 0000000..e58e9fb --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/baseboard/devicetree.cb similarity index 100% rename from src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb rename to src/mainboard/intel/adlrvp/variants/baseboard/devicetree.cb -- To view, visit https://review.coreboot.org/c/coreboot/+/47335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6 Gerrit-Change-Number: 47335 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: libpayload: Use typedef for OHCI enums
by Jacob Garber (Code Review) 08 Nov '20

08 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47224 ) Change subject: libpayload: Use typedef for OHCI enums ...................................................................... libpayload: Use typedef for OHCI enums The OHCI header file declares various enums as follows: enum { ... } enum_name; Since the name is at the end, this is actually declaring a variable called enum_name and *not* a type, which is causing a multiple definition error in GCC 10. Add typedef to each enum so it declares a type to prevent this. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I452c0a1b118990942aa53f1e7e77f5e8378e8975 --- M payloads/libpayload/drivers/usb/ohci_private.h 1 file changed, 16 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/47224/1 diff --git a/payloads/libpayload/drivers/usb/ohci_private.h b/payloads/libpayload/drivers/usb/ohci_private.h index 796be29..aa51490 100644 --- a/payloads/libpayload/drivers/usb/ohci_private.h +++ b/payloads/libpayload/drivers/usb/ohci_private.h @@ -36,7 +36,7 @@ // FIXME: fake typedef enum { CMD} reg; - enum { + typedef enum { NumberDownstreamPorts = 1 << 0, PowerSwitchingMode = 1 << 8, NoPowerSwitching = 1 << 9, @@ -46,17 +46,17 @@ PowerOnToPowerGoodTime = 1 << 24 } HcRhDescriptorAReg; - enum { + typedef enum { NumberDownstreamPortsMask = MASK(0, 8), PowerOnToPowerGoodTimeMask = MASK(24, 8) } HcRhDescriptorAMask; - enum { + typedef enum { DeviceRemovable = 1 << 0, PortPowerControlMask = 1 << 16 } HcRhDescriptorBReg; - enum { + typedef enum { CurrentConnectStatus = 1 << 0, PortEnableStatus = 1 << 1, PortSuspendStatus = 1 << 2, @@ -70,7 +70,8 @@ PortOverCurrentIndicatorChange = 1 << 19, PortResetStatusChange = 1 << 20 } HcRhPortStatusRead; - enum { + + typedef enum { ClearPortEnable = 1 << 0, SetPortEnable = 1 << 1, SetPortSuspend = 1 << 2, @@ -80,7 +81,7 @@ ClearPortPower = 1 << 9, } HcRhPortStatusSet; - enum { + typedef enum { LocalPowerStatus = 1 << 0, OverCurrentIndicator = 1 << 1, DeviceRemoteWakeupEnable = 1 << 15, @@ -89,18 +90,19 @@ ClearRemoteWakeupEnable = 1 << 31 } HcRhStatusReg; - enum { + typedef enum { FrameInterval = 1 << 0, FSLargestDataPacket = 1 << 16, FrameIntervalToggle = 1 << 31 } HcFmIntervalOffset; - enum { + + typedef enum { FrameIntervalMask = MASK(0, 14), FSLargestDataPacketMask = MASK(16, 15), FrameIntervalToggleMask = MASK(31, 1) } HcFmIntervalMask; - enum { + typedef enum { ControlBulkServiceRatio = 1 << 0, PeriodicListEnable = 1 << 2, IsochronousEnable = 1 << 3, @@ -112,7 +114,7 @@ RemoteWakeupEnable = 1 << 10 } HcControlReg; - enum { + typedef enum { ControlBulkServiceRatioMask = MASK(0, 2), HostControllerFunctionalStateMask = MASK(6, 2) } HcControlMask; @@ -124,7 +126,7 @@ USBSuspend = 3*HostControllerFunctionalState }; - enum { + typedef enum { HostControllerReset = 1 << 0, ControlListFilled = 1 << 1, BulkListFilled = 1 << 2, @@ -132,16 +134,16 @@ SchedulingOverrunCount = 1 << 16 } HcCommandStatusReg; - enum { + typedef enum { SchedulingOverrunCountMask = MASK(16, 2) } HcCommandStatusMask; - enum { + typedef enum { FrameRemaining = 1 << 0, FrameRemainingToggle = 1 << 31 } HcFmRemainingReg; - enum { + typedef enum { SchedulingOverrung = 1 << 0, WritebackDoneHead = 1 << 1, StartofFrame = 1 << 2, -- To view, visit https://review.coreboot.org/c/coreboot/+/47224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I452c0a1b118990942aa53f1e7e77f5e8378e8975 Gerrit-Change-Number: 47224 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: libpayload: Include missing compiler.h
by Jacob Garber (Code Review) 08 Nov '20

08 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47153 ) Change subject: libpayload: Include missing compiler.h ...................................................................... libpayload: Include missing compiler.h These header files define various structs like so: struct struct_name { ... } __packed; However, these header files do not include the compiler.h macro that defines what __packed is, so they are actually defining a variable named __packed and *not* declaring a packed struct. This leads to defining the same variable multiple times, which was caught by GCC 10. Include the missing <compiler.h> header to fix this. Change-Id: Ia67182520dc94149e06fe9e03a14b3fc2ee29973 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/libpayload/drivers/usb/uhci_private.h M payloads/libpayload/drivers/video/bitmap.h M payloads/libpayload/include/arm/arch/exception.h M payloads/libpayload/include/arm64/arch/exception.h M payloads/libpayload/include/fmap_serialized.h M payloads/libpayload/include/x86/arch/exception.h 6 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/47153/1 diff --git a/payloads/libpayload/drivers/usb/uhci_private.h b/payloads/libpayload/drivers/usb/uhci_private.h index 9df8f3d..9854f15 100644 --- a/payloads/libpayload/drivers/usb/uhci_private.h +++ b/payloads/libpayload/drivers/usb/uhci_private.h @@ -29,6 +29,8 @@ #ifndef __UHCI_PRIVATE_H #define __UHCI_PRIVATE_H +#include <compiler.h> + typedef enum { UHCI_SETUP = 0x2d, UHCI_IN = 0x69, UHCI_OUT = 0xe1 } uhci_pid_t; typedef u32 flistp_t; diff --git a/payloads/libpayload/drivers/video/bitmap.h b/payloads/libpayload/drivers/video/bitmap.h index 7a596f2..0178961 100644 --- a/payloads/libpayload/drivers/video/bitmap.h +++ b/payloads/libpayload/drivers/video/bitmap.h @@ -29,6 +29,7 @@ #ifndef __BITMAP_H__ #define __BITMAP_H__ +#include <compiler.h> #include <stdint.h> struct bitmap_file_header { diff --git a/payloads/libpayload/include/arm/arch/exception.h b/payloads/libpayload/include/arm/arch/exception.h index ee8520e..2360fd1 100644 --- a/payloads/libpayload/include/arm/arch/exception.h +++ b/payloads/libpayload/include/arm/arch/exception.h @@ -29,6 +29,7 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H +#include <compiler.h> #include <stdint.h> void exception_dispatch(u32 idx); diff --git a/payloads/libpayload/include/arm64/arch/exception.h b/payloads/libpayload/include/arm64/arch/exception.h index 1b4d58a..754c0ce 100644 --- a/payloads/libpayload/include/arm64/arch/exception.h +++ b/payloads/libpayload/include/arm64/arch/exception.h @@ -53,6 +53,7 @@ #ifndef __ASSEMBLER__ +#include <compiler.h> #include <stddef.h> #include <stdint.h> diff --git a/payloads/libpayload/include/fmap_serialized.h b/payloads/libpayload/include/fmap_serialized.h index 53a09af..f5c7d03 100644 --- a/payloads/libpayload/include/fmap_serialized.h +++ b/payloads/libpayload/include/fmap_serialized.h @@ -36,6 +36,7 @@ #ifndef FLASHMAP_SERIALIZED_H__ #define FLASHMAP_SERIALIZED_H__ +#include <compiler.h> #include <stdint.h> #define FMAP_SIGNATURE "__FMAP__" diff --git a/payloads/libpayload/include/x86/arch/exception.h b/payloads/libpayload/include/x86/arch/exception.h index d88029b..c4e8fd3 100644 --- a/payloads/libpayload/include/x86/arch/exception.h +++ b/payloads/libpayload/include/x86/arch/exception.h @@ -29,6 +29,7 @@ #ifndef _ARCH_EXCEPTION_H #define _ARCH_EXCEPTION_H +#include <compiler.h> #include <stdint.h> void exception_init_asm(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/47153 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia67182520dc94149e06fe9e03a14b3fc2ee29973 Gerrit-Change-Number: 47153 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: iii
by hsin-hsiung wang (Code Review) 08 Nov '20

08 Nov '20

hsin-hsiung wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47344 ) Change subject: iii ...................................................................... iii Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang(a)mediatek.com> Change-Id: I3e18386cd3cdfa42500d5020bd0d9635fa7562eb --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/qc_blobs A check.log 5 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47344/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 8c668ab..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 8c668ab552a02724a07f8c6e7285a5f21a61569b +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index a59fb6e..5e8dd64 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit a59fb6e3892f0629d43769a07ee7f1048a0ae1f8 +Subproject commit 5e8dd6456365461e725b53968ef8b82656d86560 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 0e4288f..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 0e4288f81f806620c65f70ee2bcf94b69d574096 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/qc_blobs b/3rdparty/qc_blobs index 6b7fe49..11b212c 160000 --- a/3rdparty/qc_blobs +++ b/3rdparty/qc_blobs @@ -1 +1 @@ -Subproject commit 6b7fe498eb782b8f9758f28dd53bb0697be0d0b0 +Subproject commit 11b212c273b930885d1bee0b00a223a73628c852 diff --git a/check.log b/check.log new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/check.log -- To view, visit https://review.coreboot.org/c/coreboot/+/47344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e18386cd3cdfa42500d5020bd0d9635fa7562eb Gerrit-Change-Number: 47344 Gerrit-PatchSet: 1 Gerrit-Owner: hsin-hsiung wang <hsin-hsiung.wang(a)mediatek.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/amd/common: Don't program GPIOs if the table isn't set
by Martin Roth (Code Review) 07 Nov '20

07 Nov '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47307 ) Change subject: soc/amd/common: Don't program GPIOs if the table isn't set ...................................................................... soc/amd/common: Don't program GPIOs if the table isn't set Currently, there's no check for the table being programmed. This skips programming a table if the table size is zero, or the pointer to the table has been set to NULL. BUG=None TEST=Set table pointer to NULL, table doesn't run. BRANCH=Zork Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: I7d09b47e7d619428b64cc0695f220fb64c71ef4c --- M src/soc/amd/common/block/gpio_banks/gpio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47307/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 74ea696..91773d9 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -187,6 +187,8 @@ size_t gev_items; const bool can_set_smi_flags = !(CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK) && ENV_SEPARATE_VERSTAGE); + if (!gpio_list_ptr || !size) + return; /* * Disable blocking wake/interrupt status generation while updating -- To view, visit https://review.coreboot.org/c/coreboot/+/47307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d09b47e7d619428b64cc0695f220fb64c71ef4c Gerrit-Change-Number: 47307 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/amd/common/psp: expand fam17h to family 17h in Kconfig help text
by Felix Held (Code Review) 07 Nov '20

07 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47275 ) Change subject: soc/amd/common/psp: expand fam17h to family 17h in Kconfig help text ...................................................................... soc/amd/common/psp: expand fam17h to family 17h in Kconfig help text This should make the help text slightly more readable. Change-Id: I9284c9c638e1d217d4605523dde004781f4343f9 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/psp/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/47275/1 diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index bf0477b..749ad8a 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -11,14 +11,14 @@ default n select SOC_AMD_COMMON_BLOCK_PSP help - Used by the PSP in AMD systems before fam17h, e.g. stoneyridge. + Used by the PSP in AMD systems before family 17h, e.g. stoneyridge. config SOC_AMD_COMMON_BLOCK_PSP_GEN2 bool default n select SOC_AMD_COMMON_BLOCK_PSP help - Used by the PSP in AMD fam17h CPUs and possibly newer ones. + Used by the PSP in AMD family 17h CPUs and possibly newer ones. config SOC_AMD_PSP_SELECTABLE_SMU_FW bool -- To view, visit https://review.coreboot.org/c/coreboot/+/47275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9284c9c638e1d217d4605523dde004781f4343f9 Gerrit-Change-Number: 47275 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/ocp/tiogapass: Add xeon_sp pch.asl
by Marc Jones (Code Review) 07 Nov '20

07 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47305 ) Change subject: mainboard/ocp/tiogapass: Add xeon_sp pch.asl ...................................................................... mainboard/ocp/tiogapass: Add xeon_sp pch.asl Use the xeon_sp pch.asl to include the intel common lpc.asl. Change-Id: I22ee9d325888808a9c775ecee0591b661e2bba4e Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/tiogapass/dsdt.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47305/1 diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl index ddc7160..7905a9c 100644 --- a/src/mainboard/ocp/tiogapass/dsdt.asl +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -15,4 +15,8 @@ #include <soc/intel/xeon_sp/acpi/globalnvs.asl> #include <cpu/intel/common/acpi/cpu.asl> #include <soc/intel/xeon_sp/acpi/uncore.asl> + Scope (\_SB.PC00) + { + #include <soc/intel/xeon_sp/acpi/pch.asl> + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47305 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22ee9d325888808a9c775ecee0591b661e2bba4e Gerrit-Change-Number: 47305 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/ocp/deltalake: Use xeon_sp pch.asl
by Marc Jones (Code Review) 07 Nov '20

07 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47304 ) Change subject: mainboard/ocp/deltalake: Use xeon_sp pch.asl ...................................................................... mainboard/ocp/deltalake: Use xeon_sp pch.asl Use the xeon_sp pch.asl to pickup the common block lpc.asl. This allows deltalake to pick up any general pch asl updates. Currently, generates the same asl. Change-Id: I5005032b030d288fdf5ca2f99d21fe8e6c752037 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/deltalake/dsdt.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47304/1 diff --git a/src/mainboard/ocp/deltalake/dsdt.asl b/src/mainboard/ocp/deltalake/dsdt.asl index 6afd4cb..1541134 100644 --- a/src/mainboard/ocp/deltalake/dsdt.asl +++ b/src/mainboard/ocp/deltalake/dsdt.asl @@ -24,6 +24,6 @@ // LPC related entries Scope (\_SB.PC00) { - #include <soc/intel/common/block/acpi/acpi/lpc.asl> + #include <soc/intel/xeon_sp/acpi/pch.asl> } } -- To view, visit https://review.coreboot.org/c/coreboot/+/47304 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5005032b030d288fdf5ca2f99d21fe8e6c752037 Gerrit-Change-Number: 47304 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: mainboard/ocp/tiogapass: Set longer BMC timeout
by Marc Jones (Code Review) 07 Nov '20

07 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47306 ) Change subject: mainboard/ocp/tiogapass: Set longer BMC timeout ...................................................................... mainboard/ocp/tiogapass: Set longer BMC timeout The BMC isn't always ready in 60 seconds if it printing debug output. Give it 90 seconds to finish before timing out in coreboot. Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/mainboard/ocp/tiogapass/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47306/1 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index 33f4090..008633b 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -74,7 +74,7 @@ chip drivers/ipmi # BMC KCS device pnp ca2.0 on end register "bmc_i2c_address" = "0x20" - register "bmc_boot_timeout" = "60" + register "bmc_boot_timeout" = "90" end end # Intel Corporation C621 Series Chipset LPC/eSPI Controller device pci 1f.2 on end # Intel Corporation C620 Series Chipset Family Power Management Controller -- To view, visit https://review.coreboot.org/c/coreboot/+/47306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3932d3e8fad067e8971e82b45b499801fc78079f Gerrit-Change-Number: 47306 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020