coreboot-gerrit November 2020

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Change in coreboot[master]: WIP: mediatek/mt8192: spm: Clean/invalidate cache before loading
by Nicolas Boichat (Code Review) 09 Nov '20

09 Nov '20

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47281 ) Change subject: WIP: mediatek/mt8192: spm: Clean/invalidate cache before loading ...................................................................... WIP: mediatek/mt8192: spm: Clean/invalidate cache before loading Unclear if necessary (but it might make sense). BUG=b:172177570 TEST=Asurada boots up to shell, suspend works Change-Id: I975a23d6ca3dd9c2a68f483dae608d1626c83c2b Signed-off-by: Nicolas Boichat <drinkcat(a)chromium.org> --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/47281/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 5613027..a6f2109 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/cache.h> #include <assert.h> #include <cbfs.h> #include <console/console.h> @@ -923,6 +924,9 @@ u32 dmem_start; u32 con0; + /* TODO: Unclear if necessary. */ + dcache_clean_invalidate_all(); + ptr = (uintptr_t) spm_firmware_binary + 0x40000000; pmem_words = spm_firmware.pmem_words; total_words = spm_firmware.total_words; -- To view, visit https://review.coreboot.org/c/coreboot/+/47281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I975a23d6ca3dd9c2a68f483dae608d1626c83c2b Gerrit-Change-Number: 47281 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Enable Wake on AC connect and disconnect
by Karthik Ramasubramanian (Code Review) 09 Nov '20

09 Nov '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47210 ) Change subject: mb/google/dedede: Enable Wake on AC connect and disconnect ...................................................................... mb/google/dedede: Enable Wake on AC connect and disconnect Handle AC connect and disconnect notifications from Embedded Controller (EC) and wake from S3/S0ix. BUG=b:172266344 TEST=Build and Boot to OS in Drawlat. Ensure that the system wakes up from suspend on AC connect and disconnect on both the TypeC ports. 276 | 2020-11-04 12:21:29 | S0ix Enter 277 | 2020-11-04 12:21:40 | S0ix Exit 278 | 2020-11-04 12:21:40 | EC Event | AC Disconnected 279 | 2020-11-04 12:21:57 | S0ix Enter 280 | 2020-11-04 12:22:03 | S0ix Exit 281 | 2020-11-04 12:22:03 | EC Event | AC Connected 282 | 2020-11-04 12:22:35 | S0ix Enter 283 | 2020-11-04 12:22:47 | S0ix Exit 284 | 2020-11-04 12:22:47 | EC Event | AC Disconnected 285 | 2020-11-04 12:23:08 | S0ix Enter 286 | 2020-11-04 12:23:16 | S0ix Exit 287 | 2020-11-04 12:23:16 | EC Event | AC Connected Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/47210/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h index d9b031e..24fe264 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/ec.h @@ -38,9 +38,12 @@ * 2. Power button * 3. Key press * 4. Mode change + * 5. AC Connect/Disconnect */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/47210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fa4ac0096548fd63af86e9f56c4c1ee25491399 Gerrit-Change-Number: 47210 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/purism/librem/ec.asl: End comment
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47115 ) Change subject: ec/purism/librem/ec.asl: End comment ...................................................................... ec/purism/librem/ec.asl: End comment End comment that (likely mistakenly) removed an EC query method. Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47115 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M src/ec/purism/librem/acpi/ec.asl 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index bf855af..143dd04 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -176,7 +176,7 @@ Notify (\_SB.SLPB, 0x80) } - /* KEY_F13 (Touchpad Enable/Disable) + /* KEY_F13 (Touchpad Enable/Disable) */ Method (_Q34) { TPSN (0x87) -- To view, visit https://review.coreboot.org/c/coreboot/+/47115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Gerrit-Change-Number: 47115 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/variants/drawcia: Update Power Limit2 minimum value
by Sumeet R Pawnikar (Code Review) 09 Nov '20

09 Nov '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47154 ) Change subject: mb/google/dedede/variants/drawcia: Update Power Limit2 minimum value ...................................................................... mb/google/dedede/variants/drawcia: Update Power Limit2 minimum value Update Power Limit2 minimum value to the same as maximum value. BUG=None BRANCH=None TEST=Build and test on drawcia system Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/47154/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index a5ff128..ce28123 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -212,7 +212,7 @@ .granularity = 200, }, .pl2 = { - .min_power = 6000, + .min_power = 20000, .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 5942121..202e0f4 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -115,7 +115,7 @@ .granularity = 200, }, .pl2 = { - .min_power = 6000, + .min_power = 20000, .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/47154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ecf1ffcc7871192ebe18eb8c3c3fd3e1193721e Gerrit-Change-Number: 47154 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/jasperlake_rvp: Update Power Limit2 minimum value
by Sumeet R Pawnikar (Code Review) 09 Nov '20

09 Nov '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47201 ) Change subject: mb/intel/jasperlake_rvp: Update Power Limit2 minimum value ...................................................................... mb/intel/jasperlake_rvp: Update Power Limit2 minimum value Update Power Limit2 (PL2) minimum value to the same as maximum value for jasperlake rvp board. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=None TEST=Build and test on jasperlake rvp board Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/47201/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 06cf4f6..abb5dc8 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -189,7 +189,7 @@ .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 6000, + .min_power = 20000, .max_power = 20000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/47201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I862f7106846de5fb37f74419807eedc3096ded8a Gerrit-Change-Number: 47201 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/pineview: Fix clearing memory
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47174 ) Change subject: nb/intel/pineview: Fix clearing memory ...................................................................... nb/intel/pineview: Fix clearing memory The regions TSEG, GSM, GMS should not be marked as cacheable resources. Change-Id: I083b096cf3ed250bca722674abe9feffdb2436d1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/pineview/northbridge.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/47174/1 diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index a04b62b..e98c16b 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -98,9 +98,9 @@ /* Report the memory regions */ ram_resource(dev, index++, 0, 640); ram_resource(dev, index++, 768, tomk - 768); - reserved_ram_resource(dev, index++, tseg_basek, tseg_sizek); - reserved_ram_resource(dev, index++, gtt_basek, gsm_sizek); - reserved_ram_resource(dev, index++, igd_basek, gms_sizek); + mmio_resource(dev, index++, tseg_basek, tseg_sizek); + mmio_resource(dev, index++, gtt_basek, gsm_sizek); + mmio_resource(dev, index++, igd_basek, gms_sizek); reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I083b096cf3ed250bca722674abe9feffdb2436d1 Gerrit-Change-Number: 47174 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*/chip: Remove unused devicetree entry
by Patrick Rudolph (Code Review) 09 Nov '20

09 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47176 ) Change subject: soc/intel/*/chip: Remove unused devicetree entry ...................................................................... soc/intel/*/chip: Remove unused devicetree entry InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 10 files changed, 1 insertion(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47176/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index aeacaa4..f3ce628 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,7 +30,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index dddbca4..01c0d23 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -18,7 +18,6 @@ register "gen3_dec" = "0x00fc0901" # FSP configuration - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 8562046..74529d0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -19,7 +19,6 @@ register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 1334749..519c3eb 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -23,7 +23,6 @@ register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 2c0c26a..e80c8ec 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -161,9 +161,7 @@ device domain 0 on - device pci 02.0 on # Integrated Graphics Device - register "InternalGfx" = "1" - end + device pci 02.0 on end # Integrated Graphics Device device pci 14.3 on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 7f428a2..dc24e9b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -230,7 +230,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 26d0f0d..7cd29b4 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -140,7 +140,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index e1b697e..956793a 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -152,7 +152,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 5e90530..f157f92 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -141,7 +141,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f752b5f..6a48ad0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -261,7 +261,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; -- To view, visit https://review.coreboot.org/c/coreboot/+/47176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Gerrit-Change-Number: 47176 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voema: config CSE LITE
by David Wu (Code Review) 09 Nov '20

09 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47203 ) Change subject: mb/google/volteer/var/voema: config CSE LITE ...................................................................... mb/google/volteer/var/voema: config CSE LITE Config voema to use CSE LITE BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09 --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47203/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 07e0043..3a53026 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -84,4 +84,5 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09 Gerrit-Change-Number: 47203 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema
by David Wu (Code Review) 09 Nov '20

09 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47159 ) Change subject: mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema ...................................................................... mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47159/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d8f1b44..07e0043 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -84,3 +84,4 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select USE_CAR_NEM_ENHANCED_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba Gerrit-Change-Number: 47159 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Skip TPM detection except on SPI
by Jes Klinke (Code Review) 09 Nov '20

09 Nov '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47049 to review the following change. Change subject: mb/google/volteer: Skip TPM detection except on SPI ...................................................................... mb/google/volteer: Skip TPM detection except on SPI Production Volteer devices have Cr50 TPM connected via SPI, depending on Cr50 firmware version it may or may not support long enough interrupt pulses for the SoC to safely be able to enable lowest power mode. Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced with Dauntless, communicating via I2C. The I2C drivers do not support being accessed early in ramstage, before chip init and memory mapping, (tlcl_lib_init() will halt with an error finding the I2C controlled base address.) Since the Dauntless device under development can be made to support longer interrupts, or a completely new interrupt signalling mode, there is no need to try to go through the same discovery as is done via SPI. This CL will skip the discovery, enabling the S0i3.4 sleep mode in all cases, on the reworked test devices. BUG=b:169526865 TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org> --- M 3rdparty/amd_blobs M src/mainboard/google/volteer/mainboard.c 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47049/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 8c668ab..e393a88 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 8c668ab552a02724a07f8c6e7285a5f21a61569b +Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index b4d6676..480a3f6 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -45,13 +45,24 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) { int ret; + if (!CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* + * Negotiation of long interrupt pulses is only supported via + * SPI. I2C is only used on reworked prototypes on which the + * TPM is replaced with Dauntless under development, it will + * use long pulses by default, or use the interrupt line in a + * different way altogether. + */ + return; + } + ret = tlcl_lib_init(); if (ret != VB2_SUCCESS) { printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { + if (cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Gerrit-Change-Number: 47049 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020