coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log
by Tim Wawrzynczak (Code Review) 09 Nov '20

09 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47182 ) Change subject: soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log ...................................................................... soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log All wakes by a PCH PCIe root port were lumped under one event source; this commit splits them up so each root port gets its own ID in the event log. BUG=b:172279061 BRANCH=volteer Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0 --- M src/soc/intel/tigerlake/elog.c 1 file changed, 42 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47182/1 diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 84f0a7e..256675d 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -2,11 +2,15 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> +#include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> +#include <types.h> + +#define PCIE_ROOT_PORT_STATUS 0x60 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +24,41 @@ } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; + }; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + uint32_t pme_status = pci_s_read_config32( + pme_map[i].devfn, + PCIE_ROOT_PORT_STATUS); + + if (pme_status == 0xFFFFFFFF || !(pme_status & BIT(16))) + continue; + + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -30,9 +69,9 @@ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - /* PCI Express (TODO: determine wake device) */ + /* PCI Express */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0 Gerrit-Change-Number: 47182 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device: Add pci_s_dev_is_wake_source function
by Tim Wawrzynczak (Code Review) 09 Nov '20

09 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47260 ) Change subject: device: Add pci_s_dev_is_wake_source function ...................................................................... device: Add pci_s_dev_is_wake_source function This function is the SIMPLE_DEVICE equivalent of `pci_dev_is_wake_source`, which is required so that elog can use this function, which since it runs in SMM as well, it uses the simple device model. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie5583c04366c9a16bc1b00a6892d39eeafe5da49 --- M src/device/pci_ops.c M src/include/device/pci_ops.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47260/1 diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 90f45bf..cb833f8 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -78,3 +78,18 @@ { die("PCI: dev is NULL!\n"); } + +bool pci_s_dev_is_wake_source(pci_devfn_t dev) +{ + unsigned int pm_cap; + uint16_t pmcs; + + pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM); + if (!pm_cap) + return false; + + pmcs = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL); + + /* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */ + return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS); +} diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index cdf02d6..1738cd1 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -209,4 +209,12 @@ return pci_s_find_capability(PCI_BDF(dev), cap); } +/* + * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and + * PME_ENABLE bits in PM control and status register. + * + * Returns true if PCI device is wake source, false otherwise. + */ +bool pci_s_dev_is_wake_source(pci_devfn_t dev); + #endif /* PCI_OPS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5583c04366c9a16bc1b00a6892d39eeafe5da49 Gerrit-Change-Number: 47260 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... mb/google/dedede/var/boten: Add LTE power on/off sequence LTE module used in boten has a specific power on/off sequence. GPIOs related to power sequnce are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: Power off -> 500ms -> Power on Configure the GPIOs based on these requirements. BUG=b:163100335 TEST=Build and boot Boten to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/variants/boten/Makefile.inc M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/boten/overridetree.cb A src/mainboard/google/dedede/variants/boten/variant.c 4 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marco Chen: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boten/Makefile.inc b/src/mainboard/google/dedede/variants/boten/Makefile.inc index a352709..67a7ab2 100644 --- a/src/mainboard/google/dedede/variants/boten/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boten/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index f889c7f..c27daa4 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -7,6 +7,9 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ + PAD_CFG_GPO(GPP_A10, 0, PLTRST), + /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ @@ -38,6 +41,8 @@ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL */ PAD_NC(GPP_H7, NONE), + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 4ec6457..4966aac 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -65,6 +65,11 @@ chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" device usb 2.3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c new file mode 100644 index 0000000..2540fc7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 12 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Add support for variant specific SMI sleep flow
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44587 ) Change subject: mb/google/dedede: Add support for variant specific SMI sleep flow ...................................................................... mb/google/dedede: Add support for variant specific SMI sleep flow This support is required to power off certain components that exist only in certain variants. BUG=None TEST=Build and boot Boten to OS. Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/smihandler.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marco Chen: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 20f0207..c50578d 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -21,6 +21,8 @@ pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); + variant_smi_sleep(slp_typ); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } @@ -41,3 +43,7 @@ { chromeec_smi_process_events(); } + +void __weak variant_smi_sleep(u8 slp_typ) +{ +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bb41e45..e7bfd86 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -36,4 +36,7 @@ */ bool variant_mem_is_half_populated(void); +/* Allow each variants to customize SMI sleep flow. */ +void variant_smi_sleep(u8 slp_typ); + #endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Gerrit-Change-Number: 44587 Gerrit-PatchSet: 8 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: driver/usb/acpi: Add power resources for devices on USB ports
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46713 ) Change subject: driver/usb/acpi: Add power resources for devices on USB ports ...................................................................... driver/usb/acpi: Add power resources for devices on USB ports Allow a USB device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: * Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. * Reset delay - Delay after reset GPIO is asserted (default 0). * Reset off delay - Delay after reset GPIO is de-asserted (default 0). * Enable GPIO - Optional, GPIO to enable device. * Enable delay - Delay after enable GPIO is asserted (default 0). * Enable off delay - Delay after enable GPIO is de-asserted (default 0). BUG=b:163100335 TEST=Ensure that the Power Resource ACPI object is added under the concerned USB device. Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46713 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 32 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 8cd9268..8afdf6f 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -44,7 +44,21 @@ bool use_custom_pld; struct acpi_pld custom_pld; + /* Does the device have a power resource? */ + bool has_power_resource; + + /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 55ef1d3..8a597e3 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -11,9 +11,10 @@ static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) { /* - * Return false if reset GPIO is not provided. + * Return false if reset GPIO is not provided or is provided as part of power + * resource. */ - if (cfg->reset_gpio.pin_count == 0) + if (cfg->has_power_resource || cfg->reset_gpio.pin_count == 0) return false; return true; @@ -61,6 +62,21 @@ acpi_dp_write(dsd); } + if (config->has_power_resource) { + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + NULL, + 0, + 0 + }; + acpi_device_add_power_res(&power_res_params); + } + acpigen_pop_len(); printk(BIOS_INFO, "%s: %s at %s\n", path, -- To view, visit https://review.coreboot.org/c/coreboot/+/46713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Gerrit-Change-Number: 46713 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: create pep.asl from lpit.asl
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47245 ) Change subject: soc/intel/common/acpi: create pep.asl from lpit.asl ...................................................................... soc/intel/common/acpi: create pep.asl from lpit.asl Copy lpit.asl to pep.asl to have a clean patch series without moving files and to be able to keep the replace-patch CB:46471 as small as possible to avoid confusion. Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47245 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 103 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl new file mode 100644 index 0000000..6159685 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0 +#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 + +#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2 +#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 +#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4 +#define LPID_DSM_ARG2_S0IX_ENTRY 5 +#define LPID_DSM_ARG2_S0IX_EXIT 6 + +External(\_SB.MS0X, MethodObj) +External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) +External(\_SB.PCI0.EGPM, MethodObj) +External(\_SB.PCI0.RGPM, MethodObj) + +Scope(\_SB) +{ + Device(LPID) + { + Name(_ADR, 0x00000000) + Name(_CID, EISAID("PNP0D80")) + Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) + Method(_DSM, 4) + { + If(Arg0 == ^UUID) { + /* + * Enum functions + */ + If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + Return(Buffer(One) {0x60}) + } + /* + * Function 1 - Get Device Constraints + */ + If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + Return(Package(5) {0, Ones, Ones, Ones, Ones}) + } + /* + * Function 2 - Get Crash Dump Device + */ + If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + Return(Buffer(One) {0x0}) + } + /* + * Function 3 - Display Off Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + } + /* + * Function 4 - Display On Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + } + /* + * Function 5 - Low Power S0 Entry Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } + } + /* + * Function 6 - Low Power S0 Exit Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } + } + } + + Return(Buffer(One) {0x00}) + } // Method(_DSM) + } // Device (LPID) +} // End Scope(\_SB) -- To view, visit https://review.coreboot.org/c/coreboot/+/47245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6 Gerrit-Change-Number: 47245 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs
by David Wu (Code Review) 09 Nov '20

09 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47228 ) Change subject: mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs ...................................................................... mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:171755775 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 --- M src/mainboard/google/volteer/variants/voema/memory/Makefile.inc M src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt 3 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/47228/1 diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc index b0ca222..3c8ea48 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt index fa24790..02e7443 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -1 +1,3 @@ DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +MT53E1G64D8NW-046 WT:E 1 (0001) diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt index f51b3af..b74da4a 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -1,4 +1,2 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. +MT53E512M64D4NW-046 WT:E +MT53E1G64D8NW-046 WT:E -- To view, visit https://review.coreboot.org/c/coreboot/+/47228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 Gerrit-Change-Number: 47228 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Add lib/timestamp-test test case
by Name of user not set (Code Review) 09 Nov '20

09 Nov '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46968 ) Change subject: tests: Add lib/timestamp-test test case ...................................................................... tests: Add lib/timestamp-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I39abfc644fef085cef2175086a0e45a040b244de --- A tests/include/stubs/timestamp.h M tests/lib/Makefile.inc A tests/lib/timestamp-test.c A tests/stubs/timestamp.c 4 files changed, 180 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46968/1 diff --git a/tests/include/stubs/timestamp.h b/tests/include/stubs/timestamp.h new file mode 100644 index 0000000..10b8159 --- /dev/null +++ b/tests/include/stubs/timestamp.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> + +void dummy_timestamp_set(uint64_t v); + +void dummy_timestamp_tick_freq_mhz_set(int v); diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..27773b7 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += timestamp-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,9 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c + +timestamp-test-srcs += tests/lib/timestamp-test.c +timestamp-test-srcs += tests/stubs/timestamp.c +timestamp-test-srcs += tests/stubs/console.c +timestamp-test-stage := romstage diff --git a/tests/lib/timestamp-test.c b/tests/lib/timestamp-test.c new file mode 100644 index 0000000..8dc103d --- /dev/null +++ b/tests/lib/timestamp-test.c @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../lib/timestamp.c" +#include <commonlib/bsd/helpers.h> +#include <tests/test.h> +#include "stubs/timestamp.h" + +/* Timestamp region definition */ +#define TIMESTAMP_REGION_SIZE (1 * KiB) +TEST_REGION(timestamp, TIMESTAMP_REGION_SIZE); + +void test_timestamp_init(void **state) +{ + timestamp_init(1000); + + assert_non_null(glob_ts_table); +} + +void test_timestamp_add(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + int i; + + timestamp_init(timestamp_base); + + timestamp_add(TS_START_ROMSTAGE, base_multipler); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); + + /* Add few timestamps to check if all of them will be added properly */ + for (i = 1; i < 10; ++i) + timestamp_add(i + 1, base_multipler * (i + 1)); + + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < 10; ++i) { + entry = &glob_ts_table->entries[i]; + assert_int_equal(i + 1, entry->entry_id); + assert_int_equal(base_multipler * (i + 1) - timestamp_base, + entry->entry_stamp); + } +} + +void test_timestamp_add_now(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + + /* Initialize with base timestamp of 1000. + * This value will be subtracted from each timestamp + * when adding it. + */ + timestamp_init(timestamp_base); + + dummy_timestamp_set(base_multipler); + + timestamp_add_now(TS_START_ROMSTAGE); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); +} + +void test_timestamp_rescale_table(void **state) +{ + const int base_multipler = 1000; + int i; + + timestamp_init(0); + + /* Add few timestamps to check if all of them will be rescaled properly */ + for (i = 1; i <= 10; ++i) + timestamp_add(i, base_multipler * i); + + /* Check if all entries were added to table */ + assert_int_equal(10, glob_ts_table->num_entries); + + timestamp_rescale_table(2, 4); + + /* Check if there is the same number of entries */ + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < glob_ts_table->num_entries; ++i) + assert_int_equal(base_multipler * (i + 1) / 4 * 2, + glob_ts_table->entries[i].entry_stamp); +} + +void test_get_us_since_boot(void **state) +{ + const int base_multipler = 10000; + const int timestamp_base = 1000; + const int freq_base = 100; + + timestamp_init(timestamp_base); + dummy_timestamp_set(base_multipler); + dummy_timestamp_tick_freq_mhz_set(freq_base); + /* There is a need to update this field manually, because cbmem hooks are not used. */ + glob_ts_table->tick_freq_mhz = freq_base; + + assert_int_equal((base_multipler - timestamp_base) / freq_base, get_us_since_boot()); +} + +int setup_timestamp_and_freq(void **state) +{ + dummy_timestamp_set(0); + dummy_timestamp_tick_freq_mhz_set(1); + + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_timestamp_init, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add_now, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_rescale_table, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_get_us_since_boot, setup_timestamp_and_freq), + }; + +#if CONFIG(COLLECT_TIMESTAMPS) + return cmocka_run_group_tests(tests, NULL, NULL); +#else + return 0; +#endif +} diff --git a/tests/stubs/timestamp.c b/tests/stubs/timestamp.c new file mode 100644 index 0000000..3fd739f --- /dev/null +++ b/tests/stubs/timestamp.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "stubs/timestamp.h" + +static uint64_t timestamp_value = 0; +static int timestamp_tick_freq_mhz_value = 1; + +/* Provides way to control timestamp value */ +void dummy_timestamp_set(uint64_t v) +{ + timestamp_value = v; +} + +/* Provides way to control timestamp tick frequency MHz value */ +void dummy_timestamp_tick_freq_mhz_set(int v) +{ + timestamp_tick_freq_mhz_value = v; +} + +/* Reimplementation of timestamp getter to control behaviour */ +uint64_t timestamp_get(void) +{ + return timestamp_value; +} + +int timestamp_tick_freq_mhz(void) +{ + return timestamp_tick_freq_mhz_value; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39abfc644fef085cef2175086a0e45a040b244de Gerrit-Change-Number: 46968 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: mediatek/mt8192: spm: Align spm_firmware_binary to 16-byte
by Nicolas Boichat (Code Review) 09 Nov '20

09 Nov '20

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47282 ) Change subject: WIP: mediatek/mt8192: spm: Align spm_firmware_binary to 16-byte ...................................................................... WIP: mediatek/mt8192: spm: Align spm_firmware_binary to 16-byte 16-byte alignement is critical, else the DMA transfer will corrupt data at 4096-byte boundaries. BUG=b:172177570 TEST=Asurada boots up to shell, suspend works Change-Id: I016062d04dd07950405d38f42e5e0ee01371c174 Signed-off-by: Nicolas Boichat <drinkcat(a)chromium.org> --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47282/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index a6f2109..4847377 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -9,7 +9,11 @@ #include <soc/spm.h> #include <timer.h> -static const u32 spm_firmware_binary[] = { +/* + * 16-byte alignement is critical, else the DMA transfer will corrupt data at + * 4096-byte boundaries. + */ +static const u32 spm_firmware_binary[] __aligned(16) = { 0x3200001e, 0x6a00001e, 0x6e00001e, 0x6800001e, 0x6200001e, 0x6000001e, 0x5e00001e, 0x5c00001e, 0x6000001e, 0x5800001e, 0x5600001e, 0x5400001e, 0x5200001e, 0x5000001e, 0x4e00001e, 0x4c00001e, 0xd402001e, 0xee01001e, -- To view, visit https://review.coreboot.org/c/coreboot/+/47282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I016062d04dd07950405d38f42e5e0ee01371c174 Gerrit-Change-Number: 47282 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Atlas: Wake up AP on AC plug
by Daisuke Nojiri (Code Review) 09 Nov '20

09 Nov '20

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47144 ) Change subject: Atlas: Wake up AP on AC plug ...................................................................... Atlas: Wake up AP on AC plug BUG=b:165328935 BRANCH=atlas TEST=emerge-atlas coreboot Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6 --- M src/mainboard/google/poppy/variants/atlas/include/variant/ec.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47144/1 diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h index 5e377f2..4caa734 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h @@ -37,7 +37,8 @@ */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6 Gerrit-Change-Number: 47144 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-MessageType: newchange

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