coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... mb/google/dedede/var/boten: Add LTE power on/off sequence LTE module used in boten has a specific power on/off sequence. GPIOs related to power sequnce are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: Power off -> 500ms -> Power on Configure the GPIOs based on these requirements. BUG=b:163100335 TEST=Build and boot Boten to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/variants/boten/Makefile.inc M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/boten/overridetree.cb A src/mainboard/google/dedede/variants/boten/variant.c 4 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marco Chen: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boten/Makefile.inc b/src/mainboard/google/dedede/variants/boten/Makefile.inc index a352709..67a7ab2 100644 --- a/src/mainboard/google/dedede/variants/boten/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boten/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index f889c7f..c27daa4 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -7,6 +7,9 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ + PAD_CFG_GPO(GPP_A10, 0, PLTRST), + /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ @@ -38,6 +41,8 @@ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL */ PAD_NC(GPP_H7, NONE), + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 4ec6457..4966aac 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -65,6 +65,11 @@ chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" device usb 2.3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c new file mode 100644 index 0000000..2540fc7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 12 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Add support for variant specific SMI sleep flow
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44587 ) Change subject: mb/google/dedede: Add support for variant specific SMI sleep flow ...................................................................... mb/google/dedede: Add support for variant specific SMI sleep flow This support is required to power off certain components that exist only in certain variants. BUG=None TEST=Build and boot Boten to OS. Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/smihandler.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marco Chen: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 20f0207..c50578d 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -21,6 +21,8 @@ pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); + variant_smi_sleep(slp_typ); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } @@ -41,3 +43,7 @@ { chromeec_smi_process_events(); } + +void __weak variant_smi_sleep(u8 slp_typ) +{ +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bb41e45..e7bfd86 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -36,4 +36,7 @@ */ bool variant_mem_is_half_populated(void); +/* Allow each variants to customize SMI sleep flow. */ +void variant_smi_sleep(u8 slp_typ); + #endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Gerrit-Change-Number: 44587 Gerrit-PatchSet: 8 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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Change in coreboot[master]: driver/usb/acpi: Add power resources for devices on USB ports
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46713 ) Change subject: driver/usb/acpi: Add power resources for devices on USB ports ...................................................................... driver/usb/acpi: Add power resources for devices on USB ports Allow a USB device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: * Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. * Reset delay - Delay after reset GPIO is asserted (default 0). * Reset off delay - Delay after reset GPIO is de-asserted (default 0). * Enable GPIO - Optional, GPIO to enable device. * Enable delay - Delay after enable GPIO is asserted (default 0). * Enable off delay - Delay after enable GPIO is de-asserted (default 0). BUG=b:163100335 TEST=Ensure that the Power Resource ACPI object is added under the concerned USB device. Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46713 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 32 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 8cd9268..8afdf6f 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -44,7 +44,21 @@ bool use_custom_pld; struct acpi_pld custom_pld; + /* Does the device have a power resource? */ + bool has_power_resource; + + /* GPIO used to take device out of reset or to put it into reset. */ struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index 55ef1d3..8a597e3 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -11,9 +11,10 @@ static bool usb_acpi_add_gpios_to_crs(struct drivers_usb_acpi_config *cfg) { /* - * Return false if reset GPIO is not provided. + * Return false if reset GPIO is not provided or is provided as part of power + * resource. */ - if (cfg->reset_gpio.pin_count == 0) + if (cfg->has_power_resource || cfg->reset_gpio.pin_count == 0) return false; return true; @@ -61,6 +62,21 @@ acpi_dp_write(dsd); } + if (config->has_power_resource) { + const struct acpi_power_res_params power_res_params = { + &config->reset_gpio, + config->reset_delay_ms, + config->reset_off_delay_ms, + &config->enable_gpio, + config->enable_delay_ms, + config->enable_off_delay_ms, + NULL, + 0, + 0 + }; + acpi_device_add_power_res(&power_res_params); + } + acpigen_pop_len(); printk(BIOS_INFO, "%s: %s at %s\n", path, -- To view, visit https://review.coreboot.org/c/coreboot/+/46713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Gerrit-Change-Number: 46713 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/common/acpi: create pep.asl from lpit.asl
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47245 ) Change subject: soc/intel/common/acpi: create pep.asl from lpit.asl ...................................................................... soc/intel/common/acpi: create pep.asl from lpit.asl Copy lpit.asl to pep.asl to have a clean patch series without moving files and to be able to keep the replace-patch CB:46471 as small as possible to avoid confusion. Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47245 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 103 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/common/block/acpi/acpi/pep.asl b/src/soc/intel/common/block/acpi/acpi/pep.asl new file mode 100644 index 0000000..6159685 --- /dev/null +++ b/src/soc/intel/common/block/acpi/acpi/pep.asl @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define LPID_DSM_ARG2_ENUM_FUNCTIONS 0 +#define LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS 1 + +#define LPID_DSM_ARG2_GET_CRASH_DUMP_DEV 2 +#define LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY 3 +#define LPID_DSM_ARG2_DISPLAY_ON_NOTIFY 4 +#define LPID_DSM_ARG2_S0IX_ENTRY 5 +#define LPID_DSM_ARG2_S0IX_EXIT 6 + +External(\_SB.MS0X, MethodObj) +External(\_SB.PCI0.LPCB.EC0.S0IX, MethodObj) +External(\_SB.PCI0.EGPM, MethodObj) +External(\_SB.PCI0.RGPM, MethodObj) + +Scope(\_SB) +{ + Device(LPID) + { + Name(_ADR, 0x00000000) + Name(_CID, EISAID("PNP0D80")) + Name(UUID, ToUUID("c4eb40a0-6cd2-11e2-bcfd-0800200c9a66")) + Method(_DSM, 4) + { + If(Arg0 == ^UUID) { + /* + * Enum functions + */ + If(Arg2 == LPID_DSM_ARG2_ENUM_FUNCTIONS) { + Return(Buffer(One) {0x60}) + } + /* + * Function 1 - Get Device Constraints + */ + If(Arg2 == LPID_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { + Return(Package(5) {0, Ones, Ones, Ones, Ones}) + } + /* + * Function 2 - Get Crash Dump Device + */ + If(Arg2 == LPID_DSM_ARG2_GET_CRASH_DUMP_DEV) { + Return(Buffer(One) {0x0}) + } + /* + * Function 3 - Display Off Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_OFF_NOTIFY) { + } + /* + * Function 4 - Display On Notification + */ + If(Arg2 == LPID_DSM_ARG2_DISPLAY_ON_NOTIFY) { + } + /* + * Function 5 - Low Power S0 Entry Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_ENTRY) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(1) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(1) + } + + /* + * Save the current PM bits then + * enable GPIO PM with MISCCFG_ENABLE_GPIO_PM_CONFIG + */ + If (CondRefOf (\_SB.PCI0.EGPM)) + { + \_SB.PCI0.EGPM () + } + } + /* + * Function 6 - Low Power S0 Exit Notification + */ + If(Arg2 == LPID_DSM_ARG2_S0IX_EXIT) { + /* Inform the EC */ + If (CondRefOf (\_SB.PCI0.LPCB.EC0.S0IX)) { + \_SB.PCI0.LPCB.EC0.S0IX(0) + } + + /* provide board level S0ix hook */ + If (CondRefOf (\_SB.MS0X)) { + \_SB.MS0X(0) + } + + /* Restore GPIO all Community PM */ + If (CondRefOf (\_SB.PCI0.RGPM)) + { + \_SB.PCI0.RGPM () + } + } + } + + Return(Buffer(One) {0x00}) + } // Method(_DSM) + } // Device (LPID) +} // End Scope(\_SB) -- To view, visit https://review.coreboot.org/c/coreboot/+/47245 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1c019039ef0c518cf678af6109ba914b7f47bb6 Gerrit-Change-Number: 47245 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs
by David Wu (Code Review) 09 Nov '20

09 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47228 ) Change subject: mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs ...................................................................... mb/google/volteer/var/voema: Add memory parts and generate DRAM IDs This change adds memory parts used by variant voema to mem_parts_used.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:171755775 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 --- M src/mainboard/google/volteer/variants/voema/memory/Makefile.inc M src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt M src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt 3 files changed, 7 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/47228/1 diff --git a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc index b0ca222..3c8ea48 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/memory/Makefile.inc @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ## This is an auto-generated file. Do not edit!! -## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. -SPD_SOURCES = placeholder.spd.hex +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E +SPD_SOURCES += lp4x-spd-3.hex # ID = 1(0b0001) Parts = MT53E1G64D8NW-046 WT:E diff --git a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt index fa24790..02e7443 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/dram_id.generated.txt @@ -1 +1,3 @@ DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +MT53E1G64D8NW-046 WT:E 1 (0001) diff --git a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt index f51b3af..b74da4a 100644 --- a/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt +++ b/src/mainboard/google/volteer/variants/voema/memory/mem_parts_used.txt @@ -1,4 +1,2 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# Generate an updated Makefile.inc and dram_id.generated.txt by running the -# gen_part_id tool from util/spd_tools/ddr4 or util/spd_tools/lp4x -# See util/spd_tools/{ddr4,lp4x}/README.md for more details and instructions. +MT53E512M64D4NW-046 WT:E +MT53E1G64D8NW-046 WT:E -- To view, visit https://review.coreboot.org/c/coreboot/+/47228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24d466f92a7e0fa3ab2f6241f0b5af025c53ed98 Gerrit-Change-Number: 47228 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: tests: Add lib/timestamp-test test case
by Name of user not set (Code Review) 09 Nov '20

09 Nov '20

Name of user not set #1003143 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46968 ) Change subject: tests: Add lib/timestamp-test test case ...................................................................... tests: Add lib/timestamp-test test case Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I39abfc644fef085cef2175086a0e45a040b244de --- A tests/include/stubs/timestamp.h M tests/lib/Makefile.inc A tests/lib/timestamp-test.c A tests/stubs/timestamp.c 4 files changed, 180 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46968/1 diff --git a/tests/include/stubs/timestamp.h b/tests/include/stubs/timestamp.h new file mode 100644 index 0000000..10b8159 --- /dev/null +++ b/tests/include/stubs/timestamp.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> + +void dummy_timestamp_set(uint64_t v); + +void dummy_timestamp_tick_freq_mhz_set(int v); diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 3062bca..27773b7 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -4,6 +4,7 @@ tests-y += b64_decode-test tests-y += hexstrtobin-test tests-y += imd-test +tests-y += timestamp-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -17,4 +18,9 @@ imd-test-srcs += tests/lib/imd-test.c imd-test-srcs += tests/stubs/console.c -imd-test-srcs += src/lib/imd.c \ No newline at end of file +imd-test-srcs += src/lib/imd.c + +timestamp-test-srcs += tests/lib/timestamp-test.c +timestamp-test-srcs += tests/stubs/timestamp.c +timestamp-test-srcs += tests/stubs/console.c +timestamp-test-stage := romstage diff --git a/tests/lib/timestamp-test.c b/tests/lib/timestamp-test.c new file mode 100644 index 0000000..8dc103d --- /dev/null +++ b/tests/lib/timestamp-test.c @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../lib/timestamp.c" +#include <commonlib/bsd/helpers.h> +#include <tests/test.h> +#include "stubs/timestamp.h" + +/* Timestamp region definition */ +#define TIMESTAMP_REGION_SIZE (1 * KiB) +TEST_REGION(timestamp, TIMESTAMP_REGION_SIZE); + +void test_timestamp_init(void **state) +{ + timestamp_init(1000); + + assert_non_null(glob_ts_table); +} + +void test_timestamp_add(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + int i; + + timestamp_init(timestamp_base); + + timestamp_add(TS_START_ROMSTAGE, base_multipler); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); + + /* Add few timestamps to check if all of them will be added properly */ + for (i = 1; i < 10; ++i) + timestamp_add(i + 1, base_multipler * (i + 1)); + + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < 10; ++i) { + entry = &glob_ts_table->entries[i]; + assert_int_equal(i + 1, entry->entry_id); + assert_int_equal(base_multipler * (i + 1) - timestamp_base, + entry->entry_stamp); + } +} + +void test_timestamp_add_now(void **state) +{ + const int base_multipler = 2000; + const int timestamp_base = 1000; + struct timestamp_entry *entry; + + /* Initialize with base timestamp of 1000. + * This value will be subtracted from each timestamp + * when adding it. + */ + timestamp_init(timestamp_base); + + dummy_timestamp_set(base_multipler); + + timestamp_add_now(TS_START_ROMSTAGE); + + assert_int_equal(1, glob_ts_table->num_entries); + + entry = &glob_ts_table->entries[0]; + + assert_int_equal(1, entry->entry_id); + assert_int_equal(base_multipler - timestamp_base, /* Added timestamp reduced by base */ + entry->entry_stamp); +} + +void test_timestamp_rescale_table(void **state) +{ + const int base_multipler = 1000; + int i; + + timestamp_init(0); + + /* Add few timestamps to check if all of them will be rescaled properly */ + for (i = 1; i <= 10; ++i) + timestamp_add(i, base_multipler * i); + + /* Check if all entries were added to table */ + assert_int_equal(10, glob_ts_table->num_entries); + + timestamp_rescale_table(2, 4); + + /* Check if there is the same number of entries */ + assert_int_equal(10, glob_ts_table->num_entries); + + for (i = 0; i < glob_ts_table->num_entries; ++i) + assert_int_equal(base_multipler * (i + 1) / 4 * 2, + glob_ts_table->entries[i].entry_stamp); +} + +void test_get_us_since_boot(void **state) +{ + const int base_multipler = 10000; + const int timestamp_base = 1000; + const int freq_base = 100; + + timestamp_init(timestamp_base); + dummy_timestamp_set(base_multipler); + dummy_timestamp_tick_freq_mhz_set(freq_base); + /* There is a need to update this field manually, because cbmem hooks are not used. */ + glob_ts_table->tick_freq_mhz = freq_base; + + assert_int_equal((base_multipler - timestamp_base) / freq_base, get_us_since_boot()); +} + +int setup_timestamp_and_freq(void **state) +{ + dummy_timestamp_set(0); + dummy_timestamp_tick_freq_mhz_set(1); + + return 0; +} + +int main(void) +{ + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup(test_timestamp_init, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_add_now, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_timestamp_rescale_table, setup_timestamp_and_freq), + cmocka_unit_test_setup(test_get_us_since_boot, setup_timestamp_and_freq), + }; + +#if CONFIG(COLLECT_TIMESTAMPS) + return cmocka_run_group_tests(tests, NULL, NULL); +#else + return 0; +#endif +} diff --git a/tests/stubs/timestamp.c b/tests/stubs/timestamp.c new file mode 100644 index 0000000..3fd739f --- /dev/null +++ b/tests/stubs/timestamp.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "stubs/timestamp.h" + +static uint64_t timestamp_value = 0; +static int timestamp_tick_freq_mhz_value = 1; + +/* Provides way to control timestamp value */ +void dummy_timestamp_set(uint64_t v) +{ + timestamp_value = v; +} + +/* Provides way to control timestamp tick frequency MHz value */ +void dummy_timestamp_tick_freq_mhz_set(int v) +{ + timestamp_tick_freq_mhz_value = v; +} + +/* Reimplementation of timestamp getter to control behaviour */ +uint64_t timestamp_get(void) +{ + return timestamp_value; +} + +int timestamp_tick_freq_mhz(void) +{ + return timestamp_tick_freq_mhz_value; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39abfc644fef085cef2175086a0e45a040b244de Gerrit-Change-Number: 46968 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1003143 Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: mediatek/mt8192: spm: Align spm_firmware_binary to 16-byte
by Nicolas Boichat (Code Review) 09 Nov '20

09 Nov '20

Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47282 ) Change subject: WIP: mediatek/mt8192: spm: Align spm_firmware_binary to 16-byte ...................................................................... WIP: mediatek/mt8192: spm: Align spm_firmware_binary to 16-byte 16-byte alignement is critical, else the DMA transfer will corrupt data at 4096-byte boundaries. BUG=b:172177570 TEST=Asurada boots up to shell, suspend works Change-Id: I016062d04dd07950405d38f42e5e0ee01371c174 Signed-off-by: Nicolas Boichat <drinkcat(a)chromium.org> --- M src/soc/mediatek/mt8192/spm.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47282/1 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index a6f2109..4847377 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -9,7 +9,11 @@ #include <soc/spm.h> #include <timer.h> -static const u32 spm_firmware_binary[] = { +/* + * 16-byte alignement is critical, else the DMA transfer will corrupt data at + * 4096-byte boundaries. + */ +static const u32 spm_firmware_binary[] __aligned(16) = { 0x3200001e, 0x6a00001e, 0x6e00001e, 0x6800001e, 0x6200001e, 0x6000001e, 0x5e00001e, 0x5c00001e, 0x6000001e, 0x5800001e, 0x5600001e, 0x5400001e, 0x5200001e, 0x5000001e, 0x4e00001e, 0x4c00001e, 0xd402001e, 0xee01001e, -- To view, visit https://review.coreboot.org/c/coreboot/+/47282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I016062d04dd07950405d38f42e5e0ee01371c174 Gerrit-Change-Number: 47282 Gerrit-PatchSet: 1 Gerrit-Owner: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Atlas: Wake up AP on AC plug
by Daisuke Nojiri (Code Review) 09 Nov '20

09 Nov '20

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47144 ) Change subject: Atlas: Wake up AP on AC plug ...................................................................... Atlas: Wake up AP on AC plug BUG=b:165328935 BRANCH=atlas TEST=emerge-atlas coreboot Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6 --- M src/mainboard/google/poppy/variants/atlas/include/variant/ec.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47144/1 diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h index 5e377f2..4caa734 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/ec.h @@ -37,7 +37,8 @@ */ #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)) #define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47144 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95676d785bfc1488a8c1bdd3d56f2c38d95f3fb6 Gerrit-Change-Number: 47144 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/common/pmc: Add functions for IPC mailbox in ACPI
by Duncan Laurie (Code Review) 09 Nov '20

09 Nov '20

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46259 ) Change subject: intel/common/pmc: Add functions for IPC mailbox in ACPI ...................................................................... intel/common/pmc: Add functions for IPC mailbox in ACPI This change adds two functions that provide an IPC mailbox method via ACPI for runtime clock configuration. pmc_acpi_fill_ssdt_ipc_write_method() will provide a method in the SSDT that can be called by other ACPI devices to send an IPC mailbox command. This function is exported because some SOCs override the default PMC device and need to call this function to write the method into the SSDT. pmc_acpi_set_pci_clock() will call the method defined by the previous function to enable or disable the PCIe SRCCLK for a specified root port and clock pin. It can be called by the PCIe root port after turning off power to the attached device. BUG=b:160996445 TEST=boot on volteer device and disassemble the SSDT to ensure that this method exists. Signed-off-by: Duncan Laurie <dlaurie(a)google.com> Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0 --- M src/soc/intel/common/block/include/intelblocks/pmc.h M src/soc/intel/common/block/pmc/Kconfig M src/soc/intel/common/block/pmc/pmc.c 3 files changed, 175 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46259/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 75e2127..b70d4dd 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -60,4 +60,27 @@ */ const struct device *soc_get_pmc_mux_device(int port_number); +/* + * Provides an ACPI method in the SSDT to write to the IPC mailbox which is + * defined in the PMC device MMIO address space. + * + * One possible use of this method is to to enable/disable the clock for a + * particular PCIe root port at runtime when the device is in D3 state. + * + * The ACPI method takes 7 arguments: + * IPCW (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) + * + * And can return: + * 0 = success + * 1 = error + * 2 = timeout + */ +void pmc_acpi_fill_ssdt_ipc_write_method(void); + +/* + * Call the ACPI method to write to the IPC mailbox and enable/disable the + * specified clock pin connected to the specified PCIe root port. + */ +void pmc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable); + #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index ce41b23..cb6d888 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -13,6 +13,14 @@ config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y +config PMC_IPC_MAILBOX_ACPI_INTERFACE + bool + default n + depends on HAVE_ACPI_TABLES + help + Enable this to have the PMC IPC mailbox ACPI interface added + to the SSDT for use by other drivers. + endif # SOC_INTEL_COMMON_BLOCK_PMC config PMC_INVALID_READ_AFTER_WRITE diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 24f28e3..76eaddb 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpigen.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> @@ -9,6 +10,16 @@ #include <device/pci_ids.h> #include <intelblocks/pmc.h> #include <soc/pci_devs.h> +#include <soc/iomap.h> + +/* PMC IPC Mailbox Interface. */ +#define PMC_IPC_CMD 0x00 /* IPC command */ +#define PMC_IPC_CMD_OFFSET_COMMAND 0 /* IPC command.COMMAND */ +#define PMC_IPC_CMD_OFFSET_SUB_ID 12 /* IPC command.SUB_ID */ +#define PMC_IPC_CMD_OFFSET_SIZE 16 /* IPC command.SIZE */ +#define PMC_IPC_CMD_SET_PCIE_CLOCK 0xAC /* IPC command: Set PCIe Clock */ +#define PMC_IPC_STS 0x04 /* IPC Status */ +#define PMC_IPC_WBUF 0x80 /* IPC Write Buffer */ /* SoC overrides */ @@ -98,6 +109,138 @@ } } +void pmc_acpi_fill_ssdt_ipc_write_method(void) +{ + const struct fieldlist ipcw_fields[] = { + FIELDLIST_OFFSET(PMC_IPC_CMD), /* Command */ + FIELDLIST_NAMESTR("ICMD", 32), /* Command Register */ + FIELDLIST_OFFSET(PMC_IPC_STS), /* Status */ + FIELDLIST_NAMESTR("IBSY", 1), /* Status Busy */ + FIELDLIST_NAMESTR("IERR", 1), /* Status Error */ + FIELDLIST_OFFSET(PMC_IPC_WBUF), /* Write Buffer */ + FIELDLIST_NAMESTR("IWB0", 32), /* Write Buffer 0 */ + FIELDLIST_NAMESTR("IWB1", 32), /* Write Buffer 1 */ + FIELDLIST_NAMESTR("IWB2", 32), /* Write Buffer 2 */ + FIELDLIST_NAMESTR("IWB3", 32), /* Write Buffer 3 */ + }; + const struct opregion ipcw_opregion = OPREGION("IPCS", SYSTEMMEMORY, + PCH_PWRM_BASE_ADDRESS, 0xff); + + if (!CONFIG(CONFIG_PMC_IPC_MAILBOX_ACPI_INTERFACE)) + return; + + acpigen_write_method_serialized("IPCW", 7); + + acpigen_write_opregion(&ipcw_opregion); + acpigen_write_field("IPCS", ipcw_fields, ARRAY_SIZE(ipcw_fields), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + /* Fill write buffer data registers. */ + acpigen_write_store_op_to_namestr(ARG3_OP, "IWB0"); + acpigen_write_store_op_to_namestr(ARG4_OP, "IWB1"); + acpigen_write_store_op_to_namestr(ARG5_OP, "IWB2"); + acpigen_write_store_op_to_namestr(ARG6_OP, "IWB3"); + + /* Program the command register with command and size of write data. */ + acpigen_write_store_int_to_op(0, LOCAL0_OP); + + /* Local0 += (Arg0 << PMC_IPC_CMD_OFFSET_COMMAND) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG0_OP, PMC_IPC_CMD_OFFSET_COMMAND); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_OFFSET_SUB_ID) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG1_OP, PMC_IPC_CMD_OFFSET_SUB_ID); + acpigen_emit_byte(LOCAL0_OP); + + /* Local0 += (Arg1 << PMC_IPC_CMD_OFFSET_SIZE) */ + acpigen_emit_byte(ADD_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_shiftleft_op_int(ARG2_OP, PMC_IPC_CMD_OFFSET_SIZE); + acpigen_emit_byte(LOCAL0_OP); + + /* Start mailbox command with one 32bit write. */ + acpigen_write_store_op_to_namestr(LOCAL0_OP, "ICMD"); + + /* Read status register to get busy/error status for up to 10ms. */ + acpigen_write_store_int_to_op(10, LOCAL1_OP); + + /* While (Local0 > 0) */ + acpigen_emit_byte(WHILE_OP); + acpigen_write_len_f(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_emit_byte(ZERO_OP); + /* If (IBSY == 0) { Return (SUCCESS) } */ + acpigen_write_if_lequal_namestr_int("IBSY", 0); + acpigen_write_return_integer(0); + acpigen_pop_len(); + /* If (IERR == 1) { Return (ERROR) } */ + acpigen_write_if_lequal_namestr_int("IERR", 1); + acpigen_write_return_integer(1); + acpigen_pop_len(); + /* Sleep (1) */ + acpigen_write_sleep(1); + /* Decrement (Local0) */ + acpigen_emit_byte(DECREMENT_OP); + acpigen_emit_byte(LOCAL1_OP); + acpigen_pop_len(); /* While */ + /* Return (TIMEOUT) */ + acpigen_write_return_integer(2); + + acpigen_pop_len(); /* Method */ +} + +void pmc_acpi_set_pci_clock(unsigned int pcie_rp, unsigned int clock_pin, bool enable) +{ + const uint32_t data[] = { + 1 << clock_pin, /* Clock pin to be modified */ + (enable ? 0 : 1) << clock_pin, /* Clock pin to set */ + 1 << pcie_rp, /* PCIe root port to be modified */ + (enable ? 0 : 1) << pcie_rp, /* PCIe root port to set */ + }; + const char *method = acpi_device_path_join(pcidev_path_on_root(PCH_DEVFN_PMC), "IPCW"); + + if (!CONFIG(CONFIG_PMC_IPC_MAILBOX_ACPI_INTERFACE)) + return; + + if (!method) { + printk(BIOS_ERR, "%s: Unable to find PMC device IPCW method\n", __func__); + return; + } + + /* + * The PMC IPC mailbox write method takes 7 arguments: + * IPCW (COMMAND, SUB_ID, SIZE, DATA0, DATA1, DATA2, DATA3) + */ + acpigen_emit_namestring(method); + acpigen_write_integer(PMC_IPC_CMD_SET_PCIE_CLOCK); + acpigen_write_integer(0); + acpigen_write_integer(sizeof(data)); + acpigen_write_integer(data[0]); + acpigen_write_integer(data[1]); + acpigen_write_integer(data[2]); + acpigen_write_integer(data[3]); +} + +static void pmc_fill_ssdt(const struct device *dev) +{ + const char *scope = acpi_device_scope(dev); + + if (!scope) + return; + + acpigen_write_scope(scope); + + /* Define IPC Write Method */ + pmc_acpi_fill_ssdt_ipc_write_method(); + + acpigen_pop_len(); /* Scope */ +} + static struct device_operations device_ops = { .read_resources = pch_pmc_read_resources, .set_resources = pci_dev_set_resources, @@ -105,6 +248,7 @@ .init = pmc_soc_init, .ops_pci = &pci_dev_ops_pci, .scan_bus = scan_static_bus, + .acpi_fill_ssdt = pmc_fill_ssdt, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I95f5a1ba2bc6905e0f8ce0e8b2342ad1287a23a0 Gerrit-Change-Number: 46259 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Utilize vbt data size Kconfig option
by Srinidhi N Kaushik (Code Review) 09 Nov '20

09 Nov '20

Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47209 ) Change subject: soc/intel/tigerlake: Utilize vbt data size Kconfig option ...................................................................... soc/intel/tigerlake: Utilize vbt data size Kconfig option From Tigerlake FSP v3373 onwards vbt binary size changed from 8KiB to 9KiB. Commit cf5d58328fe004d967466be42de62d6bab4c3133 had changed the size from 8 to 9 Kib in drivers/gma. This change makes use of Kconfig option to pick the size for tigerlake. BUG=b:171401992 BRANCH=none TEST=build and boot delbin and verify fw screen is loaded Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Change-Id: I21a0bba9ae01bac326f0f931641c98e8d308310f --- M src/soc/intel/tigerlake/Kconfig 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/47209/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index ed35bd6..b9a5b60 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -186,6 +186,10 @@ config TPM_CR50 select CR50_USE_LONG_INTERRUPT_PULSES +config VBT_DATA_SIZE_KB + int + default 9 + config VBOOT select VBOOT_SEPARATE_VERSTAGE select VBOOT_MUST_REQUEST_DISPLAY -- To view, visit https://review.coreboot.org/c/coreboot/+/47209 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21a0bba9ae01bac326f0f931641c98e8d308310f Gerrit-Change-Number: 47209 Gerrit-PatchSet: 1 Gerrit-Owner: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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