coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/*/chip: Remove unused devicetree entry
by Patrick Rudolph (Code Review) 09 Nov '20

09 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47176 ) Change subject: soc/intel/*/chip: Remove unused devicetree entry ...................................................................... soc/intel/*/chip: Remove unused devicetree entry InternalGfx isn't used so drop it. Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb M src/soc/intel/cannonlake/chip.h M src/soc/intel/elkhartlake/chip.h M src/soc/intel/icelake/chip.h M src/soc/intel/jasperlake/chip.h M src/soc/intel/tigerlake/chip.h 10 files changed, 1 insertion(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/47176/1 diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index aeacaa4..f3ce628 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -30,7 +30,6 @@ # FSP configuration register "SaGv" = "SaGv_Enabled" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index dddbca4..01c0d23 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -18,7 +18,6 @@ register "gen3_dec" = "0x00fc0901" # FSP configuration - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "SataSalpSupport" = "1" register "SataMode" = "Sata_AHCI" diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 8562046..74529d0 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -19,7 +19,6 @@ register "SataMode" = "Sata_AHCI" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 1334749..519c3eb 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -23,7 +23,6 @@ register "SataPortsDevSlp[0]" = "1" register "SataPortsDevSlp[1]" = "1" register "SataPortsDevSlp[2]" = "1" - register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 2c0c26a..e80c8ec 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -161,9 +161,7 @@ device domain 0 on - device pci 02.0 on # Integrated Graphics Device - register "InternalGfx" = "1" - end + device pci 02.0 on end # Integrated Graphics Device device pci 14.3 on chip drivers/wifi/generic register "wake" = "PME_B0_EN_BIT" diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 7f428a2..dc24e9b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -230,7 +230,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 26d0f0d..7cd29b4 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -140,7 +140,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index e1b697e..956793a 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -152,7 +152,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 5e90530..f157f92 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -141,7 +141,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f752b5f..6a48ad0 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -261,7 +261,6 @@ /* Gfx related */ uint8_t IgdDvmt50PreAlloc; - uint8_t InternalGfx; uint8_t SkipExtGfxScan; uint32_t GraphicsConfigPtr; -- To view, visit https://review.coreboot.org/c/coreboot/+/47176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12f424d8d883e065ef8d007e56a8bff41a7fae53 Gerrit-Change-Number: 47176 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voema: config CSE LITE
by David Wu (Code Review) 09 Nov '20

09 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47203 ) Change subject: mb/google/volteer/var/voema: config CSE LITE ...................................................................... mb/google/volteer/var/voema: config CSE LITE Config voema to use CSE LITE BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09 --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47203/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index 07e0043..3a53026 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -84,4 +84,5 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select SOC_INTEL_CSE_LITE_SKU select USE_CAR_NEM_ENHANCED_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ca82ce844e6367da70ed052445943572ae7b09 Gerrit-Change-Number: 47203 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema
by David Wu (Code Review) 09 Nov '20

09 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47159 ) Change subject: mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema ...................................................................... mb/google/variant/voema: Select USE_CAR_NEM_ENHANCED_V2 for voema BUG=b:171755775 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba --- M src/mainboard/google/volteer/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/47159/1 diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name index d8f1b44..07e0043 100644 --- a/src/mainboard/google/volteer/Kconfig.name +++ b/src/mainboard/google/volteer/Kconfig.name @@ -84,3 +84,4 @@ config BOARD_GOOGLE_VOEMA bool "-> Voema" select BOARD_GOOGLE_BASEBOARD_VOLTEER + select USE_CAR_NEM_ENHANCED_V2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47159 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibedbbe8f9ac039cbde114ace3266ec067a4003ba Gerrit-Change-Number: 47159 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/volteer: Skip TPM detection except on SPI
by Jes Klinke (Code Review) 09 Nov '20

09 Nov '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47049 to review the following change. Change subject: mb/google/volteer: Skip TPM detection except on SPI ...................................................................... mb/google/volteer: Skip TPM detection except on SPI Production Volteer devices have Cr50 TPM connected via SPI, depending on Cr50 firmware version it may or may not support long enough interrupt pulses for the SoC to safely be able to enable lowest power mode. Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced with Dauntless, communicating via I2C. The I2C drivers do not support being accessed early in ramstage, before chip init and memory mapping, (tlcl_lib_init() will halt with an error finding the I2C controlled base address.) Since the Dauntless device under development can be made to support longer interrupts, or a completely new interrupt signalling mode, there is no need to try to go through the same discovery as is done via SPI. This CL will skip the discovery, enabling the S0i3.4 sleep mode in all cases, on the reworked test devices. BUG=b:169526865 TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org> --- M 3rdparty/amd_blobs M src/mainboard/google/volteer/mainboard.c 2 files changed, 13 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47049/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 8c668ab..e393a88 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 8c668ab552a02724a07f8c6e7285a5f21a61569b +Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index b4d6676..480a3f6 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -45,13 +45,24 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) { int ret; + if (!CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) { + /* + * Negotiation of long interrupt pulses is only supported via + * SPI. I2C is only used on reworked prototypes on which the + * TPM is replaced with Dauntless under development, it will + * use long pulses by default, or use the interrupt line in a + * different way altogether. + */ + return; + } + ret = tlcl_lib_init(); if (ret != VB2_SUCCESS) { printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret); return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { + if (cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/47049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce Gerrit-Change-Number: 47049 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHz
by Johnny Li (Code Review) 09 Nov '20

09 Nov '20

Johnny Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47225 ) Change subject: mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHz ...................................................................... mb/google/volteer/variants/volteer2: Tune I2C3 camera bus freq 400 kHz The current I2C3 bus frequency is 341 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, sda_hold value for I2C3 to bring the bus frequency closer to 400kHz. BUG=b:153588771 TEST=Verified that I2C3 frequency is 394kHz. Signed-off-by: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9 --- M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/47225/1 diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index bb4db53..1cb0b52 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -39,6 +39,12 @@ }, .i2c[3] = { .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 153, + .scl_hcnt = 75, + .sda_hold = 36, + }, }, .i2c[5] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/47225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1ef95bb39d71fbb113120a0ec88305bc23e7ab9 Gerrit-Change-Number: 47225 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: storage.c: remove unneeded #if CONFIG()
by Thomas Heijligen (Code Review) 09 Nov '20

09 Nov '20

Thomas Heijligen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47248 ) Change subject: libpayload: storage.c: remove unneeded #if CONFIG() ...................................................................... libpayload: storage.c: remove unneeded #if CONFIG() Change-Id: I6e5679f66840105b3f9628071ac7aace9128107f Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M payloads/libpayload/drivers/storage/storage.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47248/1 diff --git a/payloads/libpayload/drivers/storage/storage.c b/payloads/libpayload/drivers/storage/storage.c index a3b31c5..4b585ba 100644 --- a/payloads/libpayload/drivers/storage/storage.c +++ b/payloads/libpayload/drivers/storage/storage.c @@ -28,9 +28,7 @@ #include <libpayload.h> #include <pci/pci.h> -#if CONFIG(LP_STORAGE_AHCI) -# include <storage/ahci.h> -#endif +#include <storage/ahci.h> #include <storage/storage.h> static storage_dev_t **devices = NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/47248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e5679f66840105b3f9628071ac7aace9128107f Gerrit-Change-Number: 47248 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Subrata Banik (Code Review) 09 Nov '20

09 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 09 Nov 2020 05:50:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mediatek/mt8192: memlayout: Add DRAM DMA region
by Roger Lu (Code Review) 09 Nov '20

09 Nov '20

Hello Roger Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47352 to review the following change. Change subject: mediatek/mt8192: memlayout: Add DRAM DMA region ...................................................................... mediatek/mt8192: memlayout: Add DRAM DMA region SPM DMA hardware requires a non-cacheable buffer to load SPM firmware. TEST=verified with SPM WIP patch. SPM PC stays at 0x3f4 after SPM firmware is loaded. Change-Id: Ic6521f3d14044c01ddd4da8c04126621f18ad32a --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/include/soc/memlayout.ld M src/soc/mediatek/mt8192/mmu_operations.c 3 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/47352/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 257b636..c7d26f9 100755 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -31,7 +31,7 @@ romstage-y += emi.c romstage-y += flash_controller.c romstage-y += ../common/gpio.c gpio.c -romstage-y += ../common/mmu_operations.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += memory.c dramc_param.c ../common/memory_test.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld index 891b782..a1c1be6 100644 --- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld @@ -14,6 +14,11 @@ #define DRAM_INIT_CODE(addr, size) \ REGION(dram_init_code, addr, size, 4) +#define DRAM_DMA(addr, size) \ + REGION(dram_dma, addr, size, 4K) \ + _ = ASSERT(size % 4K == 0, \ + "DRAM DMA buffer should be multiple of smallest page size (4K)!"); + SECTIONS { SRAM_START(0x00100000) @@ -37,8 +42,9 @@ SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) - POSTRAM_CBFS_CACHE(0x40000000, 2M) - RAMSTAGE(0x40200000, 512K) + DRAM_DMA(0x40000000, 1M) + POSTRAM_CBFS_CACHE(0x40100000, 2M) + RAMSTAGE(0x40300000, 512K) BL31(0x54600000, 0x60000) } diff --git a/src/soc/mediatek/mt8192/mmu_operations.c b/src/soc/mediatek/mt8192/mmu_operations.c index fb3620e..e3bc622 100644 --- a/src/soc/mediatek/mt8192/mmu_operations.c +++ b/src/soc/mediatek/mt8192/mmu_operations.c @@ -3,6 +3,7 @@ #include <device/mmio.h> #include <soc/mcucfg.h> #include <soc/mmu_operations.h> +#include <soc/symbols.h> DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_EN, 9) DEFINE_BIT(MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 8) @@ -28,3 +29,10 @@ MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6521f3d14044c01ddd4da8c04126621f18ad32a Gerrit-Change-Number: 47352 Gerrit-PatchSet: 1 Gerrit-Owner: Roger Lu <roger.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Roger Lu <roger.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/puff/var/dooly: Set default I2C0 frequency
by Tony Huang (Code Review) 09 Nov '20

09 Nov '20

Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47161 ) Change subject: mb/google/puff/var/dooly: Set default I2C0 frequency ...................................................................... mb/google/puff/var/dooly: Set default I2C0 frequency This setting copy from puff reference board and should measure whole system after EVT build. BUG=b:155261464 BRANCH=puff TEST=emerge-puff coreboot and check system speaker has sound output. Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/dooly/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/47161/1 diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index ee91dd3..f4b6d63 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -125,8 +125,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 0, - .fall_time_ns = 0, + .rise_time_ns = 60, + .fall_time_ns = 60, }, .i2c[2] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/c/coreboot/+/47161 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd5c3276e9306e81ea766d14ed1415a68dedc2ad Gerrit-Change-Number: 47161 Gerrit-PatchSet: 1 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/skx: Reorder soc_util.c
by Marc Jones (Code Review) 09 Nov '20

09 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47171 ) Change subject: soc/intel/xeon_sp/skx: Reorder soc_util.c ...................................................................... soc/intel/xeon_sp/skx: Reorder soc_util.c Reorder soc_util.c to match cpx version in preparation for more de-duplication. Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/soc_util.c 1 file changed, 98 insertions(+), 100 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/47171/1 diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 5a2b3c6..3faaed0 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -45,18 +45,42 @@ * +-------------------------+ */ -static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) +const struct SystemMemoryMapHob *get_system_memory_map(void) { size_t hob_size; - const IIO_UDS *hob; + const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob *memmap_addr; + + memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + assert(memmap_addr != NULL && hob_size != 0); + + return memmap_addr; +} + +uint8_t get_iiostack_info(struct iiostack_resource *info) +{ + size_t hob_size; const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob; - assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); - - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); assert(hob != NULL && hob_size != 0); - return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; + // copy IIO Stack info from FSP HOB + info->no_of_stacks = 0; + for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { + for (int x = 0; x < MAX_IIO_STACK; ++x) { + const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; + // TODO: do we have situation with only bux 0 and one stack? + if (ri->BusBase >= ri->BusLimit) + continue; + assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); + memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); + } + } + + return hob->PlatformData.Pci64BitResourceAllocation; } /* return 1 if command timed out else 0 */ @@ -80,26 +104,6 @@ } /* return 1 if command timed out else 0 */ -static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, - uint32_t pcode_init_mask, uint32_t val) -{ - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - - uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); - reg &= (uint32_t) ~rst_cpl_mask; - reg |= rst_cpl_mask; - reg |= val; - - /* update BIOS RESET completion bit */ - pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); - - /* wait for PCU ack */ - return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, - pcode_init_mask); -} - -/* return 1 if command timed out else 0 */ static uint32_t write_bios_mailbox_cmd(pci_devfn_t dev, uint32_t command, uint32_t data) { /* verify bios is not in busy state */ @@ -123,54 +127,38 @@ BIOS_MB_RUN_BUSY_MASK, 0); } -void config_reset_cpl3_csrs(void) +static uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) { - uint32_t data, plat_info, max_min_turbo_limit_ratio; + size_t hob_size; + const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { - uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); - /* configure PCU_CR0_FUN csrs */ - pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); - data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); - data |= P_STATE_LIMITS_LOCK; - pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); - plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); - dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); - max_min_turbo_limit_ratio = - (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> - MAX_NON_TURBO_LIM_RATIO_SHIFT; - printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", - plat_info, max_min_turbo_limit_ratio); + return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; +} - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); +/* return 1 if command timed out else 0 */ +static int set_bios_reset_cpl_for_package(uint32_t socket, uint32_t rst_cpl_mask, + uint32_t pcode_init_mask, uint32_t val) +{ + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); - data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL); - /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ - data &= 0x0fffffff; - data |= SAPMCTL_LOCK_MASK; - pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + uint32_t reg = pci_mmio_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); + reg &= (uint32_t) ~rst_cpl_mask; + reg |= rst_cpl_mask; + reg |= val; - /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); + /* update BIOS RESET completion bit */ + pci_mmio_write_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG, reg); - data = PCIE_IN_PKGCSTATE_L1_MASK; - pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); - - data = KTI_IN_PKGCSTATE_L1_MASK; - pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); - - data = PROCHOT_RATIO; - printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); - pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); - dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); - - data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); - data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; - pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); - } + /* wait for PCU ack */ + return wait_for_bios_cmd_cpl(dev, PCU_CR1_BIOS_RESET_CPL_REG, pcode_init_mask, + pcode_init_mask); } static void set_bios_init_completion_for_package(uint32_t socket) @@ -229,43 +217,54 @@ set_bios_init_completion_for_package(sbsp_socket_id); } -uint8_t get_iiostack_info(struct iiostack_resource *info) +void config_reset_cpl3_csrs(void) { - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob; + uint32_t data, plat_info, max_min_turbo_limit_ratio; - hob = fsp_find_extension_hob_by_guid( - fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); + for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { + uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); - // copy IIO Stack info from FSP HOB - info->no_of_stacks = 0; - for (int s = 0; s < hob->PlatformData.numofIIO; ++s) { - for (int x = 0; x < MAX_IIO_STACK; ++x) { - const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - // TODO: do we have situation with only bux 0 and one stack? - if (ri->BusBase >= ri->BusLimit) - continue; - assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); - memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); - } + /* configure PCU_CR0_FUN csrs */ + pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); + data = pci_mmio_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); + data |= P_STATE_LIMITS_LOCK; + pci_mmio_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); + + plat_info = pci_mmio_read_config32(cr0_dev, PCU_CR0_PLATFORM_INFO); + dump_csr64("", cr0_dev, PCU_CR0_PLATFORM_INFO); + max_min_turbo_limit_ratio = + (plat_info & MAX_NON_TURBO_LIM_RATIO_MASK) >> + MAX_NON_TURBO_LIM_RATIO_SHIFT; + printk(BIOS_SPEW, "plat_info: 0x%x, max_min_turbo_limit_ratio: 0x%x\n", + plat_info, max_min_turbo_limit_ratio); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + + data = pci_mmio_read_config32(cr1_dev, PCU_CR1_SAPMCTL); + /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ + data &= 0x0fffffff; + data |= SAPMCTL_LOCK_MASK; + pci_mmio_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); + + /* configure PCU_CR1_FUN csrs */ + pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); + + data = PCIE_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); + + data = KTI_IN_PKGCSTATE_L1_MASK; + pci_mmio_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK2, data); + + data = PROCHOT_RATIO; + printk(BIOS_SPEW, "PCU_CR2_PROCHOT_RESPONSE_RATIO_REG data: 0x%x\n", data); + pci_mmio_write_config32(cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG, data); + dump_csr("", cr2_dev, PCU_CR2_PROCHOT_RESPONSE_RATIO_REG); + + data = pci_mmio_read_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL); + data |= UNOCRE_PLIMIT_OVERRIDE_SHIFT; + pci_mmio_write_config32(cr2_dev, PCU_CR2_DYNAMIC_PERF_POWER_CTL, data); } - - return hob->PlatformData.Pci64BitResourceAllocation; -} - -#if ENV_RAMSTAGE -const struct SystemMemoryMapHob *get_system_memory_map(void) -{ - size_t hob_size; - const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; - const struct SystemMemoryMapHob *memmap_addr; - - memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); - assert(memmap_addr != NULL && hob_size != 0); - - return memmap_addr; } /* @@ -296,4 +295,3 @@ else return -1; } -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab343e903e2478709fe91739c9ca77f587286df7 Gerrit-Change-Number: 47171 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020