coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Michael Niewöhner (Code Review) 07 Nov '20

07 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > > intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off […] oh my.... sorry! my fault :/ -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 23:06:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off > kontron/bsl6/devicetree.cb : not defined -> dev is currently on - will be off > intel/saddlebrook/devicetree.cb : off -> dev is currently on - will be off This change is for the *PCH* thermal subsystem - `pci 14.2`, not the *SA* thermal subsystem - `pci 04.0`. Sorry if there was any confusion. > protectli/vault_kbl/devicetree.cb : off -> dev is currently on - will be off Behaviour will be preserved as the UPD was being disabled in protectli/vault_kbl/ramstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 22:59:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: sc7180: Correct mmu configuration for AOP SRAM regions
by mturney mturney (Code Review) 06 Nov '20

06 Nov '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47261 ) Change subject: sc7180: Correct mmu configuration for AOP SRAM regions ...................................................................... sc7180: Correct mmu configuration for AOP SRAM regions Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c --- M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7180/mmu.c 3 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/47261/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 207bc43..b498606 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -14,7 +14,14 @@ DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) -DECLARE_REGION(aop) +DECLARE_REGION(aop_code_ram) +DECLARE_REGION(aop_dec) +DECLARE_REGION(aop_qtmr_ac) +DECLARE_REGION(aop_f0_qtmr_v1_f0) +DECLARE_REGION(aop_f1_qtmr_v1_f1) +DECLARE_REGION(aop_vmidmt) +DECLARE_REGION(aop_rscc) +DECLARE_REGION(aop_data_ram) DECLARE_REGION(modem_id) #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 65e50d1..600ef63 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -18,7 +18,14 @@ SECTIONS { AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) + REGION(aop_code_ram, 0x0B000000, 0x80000, 4096) + REGION(aop_dec, 0x0B080000, 0x2000, 4096) + REGION(aop_qtmr_ac, 0x0B090000, 0x1000, 4096) + REGION(aop_f0_qtmr_v1_f0, 0x0B0A0000, 0x1000, 4096) + REGION(aop_f1_qtmr_v1_f1, 0x0B0B0000, 0x1000, 4096) + REGION(aop_vmidmt, 0x0B0C0000, 0x1000, 4096) + REGION(aop_rscc, 0x0B0D0000, 0x10000, 4096) + REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096) AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index b33baca..c889a60 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -22,5 +22,12 @@ void soc_mmu_dram_config_post_dram_init(void) { - mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); + mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); + mmu_config_range((void *)_aop_dec, REGION_SIZE(aop_dec), DEV_MEM); + mmu_config_range((void *)_aop_qtmr_ac, REGION_SIZE(aop_qtmr_ac), DEV_MEM); + mmu_config_range((void *)_aop_f0_qtmr_v1_f0, REGION_SIZE(aop_f0_qtmr_v1_f0), DEV_MEM); + mmu_config_range((void *)_aop_f1_qtmr_v1_f1, REGION_SIZE(aop_f1_qtmr_v1_f1), DEV_MEM); + mmu_config_range((void *)_aop_vmidmt, REGION_SIZE(aop_vmidmt), DEV_MEM); + mmu_config_range((void *)_aop_rscc, REGION_SIZE(aop_rscc), DEV_MEM); + mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c Gerrit-Change-Number: 47261 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Michael Niewöhner (Code Review) 06 Nov '20

06 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > Yes, but all boards are presently declaring this device. intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off kontron/bsl6/devicetree.cb : not defined -> dev is currently on - will be off intel/saddlebrook/devicetree.cb : off -> dev is currently on - will be off protectli/vault_kbl/devicetree.cb : off -> dev is currently on - will be off -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 20:54:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Marc Jones (Code Review) 06 Nov '20

06 Nov '20

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 4: Do we need to put VPD into the console code? There is already an override for get_console_loglevel() for mainboards to set the level. It seems it could be set via cmos, vpd, gpio, bmc, cbfs file, or other mechanisms. A standard would be good, but putting everything in VPD doesn't seem right, either. These these types of optional user settings don't really need RO/RW. It isn't like a serial # or something that needs protection. -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 20:40:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > no, it is not. […] Yes, but all boards are presently declaring this device. -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 20:07:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/picasso: add Raven1 GPU PCI ID
by Felix Held (Code Review) 06 Nov '20

06 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47250 ) Change subject: soc/amd/picasso: add Raven1 GPU PCI ID ...................................................................... soc/amd/picasso: add Raven1 GPU PCI ID Change-Id: Id4460eb596b080dec1a63a20869182170c3388af Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/include/soc/cpu.h 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/47250/1 diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h index e79dd87..cbc3929 100644 --- a/src/soc/amd/picasso/include/soc/cpu.h +++ b/src/soc/amd/picasso/include/soc/cpu.h @@ -12,6 +12,8 @@ #define RAVEN2_A0_CPUID 0x00820f00 #define RAVEN2_A1_CPUID 0x00820f01 +#define RAVEN1_VBIOS_VID_DID 0x100215dd +#define RAVEN1_VBIOS_REV 0x81 #define PICASSO_VBIOS_VID_DID 0x100215d8 #define PICASSO_VBIOS_REV 0xc1 #define RAVEN2_VBIOS_VID_DID 0x100215dd /* VID/DID in RV2 VBIOS header */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4460eb596b080dec1a63a20869182170c3388af Gerrit-Change-Number: 47250 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/cpu: add Raven1 CPUID to CPU table
by Felix Held (Code Review) 06 Nov '20

06 Nov '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47249 ) Change subject: soc/amd/picasso/cpu: add Raven1 CPUID to CPU table ...................................................................... soc/amd/picasso/cpu: add Raven1 CPUID to CPU table The RV1 CPUID is already in the cpu.h file, but was still missing from the CPU table in cpu.c. Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/picasso/cpu.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47249/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index 4d6e98d..5979fc6 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -128,6 +128,7 @@ }; static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_AMD, RAVEN1_B0_CPUID}, { X86_VENDOR_AMD, PICASSO_B0_CPUID }, { X86_VENDOR_AMD, PICASSO_B1_CPUID }, { X86_VENDOR_AMD, RAVEN2_A0_CPUID }, -- To view, visit https://review.coreboot.org/c/coreboot/+/47249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089 Gerrit-Change-Number: 47249 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Tim Wawrzynczak (Code Review) 06 Nov '20

06 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 ) Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden : register "options.tsr[0].desc" = ""Memory"" : register "options.tsr[1].desc" = ""Ambient"" : register "options.tsr[2].desc" = ""Charger"" : register "options.tsr[3].desc" = ""5V regulator"" > Tim, do you have any suggestion here ? Please, let's know. […] They are two separate devices so it's kind of tricky to share registers between them -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 19:24:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board
by Lucas Chen (Code Review) 06 Nov '20

06 Nov '20

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47011 ) Change subject: zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board ...................................................................... zork/var/ezkinil: Adjust USB2 phy si fine tune on DVT Board Adjust USB2 phy si setting fine tune on DVT for Ezkinil. BRANCH=zork BUG=b:156315391 TEST=Measuring scope timing and test usb detection Signed-off-by: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d --- M src/mainboard/google/zork/variants/ezkinil/overridetree.cb 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/47011/1 diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 5ef2f0a..a15a33b 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -22,6 +22,32 @@ # End : OPN Performance Configuration + #USB 2.0 strength + register "usb_2_port_tune_params[2]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb_2_port_tune_params[3]" = "{ + .com_pds_tune = 0x05, + .sq_rx_tune = 0x3, + .tx_fsls_tune = 0x3, + .tx_pre_emp_amp_tune = 0x03, + .tx_pre_emp_pulse_tune = 0x0, + .tx_rise_tune = 0x1, + .rx_vref_tune = 0x9, + .tx_hsxv_tune = 0x3, + .tx_res_tune = 0x01, + }" + + register "usb3_port_force_gen1" = "{ .ports.xhci0_port0 = 1, .ports.xhci0_port1 = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/47011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id537b6e9a17f47481b6aedcea0c6a8474d993b6d Gerrit-Change-Number: 47011 Gerrit-PatchSet: 1 Gerrit-Owner: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020