Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 )
Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled;
> > intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off […]
oh my.... sorry! my fault :/
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 )
Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled;
> intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off
> kontron/bsl6/devicetree.cb : not defined -> dev is currently on - will be off
> intel/saddlebrook/devicetree.cb : off -> dev is currently on - will be off
This change is for the *PCH* thermal subsystem - `pci 14.2`, not the *SA* thermal subsystem - `pci 04.0`. Sorry if there was any confusion.
> protectli/vault_kbl/devicetree.cb : off -> dev is currently on - will be off
Behaviour will be preserved as the UPD was being disabled in protectli/vault_kbl/ramstage.c
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 )
Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled;
> Yes, but all boards are presently declaring this device.
intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off
kontron/bsl6/devicetree.cb : not defined -> dev is currently on - will be off
intel/saddlebrook/devicetree.cb : off -> dev is currently on - will be off
protectli/vault_kbl/devicetree.cb : off -> dev is currently on - will be off
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Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 )
Change subject: console: Allow VPD to disable an otherwise enabled coreboot console
......................................................................
Patch Set 4:
Do we need to put VPD into the console code? There is already an override for get_console_loglevel() for mainboards to set the level. It seems it could be set via cmos, vpd, gpio, bmc, cbfs file, or other mechanisms.
A standard would be good, but putting everything in VPD doesn't seem right, either. These these types of optional user settings don't really need RO/RW. It isn't like a serial # or something that needs protection.
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 )
Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
File src/soc/intel/skylake/chip.c:
https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip…
PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled;
> no, it is not. […]
Yes, but all boards are presently declaring this device.
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47249 )
Change subject: soc/amd/picasso/cpu: add Raven1 CPUID to CPU table
......................................................................
soc/amd/picasso/cpu: add Raven1 CPUID to CPU table
The RV1 CPUID is already in the cpu.h file, but was still missing from
the CPU table in cpu.c.
Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/soc/amd/picasso/cpu.c
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47249/1
diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c
index 4d6e98d..5979fc6 100644
--- a/src/soc/amd/picasso/cpu.c
+++ b/src/soc/amd/picasso/cpu.c
@@ -128,6 +128,7 @@
};
static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_AMD, RAVEN1_B0_CPUID},
{ X86_VENDOR_AMD, PICASSO_B0_CPUID },
{ X86_VENDOR_AMD, PICASSO_B1_CPUID },
{ X86_VENDOR_AMD, RAVEN2_A0_CPUID },
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 )
Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded…
File src/mainboard/google/dedede/variants/drawcia/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded…
PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden
: register "options.tsr[0].desc" = ""Memory""
: register "options.tsr[1].desc" = ""Ambient""
: register "options.tsr[2].desc" = ""Charger""
: register "options.tsr[3].desc" = ""5V regulator""
> Tim, do you have any suggestion here ? Please, let's know. […]
They are two separate devices so it's kind of tricky to share registers between them
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