coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers
by V Sowmya (Code Review) 07 Nov '20

07 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47288 ) Change subject: mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers ...................................................................... mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers for ADLRVP. BUG=:b:170607415 TEST=Built and booted on ADLRVP. Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47288/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index ea75d5d..44c324b 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -173,17 +173,17 @@ device pci 04.0 on end # DPTF device pci 05.0 on end # IPU device pci 06.0 on end # PEG60 - device pci 07.0 off end # TBT_PCIe0 - device pci 07.1 off end # TBT_PCIe1 - device pci 07.2 off end # TBT_PCIe2 - device pci 07.3 off end # TBT_PCIe3 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe1 + device pci 07.2 on end # TBT_PCIe2 + device pci 07.3 on end # TBT_PCIe3 device pci 08.0 off end # GNA device pci 09.0 off end # NPK device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on end # USB xHCI - device pci 0d.1 off end # USB xDCI (OTG) - device pci 0d.2 off end # TBT DMA0 - device pci 0d.3 off end # TBT DMA1 + device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.2 on end # TBT DMA0 + device pci 0d.3 on end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/47288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33 Gerrit-Change-Number: 47288 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Configure the HPD GPIO's
by V Sowmya (Code Review) 07 Nov '20

07 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47290 ) Change subject: mb/intel/adlrvp: Configure the HPD GPIO's ...................................................................... mb/intel/adlrvp: Configure the HPD GPIO's This patch configures the HPD1 and HPD2 GPIO's. BUG=:b:170607415 TEST=Built and booted adlrvp. Verified the hotplug functionality is working. Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47290/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index e142e88..cda183d 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -277,6 +277,10 @@ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + /* HPD_1 (A19) and HPD_2 (A20) pins */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* IMGCLKOUT */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/47290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74 Gerrit-Change-Number: 47290 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 07 Nov '20

07 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > oh my.... […] Don't worry about it. -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 07 Nov 2020 00:18:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: vc/intel/FSP2_0/CPX-SP: update to ww34 release and accomodate waterma...
by Jonathan Zhang (Code Review) 07 Nov '20

07 Nov '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46640 ) Change subject: vc/intel/FSP2_0/CPX-SP: update to ww34 release and accomodate watermark patch ...................................................................... vc/intel/FSP2_0/CPX-SP: update to ww34 release and accomodate watermark patch Intel CPX-SP FSP ww34 release annotates default values for FSP-M UPD variables. FSPM MemRefreshWatermark option support is present in FB's CPX-SP FSP binary, but not in Intel's CPX-SP FSP binary. In FB's CPX-SP FSP binary, this option takes the space of UnusedUpdSpace0[0]. For DeltaLake mainboard, if corresponding VPD variable is set, use it to control the behavior. Such control is effective when FB's CPX-SP FSP binary is used. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d --- M src/mainboard/ocp/deltalake/romstage.c M src/mainboard/ocp/deltalake/vpd.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h 3 files changed, 195 insertions(+), 158 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46640/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index 71a26c8..f5bdcb0 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -59,6 +59,26 @@ "DciEn to %d\n", FSP_DCI, FSP_DCI_DEFAULT); mupd->FspmConfig.PchDciEn = FSP_DCI_DEFAULT; } + + /* + * UnusedUpdSpace0[0] is reserved for Memory Refresh Watermark. + * Following code is effective when MemRefreshWaterMark patch is added to FSP. + */ + if (vpd_gets(FSPM_MEMREFRESHWATERMARK, val_str, VPD_LEN, VPD_RW_THEN_RO)) { + val = (uint8_t)atol(val_str); + if (val > 2) { + printk(BIOS_DEBUG, "Invalid MemRefreshWatermark value from VPD: " + "%d\n", val); + val = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } + printk(BIOS_DEBUG, "Setting MemRefreshWatermark %d from VPD\n", val); + mupd->FspmConfig.UnusedUpdSpace0[0] = val; + } else { + printk(BIOS_INFO, "Not able to get VPD %s, default set " + "MemRefreshWatermark to %d\n", FSPM_MEMREFRESHWATERMARK, + FSPM_MEMREFRESHWATERMARK_DEFAULT); + mupd->FspmConfig.UnusedUpdSpace0[0] = FSPM_MEMREFRESHWATERMARK_DEFAULT; + } } /* Update bifurcation settings according to different Configs */ diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index ae2099d..16140c7 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -32,4 +32,8 @@ #define FSP_DCI "fsp_dci_enable" /* 1 or 0: enable or disable DCI */ #define FSP_DCI_DEFAULT 0 /* Default value when the VPD variable is not found */ +/* FSPM MemRefreshWatermark: 0:Auto, 1: high(default), 2: low */ +#define FSPM_MEMREFRESHWATERMARK "fspm_mem_refresh_watermark" +#define FSPM_MEMREFRESHWATERMARK_DEFAULT 1 + #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index 37ff1bd..b4d4cad 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -151,223 +151,231 @@ UINT8 CustomerRevision[32]; /** Offset 0x0060 - Bus Ratio - Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO + Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO. + Default 0x1 **/ UINT8 BusRatio[8]; /** Offset 0x0068 - D2K Credit Config - Set the D2K Credit Config + Set the D2K Credit Config. 1: Min,2: Med (Default), 3: Max. 1:Min, 2:Med, 3:Max **/ UINT8 D2KCreditConfig; /** Offset 0x0069 - Snoop Throttle Config - Set the Snoop Throttle Config - 0:DIS, 1:Min, 2:Med, 3:Max + Set the Snoop Throttle Config. 0: Disable(Default), 1: Min, 2: Med, 3: Max + 0:Disable, 1:Min, 2:Med, 3:Max **/ UINT8 SnoopThrottleConfig; /** Offset 0x006A - Snoop Throttle Config - Set the Snoop All Core Config - 0:DIS, 1:EN, 2:Auto + Set the Snoop All Core Config. 0: Disable(Default), 1: Enable, 2: Auto + 0:Disable, 1:Enable, 2:Auto **/ UINT8 SnoopAllCores; -/** Offset 0x006B - Legacy VGA Soc - Socket that claims the legacy VGA range +/** Offset 0x006B - Legacy VGA Socket + Socket that claims the legacy VGA range. Default: Socket 0 **/ UINT8 LegacyVgaSoc; /** Offset 0x006C - Legacy VGA Stack - Stack that claims the legacy VGA range + Stack that claims the legacy VGA range. Default: Stack 0 **/ UINT8 LegacyVgaStack; /** Offset 0x006D - Pcie P2P Performance Mode - Determine if to enable PCIe P2P Performance Mode + Enable: Enable PCIe P2P Performance Mode, Disable(Default): Disable PCIe + P2P Performance Mode $EN_DIS **/ UINT8 P2pRelaxedOrdering; /** Offset 0x006E - Debug Print Level - Set Debug Print Level + Debug Print Level Bitmask. 0: Disable, 1: Fatal, 2: Warning, 4: Summary, 8: Detail, + 0xF: All(Default) 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All **/ UINT8 DebugPrintLevel; /** Offset 0x006F - SNC - Enable or Disable SNC + Enable(Default) or Disable SNC $EN_DIS **/ UINT8 SncEn; /** Offset 0x0070 - UMA Clustering - Set UMA Clusters + Set number of enabled UMA Clusters. 0: Disable(Default), 2: Two Clusters, + 4: Four Clusters 0:Disable, 2:Two Clusters, 4:Four Clusters **/ UINT8 UmaClustering; /** Offset 0x0071 - IODC Mode - IODC Setup Option + IODC Mode. 0: Disable, 1: Auto(Default), 2: Push, 3: AllocFlow 4: NonAlloc, 5: WCILF 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF **/ UINT8 IoDcMode; /** Offset 0x0072 - Degrade Precedence - Setup Degrade Precedence + Degrade Precedence. 0: Topology(Default), 1: Feature 0:Topology, 1:Feature **/ UINT8 DegradePrecedence; /** Offset 0x0073 - Degrade 4 Socket Preference - Setup Degrade 4 Socket Preference + Degrade 4 Socket Preference. 0: Fully Connect(Default), 1: Dual Link Ring 0:Fully Connect, 1:Dual Link Ring **/ UINT8 Degrade4SPreference; /** Offset 0x0074 - Directory Mode - Enable or Disable Directory Mode + Enable(Default) or Disable Directory Mode $EN_DIS **/ UINT8 DirectoryModeEn; /** Offset 0x0075 - XPT Prefetch Enable - Enable or Disable XPT Prefetch + XPT Prefetch. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 XptPrefetchEn; /** Offset 0x0076 - KTI Prefetch Enable - Enable or Disable KTI Prefetch + Enable(Default) or Disable KTI Prefetch $EN_DIS **/ UINT8 KtiPrefetchEn; /** Offset 0x0077 - XPT Remote Prefetch Enable - Enable or Disable XPT Remote Prefetch Enable + Enable or Disable(Default) XPT Remote Prefetch $EN_DIS **/ UINT8 XptRemotePrefetchEn; /** Offset 0x0078 - KTI FPGA - Enable or Disable KTI FPGA - $EN_DIS + Enable or Disable KTI FPGA, Default: 0x1 (Enable) **/ UINT8 KtiFpgaEnable[8]; /** Offset 0x0080 - DDRT QoS Mode - Setup DDRT QoS + DDRT QoS. 0: Mode 0(Default), 1: Mode 1, 2: Mode 2 **/ UINT8 DdrtQosMode; /** Offset 0x0081 - KTI Link Speed Mode - Choose KTI Link Speed Mode + KTI Link Speed Mode. 0: Slow, 1: Full(Default) **/ UINT8 KtiLinkSpeedMode; /** Offset 0x0082 - KTI Link Speed - Setup KTI Link Speed + KTI Link Speed. 0: 128GT, 1: 144GT, 2: 160GT, 3: Max KTI Link Speed(Default), + 4: Frequency Per Link **/ UINT8 KtiLinkSpeed; /** Offset 0x0083 - KTI Link L0p - Enable or Disable KTI Link L0p + KTI Link L0p. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL0pEn; /** Offset 0x0084 - KTI Link L1 - Enable or Disable KTI Link L1 + KTI Link L1. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiLinkL1En; /** Offset 0x0085 - KTI Failover - Enable or Disable KTI Failover + KTI Failover. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 KtiFailoverEn; /** Offset 0x0086 - KTI LB Enable - Enable or Disable KTI LB + Enable or Disable(Default) KTI LB $EN_DIS **/ UINT8 KtiLbEn; /** Offset 0x0087 - KTI CRC Mode - Select KTI CRC Mode + KTI CRC Mode. 0: 16bit, 1: 32bit, 2: Auto(Default) 0:16bit, 1:32bit, 2:Auto **/ UINT8 KtiCrcMode; /** Offset 0x0088 - KTI CPU Socket Hotplug - Enable or Disable KTI CPU Socket Hotplug + Enable or Disable(Default) KTI CPU Socket Hotplug $EN_DIS **/ UINT8 KtiCpuSktHotPlugEn; /** Offset 0x0089 - KTI CPU Socket HotPlug Topology - Select KTI CPU Socket HotPlug Topology + KTI CPU Socket HotPlug Topology. 0: 4 Socket(Default), 1: 8 Socket 0:4Socket, 1:8Socket **/ UINT8 KtiCpuSktHotPlugTopology; /** Offset 0x008A - KTI SKU Mismatch Check - Enable or Disable KTI SKU Mismatch Check + Enable(Default) or Disable KTI SKU Mismatch Check $EN_DIS **/ UINT8 KtiSkuMismatchCheck; /** Offset 0x008B - IRQ Threshold - Select IRQ Threshold + IRQ Threshold. 0: Disable, 1: Auto(Default), 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 IrqThreshold; -/** Offset 0x008C - IRQ Threshold - Enable or Disable +/** Offset 0x008C - TOR threshold - Loctorem threshold normal + TOR threshold - Loctorem threshold normal. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremNorm; /** Offset 0x008D - TOR threshold - Loctorem threshold empty - Select TOR threshold - Loctorem threshold empty + TOR threshold - Loctorem threshold empty. 0: Disable, 1: Auto(Default), + 2: Low, 3: Medium, 4: High 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High **/ UINT8 TorThresLoctoremEmpty; /** Offset 0x008E - MBA BW Calibration - MBA BW Calibration setting + MBA BW Calibration setting. 0: Linear, 1: Biased, 2: Legacy, 3: Auto(Default) 0:Linear, 1:Biased, 2:Legacy, 3:Auto **/ UINT8 MbeBwCal; /** Offset 0x008F - TSC Sync in Sockets - Enable or Disable TSC Sync in Sockets + TSC Sync in Sockets. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 TscSyncEn; /** Offset 0x0090 - HA A to S directory optimization - Enable or Disable HA A to S directory optimization + HA A to S directory optimization. 0: Disable, 1: Enable, 2: Auto(Default) **/ UINT8 StaleAtoSOptEn; /** Offset 0x0091 - LLC Deadline Allocation - Enable or Disable LLC Deadline Allocation + Enable(Default) or Disable LLC Deadline Allocation $EN_DIS **/ UINT8 LLCDeadLineAlloc; /** Offset 0x0092 - Split Lock - Enable or Disable Split Lock + Split Lock. 0: Disable(Default), 1: Enable, 2: Auto **/ UINT8 SplitLock; /** Offset 0x0093 - MMCFG Base Address - Setup MMCFG Base Address - 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto + MMCFG Base Address. 0: 1GB, 1: 1.5GB, 2: 1.75GB, 3: 2GB, 4: 2.25GB, 5: 3GB, 6: + Auto(Default) + 0:1GB, 1:1.5GB, 2:1.75GB, 3:2GB, 4:2.25GB, 5:3GB, 6:Auto **/ UINT8 mmCfgBase; /** Offset 0x0094 - MMCFG Size - Select MMCFG Size - 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto + Select MMCFG Size. 0: 64MB, 1: 128MB, 2: 256MB, 3: 512MB, 4: 1GB, 5: 2GB, 6: + Auto(Default) + 0:64MB, 1:128MB, 2:256MB, 3:512MB, 4:1GB, 5:2GB, 6: Auto **/ UINT8 mmCfgSize; @@ -375,37 +383,44 @@ **/ UINT8 UnusedUpdSpace0[3]; +/* + * UnusedUpdSpace0[0] is reserved for following UPD variable: + * Offset 0x0095 - Usage type for Memory Refresh Watermark + * Select Memory Refresh Watermark, 0: Auto, 1: High(default), 2: Low + UINT8 MemRefreshWaterMark; + */ + /** Offset 0x0098 - MMIO High Base Address - MMIO High Base Address, a hex number for Bit[51:32] + MMIO High Base Address, a hex number for Bit[51:32]. Default: 0x6 (Gives 0x200) **/ UINT32 mmiohBase; /** Offset 0x009C - CPU Physical Address Limit - CPU Physical Address Limit + Enable(Default) or Disable CPU Physical Address Limit 0:Disable, 1:Enable **/ UINT8 CpuPaLimit; /** Offset 0x009D - High Gap - Enable or Disable High Gap + Enable or Disable(Default) High Gap $EN_DIS **/ UINT8 highGap; /** Offset 0x009E - MMIO High Size MMIO High Size, Number of 1GB contiguous regions to be assigned for MMIOH space - per CPU. Range 1-1024 + per CPU. Range 1-1024, Default: 3 **/ UINT16 mmiohSize; -/** Offset 0x00A0 - } TYPE:{Combo - Enable or Disable +/** Offset 0x00A0 - ISOC + Enable(Default) or Disable ISOC $EN_DIS **/ UINT8 isocEn; /** Offset 0x00A1 - DCA - Enable or Disable DCA + Enable or Disable(Default) DCA $EN_DIS **/ UINT8 dcaEn; @@ -414,289 +429,287 @@ **/ UINT8 UnusedUpdSpace1[2]; -/** Offset 0x00A4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A4 - BoardTypeBitmask + Board Type Bitmask. Default: 0x1 **/ UINT32 BoardTypeBitmask; -/** Offset 0x00A8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00A8 - AllLanesPtr + Pointer to array of ALL_LANES_EPARAM_LINK_INFO **/ UINT32 AllLanesPtr; -/** Offset 0x00AC - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00AC - PerLanePtr + Pointer to array of PER_LANE_EPARAM_LINK_INFO **/ UINT32 PerLanePtr; -/** Offset 0x00B0 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B0 - AllLanesSizeOfTable + Number of elements in AllLanesPtr array. **/ UINT32 AllLanesSizeOfTable; -/** Offset 0x00B4 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B4 - PerLaneSizeOfTable + Number of elements in PerLanePtr array. **/ UINT32 PerLaneSizeOfTable; -/** Offset 0x00B8 - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00B8 - WaitTimeForPSBP + Number of milliseconds to wait for remote CPUs to initialize. Default: 30 sec **/ UINT32 WaitTimeForPSBP; -/** Offset 0x00BC - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BC - IsKtiNvramDataReady + IsKtiNvramDataReady. Default: Disable $EN_DIS **/ UINT8 IsKtiNvramDataReady; -/** Offset 0x00BD - } TYPE:{Combo - Enable or Disable - $EN_DIS +/** Offset 0x00BD - BoardId + Board ID **/ UINT8 BoardId; -/** Offset 0x00BE - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BE - WaSerializationEn + Enable(Default) or Disable BIOS serialization WA $EN_DIS **/ UINT8 WaSerializationEn; -/** Offset 0x00BF - } TYPE:{Combo - Enable or Disable +/** Offset 0x00BF - KtiInEnableMktme + Enable(Default) or Disable MkTme status decides D2Kti feature state $EN_DIS **/ UINT8 KtiInEnableMktme; -/** Offset 0x00C0 - Usage type for Processor VmxEnable Function - Processor VmxEnable Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C0 - Processor VmxEnable Function + Enable(Default) or Disable Processor VmxEnable Function $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x00C1 - Usage type for Processor X2apic Function - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C1 - Processor X2apic Function + Enable(Default) or Disable Processor X2apic Function + $EN_DIS **/ UINT8 X2apic; -/** Offset 0x00C2 - Usage type for DDR frequency limit - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C2 - DDR frequency limit + Enable(Default) or Disable Processor X2apic Function **/ UINT8 DdrFreqLimit; -/** Offset 0x00C3 - Usage type for Memory Serial Debug Message Level - Processor X2apic Function, if enabled, the value is 0x01, if disabled, the value is 0x00 +/** Offset 0x00C3 - Memory Serial Debug Message Level + Enable(Default) or Disable Processor X2apic Function **/ UINT8 serialDebugMsgLvl; /** Offset 0x00C4 - IIO ConfigIOU0 ConfigIOU[MAX_SOCKET][0]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU0[8]; /** Offset 0x00CC - IIO ConfigIOU1 ConfigIOU[MAX_SOCKET][1]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU1[8]; /** Offset 0x00D4 - IIO ConfigIOU2 ConfigIOU[MAX_SOCKET][2]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU2[8]; /** Offset 0x00DC - IIO ConfigIOU3 ConfigIOU[MAX_SOCKET][3]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU3[8]; /** Offset 0x00E4 - IIO ConfigIOU4 ConfigIOU[MAX_SOCKET][4]: MAX_SOCKET=8, 0x00:x4x4x4x4, 0x01:x4x4xxx8, 0x02:xxx8x4x4, - 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO + 0x03:xxx8xxx8, 0x04:xxxxxx16, 0xFF:AUTO(Default) **/ UINT8 IioConfigIOU4[8]; -/** Offset 0x00EC - Usage type for IIO PCIE Config Table Ptr - IIO PCIE Config Table Ptr +/** Offset 0x00EC - IIO PCIE Config Table Ptr + Pointer to array of UPD_IIO_PCIE_PORT_CONFIG **/ UINT32 IioPcieConfigTablePtr; -/** Offset 0x00F0 - Usage type for IIO PCIE Config Table Number - IIO PCIE Config Table Number +/** Offset 0x00F0 - IIO PCIE Config Table Number + Number of elements in IioPcieConfigTablePtr array. **/ UINT32 IioPcieConfigTableNumber; -/** Offset 0x00F4 - Usage type for IIO PCIE Root Port Enable or Disable - IIO PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x00F4 - IIO PCIE Root Port Enable + Enable(Default) or Disable IIO PCH rootport **/ UINT8 IIOPcieRootPortEnable; -/** Offset 0x00F5 - Usage type for IIO DeEmphasis - IIO DeEmphasis +/** Offset 0x00F5 - IIO DeEmphasis + IIO DeEmphasis. Default: 0x1 **/ UINT8 DeEmphasis; -/** Offset 0x00F6 - Usage type for IIO PCIE Root Port link speed - IIO root port link speed +/** Offset 0x00F6 - IIO PCIe Root Port Link Speed + IIO PCIe Root Port Link Speed. 0: Auto(Default), 1: Gen1, 2: Gen2, 3: Gen3, 4: Gen4 + 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3, 4:Gen4 **/ UINT8 IIOPciePortLinkSpeed; -/** Offset 0x00F7 - Usage type for IIO PCIE Root Port Max Payload - IIO Root Port Max Payload +/** Offset 0x00F7 - IIO PCIe Root Port Max Payload + IIO PCIe Root Port Max Payload. 0: 128B, 1: 256B, 2: 512B, 7: Auto(Default) + 0:128B, 1: 256B, 2:512B, 7:Auto **/ UINT8 IIOPcieMaxPayload; -/** Offset 0x00F8 - Usage type for IIO DfxDnTxPreset - IIO DfxDnTxPreset +/** Offset 0x00F8 - IIO DfxDnTxPreset + IIO Downstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxDnTxPreset; -/** Offset 0x00F9 - Usage type for IIO DfxRxPreset - IIO DfxRxPreset +/** Offset 0x00F9 - IIO DfxRxPreset + IIO Downstream Reciever Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxRxPreset; -/** Offset 0x00FA - Usage type for IIO DfxUpTxPreset - IIO DfxUpTxPreset +/** Offset 0x00FA - IIO DfxUpTxPreset + IIO Upstream Transmitter Preset. Default: Auto(0xFF), otherwise preset 0-10 **/ UINT8 DfxUpTxPreset; -/** Offset 0x00FB - Usage type for IIO PcieCommonClock - IIO PcieCommonClock +/** Offset 0x00FB - IIO PCIe Common Clock + IIO PCIe Common Clock. 0: Disable, 1: Enable(Default), 2: Auto **/ UINT8 PcieCommonClock; -/** Offset 0x00FC - Usage type for IIO NtbPpd - IIO NtbPpd +/** Offset 0x00FC - IIO Non-Transparent Port Definition + IIO Non-Transparent Port Definition. 0: Transparent(Default), 1: Non-Transparent + Bridge, 2: Non-Transparent Root Port **/ UINT8 NtbPpd; -/** Offset 0x00FD - Usage type for IIO NtbBarSizeOverride - IIO NtbBarSizeOverride +/** Offset 0x00FD - IIO Non-Transparent Bridge BAR Size Override + Enable or Disable(Default) IIO Non-Transparent Bridge BAR Size Override. **/ UINT8 NtbBarSizeOverride; -/** Offset 0x00FE - Usage type for IIO NtbSplitBar - IIO NtbSplitBar +/** Offset 0x00FE - IIO Non-Transparent Bridge Split BAR Mode + Enable or Disable(Default) IIO Non-Transparent Bridge Split BAR Mode **/ UINT8 NtbSplitBar; -/** Offset 0x00FF - Usage type for IIO NtbBarSizeImBar1 - IIO NtbBarSizeImBar1 +/** Offset 0x00FF - IIO NtbBarSizeImBar1 + IIO NtbBarSizeImBar1. Default: 0x16 **/ UINT8 NtbBarSizeImBar1; -/** Offset 0x0100 - Usage type for IIO NtbBarSizeImBar2 - IIO PNtbBarSizeImBar2 +/** Offset 0x0100 - IIO NtbBarSizeImBar2 + IIO PNtbBarSizeImBar2. Default: 0x16 **/ UINT8 NtbBarSizeImBar2; -/** Offset 0x0101 - Usage type for IIO NtbBarSizeImBar2_0 - IIO PNtbBarSizeImBar2_0 +/** Offset 0x0101 - IIO NtbBarSizeImBar2_0 + IIO PNtbBarSizeImBar2_0. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_0; -/** Offset 0x0102 - Usage type for IIO NtbBarSizeImBar2_1 - IIO NtbBarSizeImBar2_1 +/** Offset 0x0102 - IIO NtbBarSizeImBar2_1 + IIO NtbBarSizeImBar2_1. Default: 0x0C **/ UINT8 NtbBarSizeImBar2_1; -/** Offset 0x0103 - Usage type for IIO NtbBarSizeEmBarSZ1 - IIO NtbBarSizeEmBarSZ1 +/** Offset 0x0103 - IIO NtbBarSizeEmBarSZ1 + IIO NtbBarSizeEmBarSZ1. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ1; -/** Offset 0x0104 - Usage type for IIO NtbBarSizeEmBarSZ2 - IIO NtbBarSizeEmBarSZ2 +/** Offset 0x0104 - IIO NtbBarSizeEmBarSZ2 + IIO NtbBarSizeEmBarSZ2. . Default: 0x16 **/ UINT8 NtbBarSizeEmBarSZ2; -/** Offset 0x0105 - Usage type for IIO NtbBarSizeEmBarSZ2_0 - IIO NtbBarSizeEmBarSZ2_0 +/** Offset 0x0105 - IIO NtbBarSizeEmBarSZ2_0 + IIO NtbBarSizeEmBarSZ2_0. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_0; -/** Offset 0x0106 - Usage type for IIO NtbBarSizeEmBarSZ2_1 - IIO NtbBarSizeEmBarSZ2_1 +/** Offset 0x0106 - IIO NtbBarSizeEmBarSZ2_1 + IIO NtbBarSizeEmBarSZ2_1. . Default: 0x0C **/ UINT8 NtbBarSizeEmBarSZ2_1; -/** Offset 0x0107 - Usage type for IIO NtbXlinkCtlOverride - IIO NtbXlinkCtlOverride +/** Offset 0x0107 - IIO Non-Transparent Cross Link Override + IIO Non-Transparent Cross Link Override. 1:Operate as RP, 2:Operate as NTB-NTB (NT + Port), 3:Operate as NTB-> DSP (NTB EP)(Default) **/ UINT8 NtbXlinkCtlOverride; -/** Offset 0x0108 - Usage type for IIO VT-D Function - IIO VT-D Function, if supported, the value is 0x01, if not supported, the value is 0x00 +/** Offset 0x0108 - VT-d Support + Enable or Disable(Default) VT-d Support **/ UINT8 VtdSupport; -/** Offset 0x0109 - Usage type for IIO Pcie Port Hide +/** Offset 0x0109 - IIO PCIe Port Hide Hide or visible for IIO Pcie Port, 1 : Hide, 0 : Visible **/ UINT8 PEXPHIDE; -/** Offset 0x010A - Usage type for IIO Pcie Port Menu Hide - Hide or visible for IIO Pcie Port Menu, 1 : Hide, 0 : Visible +/** Offset 0x010A - IIO Pcie Port Menu Hide + Hide or visible for IIO PCIe Port Menu, 1 : Hide, 0 : Visible **/ UINT8 HidePEXPMenu; /** Offset 0x010B - PchSirqMode - Enable or Disable PchSirqMode + PchSirqMode. 0: Quiet Mode(Default) 1: Continuous Mode **/ UINT8 PchSirqMode; /** Offset 0x010C - PchAdrEn - Enable or Disable PchAdr + PchAdr 0:PLATFORM POR, 1:FORCE ENABLE(Default), 2:FORCE DISABLE **/ UINT8 PchAdrEn; /** Offset 0x010D - ThermalDeviceEnable - Enable or Disable ThermalDeviceEnable with PCI or ACPI mode + Thermal Device Mode. 0: Disable, 1: Enabled in PCI mode, 2: Enabled in ACPI + mode(Default) **/ UINT8 ThermalDeviceEnable; -/** Offset 0x010E - } TYPE:{Combo - Root port swapping based on device connection status : TRUE or FALSE +/** Offset 0x010E - PchPcieRootPortFunctionSwap + Root port swapping based on device connection status : TRUE(Default) or FALSE TRUE : 0x01, FALSE : 0x00 **/ UINT8 PchPcieRootPortFunctionSwap; /** Offset 0x010F - PCH PCIE PLL Ssc Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC - of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF + of 2.0%), Auto : 0xFE(Set to hardware default), Disable(Default) : 0xFF **/ UINT8 PchPciePllSsc; -/** Offset 0x0110 - Usage type for PCH PCIE Root Port Index +/** Offset 0x0110 - PCH PCIE Root Port Index Index assigned to every PCH PCIE Root Port **/ UINT8 PchPciePortIndex[20]; -/** Offset 0x0124 - Usage type for PCH PCIE Root Port Enable or Disable - 0-19: PCH rootport, if port is enabled, the value is 0x01, if the port is disabled, - the value is 0x00 +/** Offset 0x0124 - PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, if port is enabled(Default), the value is 0x01, if the port + is disabled, the value is 0x00 **/ UINT8 PchPcieForceEnable[20]; -/** Offset 0x0138 - Usage type for PCH PCIE Root Port Link Speed - 0-19: PCH rootport, 0x00 : Pcie Auto Speed, 0x01 : Pcie Gen1 Speed, 0x02 : Pcie - Gen2 Speed, 0x03 : Pcie Gen3 Speed +/** Offset 0x0138 - PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x00 : Pcie Auto Speed(Default), 0x01 : Pcie Gen1 Speed, 0x02 + : Pcie Gen2 Speed, 0x03 : Pcie Gen3 Speed **/ UINT8 PchPciePortLinkSpeed[20]; /** Offset 0x014C - PchDciEn - Enable or Disable Pch DciEn + Enable or Disable(Default) PCH DCI **/ UINT8 PchDciEn; @@ -706,7 +719,7 @@ UINT8 MeUmaEnable; /** Offset 0x014E - SerialIoUartDebugEnable - Enable SerialIo Uart debug library in FSP. + Enable(Default) or Disable SerialIo Uart debug library in FSP. 0:Disable, 1:Enable **/ UINT8 SerialIoUartDebugEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/46640 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57ad01f33b92bf61a6a2725dd1cdbbc99c02405d Gerrit-Change-Number: 46640 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

5 16

Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Michael Niewöhner (Code Review) 06 Nov '20

06 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > > intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off […] oh my.... sorry! my fault :/ -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 23:06:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off > kontron/bsl6/devicetree.cb : not defined -> dev is currently on - will be off > intel/saddlebrook/devicetree.cb : off -> dev is currently on - will be off This change is for the *PCH* thermal subsystem - `pci 14.2`, not the *SA* thermal subsystem - `pci 04.0`. Sorry if there was any confusion. > protectli/vault_kbl/devicetree.cb : off -> dev is currently on - will be off Behaviour will be preserved as the UPD was being disabled in protectli/vault_kbl/ramstage.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 22:59:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: sc7180: Correct mmu configuration for AOP SRAM regions
by mturney mturney (Code Review) 06 Nov '20

06 Nov '20

mturney mturney has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47261 ) Change subject: sc7180: Correct mmu configuration for AOP SRAM regions ...................................................................... sc7180: Correct mmu configuration for AOP SRAM regions Signed-off-by: T Michael Turney <mturney(a)codeaurora.org> Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c --- M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/memlayout.ld M src/soc/qualcomm/sc7180/mmu.c 3 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/47261/1 diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 207bc43..b498606 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -14,7 +14,14 @@ DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) -DECLARE_REGION(aop) +DECLARE_REGION(aop_code_ram) +DECLARE_REGION(aop_dec) +DECLARE_REGION(aop_qtmr_ac) +DECLARE_REGION(aop_f0_qtmr_v1_f0) +DECLARE_REGION(aop_f1_qtmr_v1_f1) +DECLARE_REGION(aop_vmidmt) +DECLARE_REGION(aop_rscc) +DECLARE_REGION(aop_data_ram) DECLARE_REGION(modem_id) #endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld index 65e50d1..600ef63 100644 --- a/src/soc/qualcomm/sc7180/memlayout.ld +++ b/src/soc/qualcomm/sc7180/memlayout.ld @@ -18,7 +18,14 @@ SECTIONS { AOPSRAM_START(0x0B000000) - REGION(aop, 0x0B000000, 0x100000, 4096) + REGION(aop_code_ram, 0x0B000000, 0x80000, 4096) + REGION(aop_dec, 0x0B080000, 0x2000, 4096) + REGION(aop_qtmr_ac, 0x0B090000, 0x1000, 4096) + REGION(aop_f0_qtmr_v1_f0, 0x0B0A0000, 0x1000, 4096) + REGION(aop_f1_qtmr_v1_f1, 0x0B0B0000, 0x1000, 4096) + REGION(aop_vmidmt, 0x0B0C0000, 0x1000, 4096) + REGION(aop_rscc, 0x0B0D0000, 0x10000, 4096) + REGION(aop_data_ram, 0x0B0E0000, 0x20000, 4096) AOPSRAM_END(0x0B100000) SSRAM_START(0x14680000) diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index b33baca..c889a60 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -22,5 +22,12 @@ void soc_mmu_dram_config_post_dram_init(void) { - mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); + mmu_config_range((void *)_aop_code_ram, REGION_SIZE(aop_code_ram), CACHED_RAM); + mmu_config_range((void *)_aop_dec, REGION_SIZE(aop_dec), DEV_MEM); + mmu_config_range((void *)_aop_qtmr_ac, REGION_SIZE(aop_qtmr_ac), DEV_MEM); + mmu_config_range((void *)_aop_f0_qtmr_v1_f0, REGION_SIZE(aop_f0_qtmr_v1_f0), DEV_MEM); + mmu_config_range((void *)_aop_f1_qtmr_v1_f1, REGION_SIZE(aop_f1_qtmr_v1_f1), DEV_MEM); + mmu_config_range((void *)_aop_vmidmt, REGION_SIZE(aop_vmidmt), DEV_MEM); + mmu_config_range((void *)_aop_rscc, REGION_SIZE(aop_rscc), DEV_MEM); + mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6611dc614c80063c7df057b59337417c8f56fd9c Gerrit-Change-Number: 47261 Gerrit-PatchSet: 1 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Michael Niewöhner (Code Review) 06 Nov '20

06 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > Yes, but all boards are presently declaring this device. intel/kblrvp/variants/rvp11/overridetree.cb : off -> dev is currently on - will be off kontron/bsl6/devicetree.cb : not defined -> dev is currently on - will be off intel/saddlebrook/devicetree.cb : off -> dev is currently on - will be off protectli/vault_kbl/devicetree.cb : off -> dev is currently on - will be off -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 20:54:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Marc Jones (Code Review) 06 Nov '20

06 Nov '20

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 4: Do we need to put VPD into the console code? There is already an override for get_console_loglevel() for mainboards to set the level. It seems it could be set via cmos, vpd, gpio, bmc, cbfs file, or other mechanisms. A standard would be good, but putting everything in VPD doesn't seem right, either. These these types of optional user settings don't really need RO/RW. It isn't like a serial # or something that needs protection. -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 20:40:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > no, it is not. […] Yes, but all boards are presently declaring this device. -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 20:07:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Benjamin Doron <benjamin.doron00(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2020