coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Furquan Shaikh (Code Review) 06 Nov '20

06 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Nov 2020 17:29:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/intelp2m: Update macros
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45008 ) Change subject: util/intelp2m: Update macros ...................................................................... Patch Set 3: > Patch Set 2: Code-Review+2 > > (3 comments) > > Agree, it would be nice to fix those. Please make another patch for that if you can I was planning on updating those after I was sure that these were the correct macros, but this is fine too. -- To view, visit https://review.coreboot.org/c/coreboot/+/45008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed Gerrit-Change-Number: 45008 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Nov 2020 17:24:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/47116/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47116/2//COMMIT_MSG@1 PS2, Line 1: Parent: 9c1c0096 (soc/intel/skylake: Enable thermal subsystem depending on devicetree) > Rebase on master? Done https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; > According to Kaby Lake Fsp.bsf [1], it's enabled by default. […] The current behaviour may have forced boards to enable the device to follow FSP, but this is preserving the current behaviour. -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 17:16:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 06 Nov '20

06 Nov '20

Hello Felix Singer, build bot (Jenkins), Michael Niewöhner, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47116 to look at the new patch set (#3). Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... soc/intel/skylake: Enable PCH thermal depending on devicetree Hook up PCH thermal subsystem configuration to devicetree. Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/mainboard/protectli/vault_kbl/ramstage.c M src/soc/intel/skylake/chip.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/47116/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp/skx: Fix MADT CPU indexes
by Marc Jones (Code Review) 06 Nov '20

06 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47277 ) Change subject: soc/intel/xeon_sp/skx: Fix MADT CPU indexes ...................................................................... soc/intel/xeon_sp/skx: Fix MADT CPU indexes The CPU index wasn't getting updated. Confirm MADT sets IOAPIC and CPU ID numbers. Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/skx/soc_acpi.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47277/1 diff --git a/src/soc/intel/xeon_sp/skx/soc_acpi.c b/src/soc/intel/xeon_sp/skx/soc_acpi.c index b392619..95563f5 100644 --- a/src/soc/intel/xeon_sp/skx/soc_acpi.c +++ b/src/soc/intel/xeon_sp/skx/soc_acpi.c @@ -182,7 +182,7 @@ unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current) { struct device *cpu; - int num_cpus = 0; + uint8_t num_cpus = 0; for (cpu = all_devices; cpu; cpu = cpu->next) { if ((cpu->path.type != DEVICE_PATH_APIC) || @@ -193,6 +193,7 @@ continue; current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, num_cpus, cpu->path.apic.apic_id); + num_cpus++; } return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/47277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72430cc48f4609ac408e723172ba1ed263cca8e3 Gerrit-Change-Number: 47277 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp: Move CPU helper functions
by Marc Jones (Code Review) 06 Nov '20

06 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47170 ) Change subject: soc/intel/xeon_sp: Move CPU helper functions ...................................................................... soc/intel/xeon_sp: Move CPU helper functions Continue Xeon-SP de-duplication. Move CPU helper functions from skx/ and cpx soc_util.c to common util.c. Functions only used by util.c are updated to be static. The following functions are moved: int get_threads_per_package(void); int get_platform_thread_count(void); const IIO_UDS *get_iio_uds(void); unsigned int soc_get_num_cpus(void); void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread); void xeonsp_init_cpu_config(void); Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/util.c 9 files changed, 147 insertions(+), 278 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/47170/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index acf030b..d33d1d0 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -11,8 +11,9 @@ #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/pci_devs.h> -#include <soc/soc_util.h> #include <soc/pm.h> +#include <soc/soc_util.h> +#include <soc/util.h> #include <string.h> acpi_cstate_t *soc_get_cstate_map(size_t *entries) diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 4e0de87..736207e 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -17,6 +17,7 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/soc_util.h> +#include <soc/util.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 5f4a6f9..8c454bb2 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -13,16 +13,6 @@ uint8_t get_iiostack_info(struct iiostack_resource *info); -void xeonsp_init_cpu_config(void); -const IIO_UDS *get_iio_uds(void); -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread); -/* Return socket count, as obtained from FSP HOB */ -unsigned int soc_get_num_cpus(void); - -int get_platform_thread_count(void); -int get_threads_per_package(void); const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index de6d852..149f2c0 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <commonlib/sort.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> @@ -9,22 +8,11 @@ #include <soc/cpu.h> #include <soc/pci_devs.h> #include <soc/soc_util.h> +#include <soc/util.h> #include <stdlib.h> #include <string.h> #include <timer.h> -int get_threads_per_package(void) -{ - unsigned int core_count, thread_count; - cpu_read_topology(&core_count, &thread_count); - return thread_count; -} - -int get_platform_thread_count(void) -{ - return soc_get_num_cpus() * get_threads_per_package(); -} - const struct SystemMemoryMapHob *get_system_memory_map(void) { size_t hob_size; @@ -41,125 +29,6 @@ return *memmap_addr; } -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread) -{ - if (package != NULL) - *package = (apicid >> (thread_bits + core_bits)); - if (core != NULL) - *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); - if (thread != NULL) - *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); -} - -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - register int ecx; - struct cpuid_result cpuid_regs; - - /* get max index of CPUID */ - cpuid_regs = cpuid(0); - assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ - - *thread_bits = *core_bits = 0; - ecx = 0; - while (1) { - cpuid_regs = cpuid_ext(0xb, ecx); - if (ecx == 0) { - *thread_bits = (cpuid_regs.eax & 0x1f); - } else { - *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; - break; - } - ecx++; - } -} - -const IIO_UDS *get_iio_uds(void) -{ - size_t hob_size; - const IIO_UDS *hob; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - return hob; -} - -unsigned int soc_get_num_cpus(void) -{ - /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ - return get_iio_uds()->SystemStatus.numCpus; -} - -void xeonsp_init_cpu_config(void) -{ - struct device *dev; - int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; - int num_apics = 0; - uint32_t core_bits, thread_bits; - unsigned int core_count, thread_count; - unsigned int num_sockets; - - /* - * sort APIC ids in asending order to identify apicid ranges for - * each numa domain - */ - for (dev = all_devices; dev; dev = dev->next) { - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - apic_ids[num_apics++] = dev->path.apic.apic_id; - } - if (num_apics > 1) - bubblesort(apic_ids, num_apics, NUM_ASCENDING); - - num_sockets = soc_get_num_cpus(); - cpu_read_topology(&core_count, &thread_count); - assert(num_apics == (num_sockets * thread_count)); - - /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ - int index = 0; - for (int id = 0; id < num_apics; ++id) { - int apic_id = apic_ids[id]; - if (apic_id & 0x1) { /* 2nd thread */ - apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; - } else { /* 1st thread */ - apic_ids_by_thread[index++] = apic_id; - } - } - - /* update apic_id, node_id in sorted order */ - num_apics = 0; - get_core_thread_bits(&core_bits, &thread_bits); - for (dev = all_devices; dev; dev = dev->next) { - uint8_t package; - - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; - get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, - &package, NULL, NULL); - dev->path.apic.node_id = package; - printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", - num_apics, dev->path.apic.apic_id, - dev->path.apic.apic_id, dev->path.apic.node_id); - - ++num_apics; - } -} - uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 51e2b69..73fc63d 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -10,5 +10,10 @@ void unlock_pam_regions(void); void get_stack_busnos(uint32_t *bus); msr_t read_msr_ppin(void); +int get_threads_per_package(void); +int get_platform_thread_count(void); +const IIO_UDS *get_iio_uds(void); +unsigned int soc_get_num_cpus(void); +void xeonsp_init_cpu_config(void); #endif diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index f6bf6ed..c48fb92 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -11,6 +11,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/soc_util.h> +#include <soc/util.h> #include "chip.h" diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index cce542a..fd0d4e2 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -13,20 +13,11 @@ uint8_t get_iiostack_info(struct iiostack_resource *info); -void xeonsp_init_cpu_config(void); - void config_reset_cpl3_csrs(void); -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits); -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread); - -int get_platform_thread_count(void); -int get_threads_per_package(void); const struct SystemMemoryMapHob *get_system_memory_map(void); void set_bios_init_completion(void); -unsigned int soc_get_num_cpus(void); int soc_get_stack_for_port(int port); #endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 3af6483..5a2b3c6 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <commonlib/sort.h> #include <console/console.h> #include <delay.h> #include <device/pci.h> @@ -230,64 +229,6 @@ set_bios_init_completion_for_package(sbsp_socket_id); } -void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - register int ecx; - struct cpuid_result cpuid_regs; - - /* get max index of CPUID */ - cpuid_regs = cpuid(0); - assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ - - *thread_bits = *core_bits = 0; - ecx = 0; - while (1) { - cpuid_regs = cpuid_ext(0xb, ecx); - if (ecx == 0) { - *thread_bits = (cpuid_regs.eax & 0x1f); - } else { - *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; - break; - } - ecx++; - } -} - -void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, - uint8_t *package, uint8_t *core, uint8_t *thread) -{ - if (package != NULL) - *package = (apicid >> (thread_bits + core_bits)); - if (core != NULL) - *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); - if (thread != NULL) - *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); -} - -unsigned int soc_get_num_cpus(void) -{ - size_t hob_size; - const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; - const IIO_UDS *hob; - - /* these fields are incorrect - need debugging */ - hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); - assert(hob != NULL && hob_size != 0); - return hob->SystemStatus.numCpus; -} - -int get_threads_per_package(void) -{ - unsigned int core_count, thread_count; - cpu_read_topology(&core_count, &thread_count); - return thread_count; -} - -int get_platform_thread_count(void) -{ - return soc_get_num_cpus() * get_threads_per_package(); -} - uint8_t get_iiostack_info(struct iiostack_resource *info) { size_t hob_size; @@ -327,73 +268,6 @@ return memmap_addr; } -void xeonsp_init_cpu_config(void) -{ - struct device *dev; - int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; - int num_apics = 0; - uint32_t core_bits, thread_bits; - unsigned int core_count, thread_count; - unsigned int num_cpus; - - /* sort APIC ids in asending order to identify apicid ranges for - each numa domain - */ - for (dev = all_devices; dev; dev = dev->next) { - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - apic_ids[num_apics++] = dev->path.apic.apic_id; - } - if (num_apics > 1) - bubblesort(apic_ids, num_apics, NUM_ASCENDING); - - num_cpus = soc_get_num_cpus(); - cpu_read_topology(&core_count, &thread_count); - assert(num_apics == (num_cpus * thread_count)); - - /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ - int index = 0; - for (int id = 0; id < num_apics; ++id) { - int apic_id = apic_ids[id]; - if (apic_id & 0x1) { /* 2nd thread */ - apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; - } else { /* 1st thread */ - apic_ids_by_thread[index++] = apic_id; - } - } - - /* update apic_id, node_id in sorted order */ - num_apics = 0; - get_core_thread_bits(&core_bits, &thread_bits); - for (dev = all_devices; dev; dev = dev->next) { - uint8_t package; - - if ((dev->path.type != DEVICE_PATH_APIC) || - (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { - continue; - } - if (!dev->enabled) - continue; - if (num_apics >= ARRAY_SIZE(apic_ids)) - break; - dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; - get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, - &package, NULL, NULL); - dev->path.apic.node_id = package; - printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", - num_apics, dev->path.apic.apic_id, - dev->path.apic.apic_id, dev->path.apic.node_id); - - ++num_apics; - } -} - /* * EX: SKX-SP * Ports Stack Stack(HOB) IioConfigIou diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 66b9ef1..feacca4 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> +#include <commonlib/sort.h> #include <console/console.h> +#include <device/device.h> #include <device/pci.h> +#include <intelblocks/cpulib.h> #include <soc/pci_devs.h> #include <soc/msr.h> #include <soc/util.h> @@ -85,3 +89,136 @@ wrmsr(MSR_PPIN_CTL, msr); return ppin; } + +int get_threads_per_package(void) +{ + unsigned int core_count, thread_count; + cpu_read_topology(&core_count, &thread_count); + return thread_count; +} + +int get_platform_thread_count(void) +{ + return soc_get_num_cpus() * get_threads_per_package(); +} + +const IIO_UDS *get_iio_uds(void) +{ + size_t hob_size; + const IIO_UDS *hob; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + + hob = fsp_find_extension_hob_by_guid(fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + return hob; +} + +unsigned int soc_get_num_cpus(void) +{ + /* The FSP IIO UDS HOB has field numCpus, it is actually socket count */ + return get_iio_uds()->SystemStatus.numCpus; +} + +#if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ +static void get_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) +{ + register int ecx; + struct cpuid_result cpuid_regs; + + /* get max index of CPUID */ + cpuid_regs = cpuid(0); + assert(cpuid_regs.eax >= 0xb); /* cpuid_regs.eax is max input value for cpuid */ + + *thread_bits = *core_bits = 0; + ecx = 0; + while (1) { + cpuid_regs = cpuid_ext(0xb, ecx); + if (ecx == 0) { + *thread_bits = (cpuid_regs.eax & 0x1f); + } else { + *core_bits = (cpuid_regs.eax & 0x1f) - *thread_bits; + break; + } + ecx++; + } +} + +static void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, + uint8_t *package, uint8_t *core, uint8_t *thread) +{ + if (package != NULL) + *package = (apicid >> (thread_bits + core_bits)); + if (core != NULL) + *core = (uint32_t)((apicid >> thread_bits) & ~((~0) << core_bits)); + if (thread != NULL) + *thread = (uint32_t)(apicid & ~((~0) << thread_bits)); +} + +void xeonsp_init_cpu_config(void) +{ + struct device *dev; + int apic_ids[CONFIG_MAX_CPUS] = {0}, apic_ids_by_thread[CONFIG_MAX_CPUS] = {0}; + int num_apics = 0; + uint32_t core_bits, thread_bits; + unsigned int core_count, thread_count; + unsigned int num_sockets; + + /* + * sort APIC ids in asending order to identify apicid ranges for + * each numa domain + */ + for (dev = all_devices; dev; dev = dev->next) { + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + apic_ids[num_apics++] = dev->path.apic.apic_id; + } + if (num_apics > 1) + bubblesort(apic_ids, num_apics, NUM_ASCENDING); + + num_sockets = soc_get_num_cpus(); + cpu_read_topology(&core_count, &thread_count); + assert(num_apics == (num_sockets * thread_count)); + + /* sort them by thread i.e., all cores with thread 0 and then thread 1 */ + int index = 0; + for (int id = 0; id < num_apics; ++id) { + int apic_id = apic_ids[id]; + if (apic_id & 0x1) { /* 2nd thread */ + apic_ids_by_thread[index + (num_apics/2) - 1] = apic_id; + } else { /* 1st thread */ + apic_ids_by_thread[index++] = apic_id; + } + } + + /* update apic_id, node_id in sorted order */ + num_apics = 0; + get_core_thread_bits(&core_bits, &thread_bits); + for (dev = all_devices; dev; dev = dev->next) { + uint8_t package; + + if ((dev->path.type != DEVICE_PATH_APIC) || + (dev->bus->dev->path.type != DEVICE_PATH_CPU_CLUSTER)) { + continue; + } + if (!dev->enabled) + continue; + if (num_apics >= ARRAY_SIZE(apic_ids)) + break; + dev->path.apic.apic_id = apic_ids_by_thread[num_apics]; + get_cpu_info_from_apicid(dev->path.apic.apic_id, core_bits, thread_bits, + &package, NULL, NULL); + dev->path.apic.node_id = package; + printk(BIOS_DEBUG, "CPU %d apic_id: 0x%x (%d), node_id: 0x%x\n", + num_apics, dev->path.apic.apic_id, + dev->path.apic.apic_id, dev->path.apic.node_id); + + ++num_apics; + } +} +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I118a451b9468459cf2c2194f31da1055e1435ebe Gerrit-Change-Number: 47170 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes
by Marc Jones (Code Review) 06 Nov '20

06 Nov '20

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47169 ) Change subject: soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes ...................................................................... soc/intel/xeon_sp/cpx: Reorder cpu.c .h includes Clean up the header includes. Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9 Signed-off-by: Marc Jones <marcjones(a)sysproconsulting.com> --- M src/soc/intel/xeon_sp/cpx/cpu.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/47169/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 5bde819..4e0de87 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -6,6 +6,7 @@ #include <console/console.h> #include <console/debug.h> #include <cpu/cpu.h> +#include <cpu/intel/common/common.h> #include <cpu/intel/microcode.h> #include <cpu/intel/turbo.h> #include <cpu/x86/lapic.h> @@ -16,8 +17,9 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/soc_util.h> + #include "chip.h" -#include <cpu/intel/common/common.h> + static const void *microcode_patch; -- To view, visit https://review.coreboot.org/c/coreboot/+/47169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f61d1a82b37bc0ed803967dc64decf18f44adc9 Gerrit-Change-Number: 47169 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: driver/usb/acpi: Add power resources for devices on USB ports
by Tim Wawrzynczak (Code Review) 06 Nov '20

06 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46713 ) Change subject: driver/usb/acpi: Add power resources for devices on USB ports ...................................................................... Patch Set 4: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/46713/4/src/drivers/usb/acpi/chip.h File src/drivers/usb/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/46713/4/src/drivers/usb/acpi/chip.… PS4, Line 62: }; Just for consistency's sake, I would have left the stop GPIO in here. -- To view, visit https://review.coreboot.org/c/coreboot/+/46713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Gerrit-Change-Number: 46713 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Fri, 06 Nov 2020 16:59:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Felix Singer (Code Review) 06 Nov '20

06 Nov '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 2: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/47116/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47116/2//COMMIT_MSG@1 PS2, Line 1: Parent: 9c1c0096 (soc/intel/skylake: Enable thermal subsystem depending on devicetree) Rebase on master? https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… File src/soc/intel/skylake/chip.c: https://review.coreboot.org/c/coreboot/+/47116/2/src/soc/intel/skylake/chip… PS2, Line 285: params->PchThermalDeviceEnable = dev && dev->enabled; According to Kaby Lake Fsp.bsf [1], it's enabled by default. Please check if all related mainboards are enabling it to keep the current behaviour. [1] https://github.com/intel/FSP/blob/master/KabylakeFspBinPkg/Fsp.bsf#L629 -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 13:21:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Fix generating DMAR IOAPIC
by Arthur Heymans (Code Review) 06 Nov '20

06 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47253 ) Change subject: soc/intel/xeon_sp: Fix generating DMAR IOAPIC ...................................................................... soc/intel/xeon_sp: Fix generating DMAR IOAPIC Using the stack number from the HOB for the lookup table results in wrong IOAPIC ID for PSTACK2. Translate the HOB stack number to a lookup table IDX. This way DMAR is aligned to the APIC ACPI table. This Fixes Linux complaining about not remapping Interrupts for IOAPIC 13. Change-Id: I9b6da491f8d5d1004864c9d704578c3b060809cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/47253/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index cf397f7..b44fc3a 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -180,6 +180,23 @@ return (atsr_size + pci_br_size); } +static int stack_to_ioapic_idx(const IIO_STACKS stack) +{ + switch (stack) { + case CSTACK: + return 0; + case PSTACK0: + return 1; + case PSTACK1: + return 2; + case PSTACK2: + return 3; + default: + printk(BIOS_ERR, "DMAR: unhandled IIO stack!\n"); + return -1; + } +} + static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { @@ -230,7 +247,7 @@ } // Add IOAPIC entry - enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + enum_id = IoApicID[(socket * MAX_IIO_STACK) + stack_to_ioapic_idx(stack)]; printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, -- To view, visit https://review.coreboot.org/c/coreboot/+/47253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6da491f8d5d1004864c9d704578c3b060809cb Gerrit-Change-Number: 47253 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020