coreboot-gerrit November 2020

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Change in coreboot[master]: amdfwtool: Use shell command to get depend file list
by Bao Zheng (Code Review) 06 Nov '20

06 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47237 to review the following change. Change subject: amdfwtool: Use shell command to get depend file list ...................................................................... amdfwtool: Use shell command to get depend file list The amdfwtool is not available at the beginning of the building. So it may have error if it is missing. Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Makefile.inc M src/southbridge/amd/pi/hudson/Makefile.inc 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/47237/1 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 5a88d0b..ffc1463 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -242,7 +242,8 @@ OPT_WHITELIST_FILE=$(call add_opt_prefix, $(PSP_WHITELIST_FILE), --whitelist) # Add all the files listed in the config file -DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index c608286..fb0a45b 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -148,7 +148,8 @@ OPT_PSP_USE_PSPSECUREOS=$(call strip_quotes, $(PSP_USE_PSPSECUREOS)) # Add all the files listed in the config file -DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE)) \ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index d5528aa..94c759e 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -121,7 +121,8 @@ OPT_SMUSCS_FILE=$(call add_opt_prefix, $(SMUSCS_FILE), --smuscs) # Add all the files listed in the config file -DEP_FILES=$(shell $(AMDFWTOOL) --config $(CONFIG_AMDFW_CONFIG_FILE) --depend) +POUND_SIGN=$(call strip_quotes, "\#") +DEP_FILES= $(patsubst %,$(FIRMWARE_LOCATION)/%, $(shell sed -e /^$(POUND_SIGN)/d -e /^FIRMWARE_LOCATION/d $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}' )) $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/47237 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452 Gerrit-Change-Number: 47237 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/picasso: Update coreboot UPD variable names to include units
by Bao Zheng (Code Review) 06 Nov '20

06 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46840 to review the following change. Change subject: soc/amd/picasso: Update coreboot UPD variable names to include units ...................................................................... soc/amd/picasso: Update coreboot UPD variable names to include units Use command below to change the variable globally. sed -i "s/\<variable\>/variable_u/g" `grep variable -rl ./ --exclude-dir=build` BUG=b:171334623 TEST=Build Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/berknip/overridetree.cb M src/mainboard/google/zork/variants/dalboz/overridetree.cb M src/mainboard/google/zork/variants/dirinboz/overridetree.cb M src/mainboard/google/zork/variants/ezkinil/overridetree.cb M src/mainboard/google/zork/variants/morphius/overridetree.cb M src/mainboard/google/zork/variants/trembyle/overridetree.cb M src/mainboard/google/zork/variants/vilboz/overridetree.cb M src/mainboard/google/zork/variants/woomax/overridetree.cb M src/soc/amd/picasso/chip.h M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/root_complex.c M src/vendorcode/amd/fsp/picasso/FspmUpd.h M util/mainboard/google/dalboz/template/overridetree.cb M util/mainboard/google/trembyle/template/overridetree.cb 16 files changed, 158 insertions(+), 158 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/46840/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index 58e25e6..00e77c0 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -15,22 +15,22 @@ # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_mS" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA - register "vddcr_soc_voltage_margin" = "0" #mV - register "vddcr_vdd_voltage_margin" = "0" #mV + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" + register "vddcr_soc_voltage_margin" = "0" + register "vddcr_vdd_voltage_margin" = "0" # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 3ab70a2..c1f82a7 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -15,22 +15,22 @@ # For the below fields, 0 indicates use SOC default # PROCHOT_L de-assertion Ramp Time - register "prochot_l_deassertion_ramp_time" = "20" #mS + register "prochot_l_deassertion_ramp_time_mS" = "20" # Lower die temperature limit - register "thermctl_limit" = "100" #degrees C + register "thermctl_limit_degreeC" = "100" # FP5 Processor Voltage Supply PSI Currents - register "psi0_current_limit" = "18000" #mA - register "psi0_soc_current_limit" = "12000" #mA + register "psi0_current_limit_mA" = "18000" + register "psi0_soc_current_limit_mA" = "12000" register "vddcr_soc_voltage_margin" = "0" #mV register "vddcr_vdd_voltage_margin" = "0" #mV # VRM Limits - register "vrm_maximum_current_limit" = "0" #mA - register "vrm_soc_maximum_current_limit" = "0" #mA - register "vrm_current_limit" = "0" #mA - register "vrm_soc_current_limit" = "0" #mA + register "vrm_maximum_current_limit_mA" = "0" + register "vrm_soc_maximum_current_limit_mA" = "0" + register "vrm_current_limit_mA" = "0" + register "vrm_soc_current_limit_mA" = "0" # Misc SMU settings register "sb_tsi_alert_comparator_mode_en" = "0" diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 674d557..e7f4d40 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "3" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "12000" - register "telemetry_vddcr_vdd_slope" = "65599" #mA + register "telemetry_vddcr_vdd_slope_mA" = "65599" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29788" #mA + register "telemetry_vddcr_soc_slope_mA" = "29788" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/dalboz/overridetree.cb b/src/mainboard/google/zork/variants/dalboz/overridetree.cb index 1ddb17b..961fc12 100644 --- a/src/mainboard/google/zork/variants/dalboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dalboz/overridetree.cb @@ -9,17 +9,17 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mw" = "6000" + register "fast_ppt_limit_mw" = "9000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "2500" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "30231" #mA + register "telemetry_vddcr_vdd_slope_mA" = "30231" register "telemetry_vddcr_vdd_offset" = "0-1" - register "telemetry_vddcr_soc_slope" = "22644" #mA + register "telemetry_vddcr_soc_slope_mA" = "22644" register "telemetry_vddcr_soc_offset" = "68" # I2C2 for touchscreen and trackpad diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index a11fa5e..5aed9d3 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "2500" + register "sustained_power_limit_mW" = "4800" - register "telemetry_vddcr_vdd_slope" = "42465" #mA + register "telemetry_vddcr_vdd_slope_mA" = "42465" register "telemetry_vddcr_vdd_offset" = "69" - register "telemetry_vddcr_soc_slope" = "42667" #mA + register "telemetry_vddcr_soc_slope_mA" = "42667" register "telemetry_vddcr_soc_offset" = "167" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb index 5ef2f0a..1846f51 100644 --- a/src/mainboard/google/zork/variants/ezkinil/overridetree.cb +++ b/src/mainboard/google/zork/variants/ezkinil/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "12000" - register "telemetry_vddcr_vdd_slope" = "62413" #mA + register "telemetry_vddcr_vdd_slope_mA" = "62413" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/morphius/overridetree.cb b/src/mainboard/google/zork/variants/morphius/overridetree.cb index 43a9439..78c516f 100644 --- a/src/mainboard/google/zork/variants/morphius/overridetree.cb +++ b/src/mainboard/google/zork/variants/morphius/overridetree.cb @@ -9,24 +9,24 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "20000" #mw - register "fast_ppt_limit" = "24000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "12000" #mw - register "thermctl_limit" = "100" #degrees C + register "slow_ppt_limit_mW" = "20000" + register "fast_ppt_limit_mW" = "24000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "12000" + register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcr_vdd_slope" = "78709" #mA + register "telemetry_vddcr_vdd_slope_mA" = "78709" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "29035" #mA + register "telemetry_vddcr_soc_slope_mA" = "29035" register "telemetry_vddcr_soc_offset" = "0" # Set STAPM confiuration for tablet mode register "dptc_enable" = "1" - register "slow_ppt_limit_tablet_mode" = "20000" #mw - register "fast_ppt_limit_tablet_mode" = "24000" #mw - register "sustained_power_limit_tablet_mode" = "12000" #mw - register "thermctl_limit_tablet_mode" = "70" #degrees C + register "slow_ppt_limit_tablet_mode_mW" = "20000" + register "fast_ppt_limit_tablet_mode_mW" = "24000" + register "sustained_power_limit_tablet_mode_mW" = "12000" + register "thermctl_limit_tablet_mode_degreeC" = "70" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index f06f03d..d2385c6 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -9,15 +9,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "71222" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/mainboard/google/zork/variants/vilboz/overridetree.cb b/src/mainboard/google/zork/variants/vilboz/overridetree.cb index a93beb5..fe11a88 100644 --- a/src/mainboard/google/zork/variants/vilboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/vilboz/overridetree.cb @@ -10,17 +10,17 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" # mW - register "fast_ppt_limit" = "9000" # mW - register "slow_ppt_time_constant" = "5" # second - register "stapm_time_constant" = "1400" # second - register "sustained_power_limit" = "4800" # mW + register "slow_ppt_limit_mW" = "6000" # mW + register "fast_ppt_limit_mW" = "9000" # mW + register "slow_ppt_time_constant_sec" = "5" # second + register "stapm_time_constant_sec" = "1400" # second + register "sustained_power_limit_mW" = "4800" # mW # End : OPN Performance Configuration - register "telemetry_vddcr_vdd_slope" = "32643" #mA + register "telemetry_vddcr_vdd_slope_mA" = "32643" #mA register "telemetry_vddcr_vdd_offset" = "208" - register "telemetry_vddcr_soc_slope" = "22742" #mA + register "telemetry_vddcr_soc_slope_mA" = "22742" #mA register "telemetry_vddcr_soc_offset" = "-83" # USB OC pin mapping diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index 19d66fc..fa8fefc 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -10,15 +10,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "102586" #mA + register "telemetry_vddcr_vdd_slope_mA" = "102586" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "26967" #mA + register "telemetry_vddcr_soc_slope_mA" = "26967" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h index 3098a81..1813289 100644 --- a/src/soc/amd/picasso/chip.h +++ b/src/soc/amd/picasso/chip.h @@ -102,22 +102,22 @@ uint8_t system_config; /* STAPM Configuration */ - uint32_t fast_ppt_limit; - uint32_t slow_ppt_limit; - uint32_t slow_ppt_time_constant; - uint32_t stapm_time_constant; - uint32_t sustained_power_limit; + uint32_t fast_ppt_limit_mW; + uint32_t slow_ppt_limit_mW; + uint32_t slow_ppt_time_constant_sec; + uint32_t stapm_time_constant_sec; + uint32_t sustained_power_limit_mW; /* Enable dptc for tablet mode (0 = disable, 1 = enable) */ uint8_t dptc_enable; /* STAPM Configuration for tablet mode (need enable dptc_enable first) */ - uint32_t fast_ppt_limit_tablet_mode; - uint32_t slow_ppt_limit_tablet_mode; - uint32_t sustained_power_limit_tablet_mode; + uint32_t fast_ppt_limit_tablet_mode_mW; + uint32_t slow_ppt_limit_tablet_mode_mW; + uint32_t sustained_power_limit_tablet_mode_mW; /* PROCHOT_L de-assertion Ramp Time */ - uint32_t prochot_l_deassertion_ramp_time; + uint32_t prochot_l_deassertion_ramp_time_mS; enum { DOWNCORE_AUTO = 0, @@ -128,29 +128,29 @@ uint8_t smt_disable; /* 1=disable SMT, 0=enable SMT */ /* Lower die temperature limit */ - uint32_t thermctl_limit; - uint32_t thermctl_limit_tablet_mode; + uint32_t thermctl_limit_degreeC; + uint32_t thermctl_limit_tablet_mode_degreeC; /* FP5 Processor Voltage Supply PSI Currents. 0 indicates use SOC default */ - uint32_t psi0_current_limit; - uint32_t psi0_soc_current_limit; + uint32_t psi0_current_limit_mA; + uint32_t psi0_soc_current_limit_mA; uint32_t vddcr_soc_voltage_margin; uint32_t vddcr_vdd_voltage_margin; /* VRM Limits. 0 indicates use SOC default */ - uint32_t vrm_maximum_current_limit; - uint32_t vrm_soc_maximum_current_limit; - uint32_t vrm_current_limit; - uint32_t vrm_soc_current_limit; + uint32_t vrm_maximum_current_limit_mA; + uint32_t vrm_soc_maximum_current_limit_mA; + uint32_t vrm_current_limit_mA; + uint32_t vrm_soc_current_limit_mA; /* Misc SMU settings */ uint8_t sb_tsi_alert_comparator_mode_en; uint8_t core_dldo_bypass; uint8_t min_soc_vid_offset; uint8_t aclk_dpm0_freq_400MHz; - uint32_t telemetry_vddcr_vdd_slope; + uint32_t telemetry_vddcr_vdd_slope_mA; uint32_t telemetry_vddcr_vdd_offset; - uint32_t telemetry_vddcr_soc_slope; + uint32_t telemetry_vddcr_soc_slope_mA; uint32_t telemetry_vddcr_soc_offset; struct { diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index b967431..6da5b0d 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -105,37 +105,37 @@ mcfg->system_config = config->system_config; - if ((config->slow_ppt_limit) && - (config->fast_ppt_limit) && - (config->slow_ppt_time_constant) && - (config->stapm_time_constant)) { - mcfg->slow_ppt_limit = config->slow_ppt_limit; - mcfg->fast_ppt_limit = config->fast_ppt_limit; - mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant; - mcfg->stapm_time_constant = config->stapm_time_constant; + if ((config->slow_ppt_limit_mW) && + (config->fast_ppt_limit_mW) && + (config->slow_ppt_time_constant_sec) && + (config->stapm_time_constant_sec)) { + mcfg->slow_ppt_limit_mW = config->slow_ppt_limit_mW; + mcfg->fast_ppt_limit_mW = config->fast_ppt_limit_mW; + mcfg->slow_ppt_time_constant_sec = config->slow_ppt_time_constant_sec; + mcfg->stapm_time_constant_sec = config->stapm_time_constant_sec; } mcfg->ccx_down_core_mode = config->downcore_mode; mcfg->ccx_disable_smt = config->smt_disable; - mcfg->sustained_power_limit = config->sustained_power_limit; - mcfg->prochot_l_deassertion_ramp_time = config->prochot_l_deassertion_ramp_time; - mcfg->thermctl_limit = config->thermctl_limit; - mcfg->psi0_current_limit = config->psi0_current_limit; - mcfg->psi0_soc_current_limit = config->psi0_soc_current_limit; + mcfg->sustained_power_limit_mW = config->sustained_power_limit_mW; + mcfg->prochot_l_deassertion_ramp_time_mS = config->prochot_l_deassertion_ramp_time_mS; + mcfg->thermctl_limit_degreeC = config->thermctl_limit_degreeC; + mcfg->psi0_current_limit_mA = config->psi0_current_limit_mA; + mcfg->psi0_soc_current_limit_mA = config->psi0_soc_current_limit_mA; mcfg->vddcr_soc_voltage_margin = config->vddcr_soc_voltage_margin; mcfg->vddcr_vdd_voltage_margin = config->vddcr_vdd_voltage_margin; - mcfg->vrm_maximum_current_limit = config->vrm_maximum_current_limit; - mcfg->vrm_soc_maximum_current_limit = config->vrm_soc_maximum_current_limit; - mcfg->vrm_current_limit = config->vrm_current_limit; - mcfg->vrm_soc_current_limit = config->vrm_soc_current_limit; + mcfg->vrm_maximum_current_limit_mA = config->vrm_maximum_current_limit_mA; + mcfg->vrm_soc_maximum_current_limit_mA = config->vrm_soc_maximum_current_limit_mA; + mcfg->vrm_current_limit_mA = config->vrm_current_limit_mA; + mcfg->vrm_soc_current_limit_mA = config->vrm_soc_current_limit_mA; mcfg->sb_tsi_alert_comparator_mode_en = config->sb_tsi_alert_comparator_mode_en; mcfg->core_dldo_bypass = config->core_dldo_bypass; mcfg->min_soc_vid_offset = config->min_soc_vid_offset; mcfg->aclk_dpm0_freq_400MHz = config->aclk_dpm0_freq_400MHz; - mcfg->telemetry_vddcr_vdd_slope = config->telemetry_vddcr_vdd_slope; + mcfg->telemetry_vddcr_vdd_slope_mA = config->telemetry_vddcr_vdd_slope_mA; mcfg->telemetry_vddcr_vdd_offset = config->telemetry_vddcr_vdd_offset; - mcfg->telemetry_vddcr_soc_slope = config->telemetry_vddcr_soc_slope; + mcfg->telemetry_vddcr_soc_slope_mA = config->telemetry_vddcr_soc_slope_mA; mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset; mcfg->hd_audio_enable = devtree_hda_dev_enabled(); mcfg->sata_enable = devtree_sata_dev_enabled(); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 174cddc..72a0974 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -200,15 +200,15 @@ if (!config->dptc_enable) return; - struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit, - config->sustained_power_limit, - config->fast_ppt_limit, - config->slow_ppt_limit); + struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, + config->sustained_power_limit_mW, + config->fast_ppt_limit_mW, + config->slow_ppt_limit_mW); struct dptc_input tablet_mode_input = DPTC_INPUTS( - config->thermctl_limit_tablet_mode, - config->sustained_power_limit_tablet_mode, - config->fast_ppt_limit_tablet_mode, - config->slow_ppt_limit_tablet_mode); + config->thermctl_limit_tablet_mode_degreeC, + config->sustained_power_limit_tablet_mode_mW, + config->fast_ppt_limit_tablet_mode_mW, + config->slow_ppt_limit_tablet_mode_mW); /* Scope (\_SB) */ acpigen_write_scope("\\_SB"); diff --git a/src/vendorcode/amd/fsp/picasso/FspmUpd.h b/src/vendorcode/amd/fsp/picasso/FspmUpd.h index 56e1a5e..57002f0 100644 --- a/src/vendorcode/amd/fsp/picasso/FspmUpd.h +++ b/src/vendorcode/amd/fsp/picasso/FspmUpd.h @@ -18,33 +18,33 @@ /** Offset 0x004C**/ uint32_t serial_port_stride; /** Offset 0x0050**/ uint32_t serial_port_baudrate; /** Offset 0x0054**/ uint32_t serial_port_refclk; - /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope; - /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2; - /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3; - /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4; - /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5; + /** Offset 0x0058**/ uint32_t telemetry_vddcr_vdd_slope_mA; + /** Offset 0x005C**/ uint32_t telemetry_vddcr_vdd_slope2_mA; + /** Offset 0x0060**/ uint32_t telemetry_vddcr_vdd_slope3_mA; + /** Offset 0x0064**/ uint32_t telemetry_vddcr_vdd_slope4_mA; + /** Offset 0x0068**/ uint32_t telemetry_vddcr_vdd_slope5_mA; /** Offset 0x006C**/ uint32_t telemetry_vddcr_vdd_offset; - /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope; + /** Offset 0x0070**/ uint32_t telemetry_vddcr_soc_slope_mA; /** Offset 0x0074**/ uint32_t telemetry_vddcr_soc_offset; /** Offset 0x0078**/ uint8_t aa_mode_en; /** Offset 0x0079**/ uint8_t unused2; /** Offset 0x007A**/ uint8_t unused3; /** Offset 0x007B**/ uint8_t unused4; - /** Offset 0x007C**/ uint32_t fast_ppt_limit; - /** Offset 0x0080**/ uint32_t slow_ppt_limit; - /** Offset 0x0084**/ uint32_t slow_ppt_time_constant; - /** Offset 0x0088**/ uint32_t psi0_current_limit; - /** Offset 0x008C**/ uint32_t psi0_soc_current_limit; - /** Offset 0x0090**/ uint32_t thermctl_limit; - /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit; - /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit; - /** Offset 0x009C**/ uint32_t sustained_power_limit; - /** Offset 0x00A0**/ uint32_t stapm_time_constant; - /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time; - /** Offset 0x00A8**/ uint32_t vrm_current_limit; - /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit; - /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin; - /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin; + /** Offset 0x007C**/ uint32_t fast_ppt_limit_mw; + /** Offset 0x0080**/ uint32_t slow_ppt_limit_mw; + /** Offset 0x0084**/ uint32_t slow_ppt_time_constant_sec; + /** Offset 0x0088**/ uint32_t psi0_current_limit_mA; + /** Offset 0x008C**/ uint32_t psi0_soc_current_limit_mA; + /** Offset 0x0090**/ uint32_t thermctl_limit_degreeC; + /** Offset 0x0094**/ uint32_t vrm_maximum_current_limit_mA; + /** Offset 0x0098**/ uint32_t vrm_soc_maximum_current_limit_mA; + /** Offset 0x009C**/ uint32_t sustained_power_limit_mW; + /** Offset 0x00A0**/ uint32_t stapm_time_constant_sec; + /** Offset 0x00A4**/ uint32_t prochot_l_deassertion_ramp_time_mS; + /** Offset 0x00A8**/ uint32_t vrm_current_limit_mA; + /** Offset 0x00AC**/ uint32_t vrm_soc_current_limit_mA; + /** Offset 0x00B0**/ uint32_t vddcr_soc_voltage_margin_mV; + /** Offset 0x00B4**/ uint32_t vddcr_vdd_voltage_margin_mV; /** Offset 0x00B8**/ uint32_t smu_feature_control_defines; /** Offset 0x00BC**/ uint32_t smu_feature_control_defines_ext; /** Offset 0x00C0**/ uint8_t sb_tsi_alert_comparator_mode_en; diff --git a/util/mainboard/google/dalboz/template/overridetree.cb b/util/mainboard/google/dalboz/template/overridetree.cb index 7645ba3..d870177 100644 --- a/util/mainboard/google/dalboz/template/overridetree.cb +++ b/util/mainboard/google/dalboz/template/overridetree.cb @@ -10,11 +10,11 @@ register "system_config" = "1" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "6000" #mw - register "fast_ppt_limit" = "9000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "2500" #second - register "sustained_power_limit" = "4800" #mw + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "2500" + register "sustained_power_limit_mW" = "4800" # End : OPN Performance Configuration diff --git a/util/mainboard/google/trembyle/template/overridetree.cb b/util/mainboard/google/trembyle/template/overridetree.cb index d332fce..9788025 100644 --- a/util/mainboard/google/trembyle/template/overridetree.cb +++ b/util/mainboard/google/trembyle/template/overridetree.cb @@ -10,15 +10,15 @@ register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect - register "slow_ppt_limit" = "25000" #mw - register "fast_ppt_limit" = "30000" #mw - register "slow_ppt_time_constant" = "5" #second - register "stapm_time_constant" = "200" #second - register "sustained_power_limit" = "15000" #mw + register "slow_ppt_limit_mW" = "25000" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_time_constant_sec" = "5" + register "stapm_time_constant_sec" = "200" + register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope" = "71222" #mA + register "telemetry_vddcr_vdd_slope_mA" = "71222" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope" = "28977" #mA + register "telemetry_vddcr_soc_slope_mA" = "28977" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/46840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I056a76663e84ebc940343d64178c18cb20df01a3 Gerrit-Change-Number: 46840 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Maulik V Vaghela (Code Review) 06 Nov '20

06 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46842 to look at the new patch set (#11). Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... soc/intel/jasperlake: Correct GPIO pad sequence for community pad group In gpio.c file, we have community group array for each comm, representing gpio groups within that community. Like there might be group H,D, VGPIO and C within community 1. Community also may have some reserved gpio and we also define those in an array which indicates OS can't use those GPIO (through PAD_BASE_NONE) Now when we define reserved pads in the middle of actual community pads, it creates an issue while calculating an offset for GPIO host own pad register. This is because function actually checks current gpio index (lets say vgpio_39 in our case) and tries to get group index from an array which we have defined. If we have defined reserved gpios in between 2 communities, index calculated will also account for reserved GPIO and register offset calculation will move to next set of register (offset 0xC instead of offset 0x8). Because of this coreboot won't configure HOST_OWN_PAD register correctly and driver will not be able to get non-SMI interrupts for related gpio. Align pad group as per EDS and pin-ctrl driver in linux kernel. Reference: DOC#618876 (EDS volume 2) BUG=None BRANCH=None TEST=VGPIO community index is correctly calculated. Drawlat board boots fine with this change and warm reset also works. Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/gpio.c 1 file changed, 11 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 11 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Michael Niewöhner (Code Review) 06 Nov '20

06 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 5: @Angel opinions on this? https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c#1331 -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 10:19:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Michael Niewöhner (Code Review) 06 Nov '20

06 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c@1331 PS5, Line 1331: soc_residency_counter(&lpit->lpit_soc); > Michael. Again should this be in "src/arch/x86/acpi. […] acpi_create_lpit is right in src/acpi/acpi.c IMO; I'm not sure about system_residency_counter and soc_residency_counter which could be better in src/arch/x86/acpi.c @Angel what do you think? -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 10:19:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Maulik V Vaghela (Code Review) 06 Nov '20

06 Nov '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... Patch Set 10: Rebased patchset 9 to avoid merge conflict. -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 06 Nov 2020 10:15:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Maulik V Vaghela (Code Review) 06 Nov '20

06 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46842 to look at the new patch set (#10). Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... soc/intel/jasperlake: Correct GPIO pad sequence for community pad group In gpio.c file, we have community group array for each comm, representing gpio groups within that community. Like there might be group H,D, VGPIO and C within community 1. Community also may have some reserved gpio and we also define those in an array which indicates OS can't use those GPIO (through PAD_BASE_NONE) Now when we define reserved pads in the middle of actual community pads, it creates an issue while calculating an offset for GPIO host own pad register. This is because function actually checks current gpio index (lets say vgpio_39 in our case) and tries to get group index from an array which we have defined. If we have defined reserved gpios in between 2 communities, index calculated will also account for reserved GPIO and register offset calculation will move to next set of register (offset 0xC instead of offset 0x8). Because of this coreboot won't configure HOST_OWN_PAD register correctly and driver will not be able to get non-SMI interrupts for related gpio. Align pad group as per EDS and pin-ctrl driver in linux kernel. Reference: DOC#618876 (EDS volume 2) BUG=None BRANCH=None TEST=VGPIO community index is correctly calculated. Drawlat board boots fine with this change and warm reset also works. Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/gpio.c 1 file changed, 11 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 10 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 06 Nov '20

06 Nov '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c@1331 PS5, Line 1331: soc_residency_counter(&lpit->lpit_soc); Michael. Again should this be in "src/arch/x86/acpi.c" ? https://review.coreboot.org/c/coreboot/+/32350/5/src/arch/x86/Kconfig File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/32350/5/src/arch/x86/Kconfig@264 PS5, Line 264: help Michael, do you think this should be here or src/Kconfig. LPIT doc says its Intel specific feature so i moved it here. Please suggest? -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 09:59:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 06 Nov '20

06 Nov '20

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 5: This is still WIP, not finished working on all the comments. i am uploading a WIP patch here as the old patch was too outdated and had few merge conflicts while trying to cherry pick. -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 06 Nov 2020 09:54:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP]src/arch/x86:Add support for low power idle table
by Shaunak Saha (Code Review) 06 Nov '20

06 Nov '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Justin TerAvest, Paul Menzel, Duncan Laurie, Patrick Rudolph, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32350 to look at the new patch set (#5). Change subject: [WIP]src/arch/x86:Add support for low power idle table ...................................................................... [WIP]src/arch/x86:Add support for low power idle table Add coreboot support for LPIT residency.Residencies for each low power state can be read via FFH (Function fixed hardware) or a memory mapped interface. On platforms supporting S0ix sleep states, there can be two types of residencies: CPU PKG C10 (Read via FFH interface) Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface) The following attributes are added dynamically to the cpuidle sysfs attribute group: /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us The “low_power_idle_cpu_residency_us” attribute shows time spent by the CPU package in PKG C10. The “low_power_idle_system_residency_us” attribute shows SLP_S0 residency, or system time spent with the SLP_S0# signal asserted. This is the lowest possible system power state, achieved only when CPU is in PKG C10 and all functional blocks in PCH are in a low power state. In this patch we can set the residency via FFH or memory mapped depending on how we set the residency counter address. Example: 1. For CNL: space_id:0,residency_counter.addrl:0x632 and ACPI_LPIT selected in soc Kconfig sysfs file thet kernel creates is /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us. 2. For CNL: space_id:0, residency_counter.addrl:0xfe000000 + 0x193C and ACPI_LPIT elected in soc Kconfig sysfs file thet kernel creates is /sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 --- M src/acpi/acpi.c M src/arch/x86/Kconfig M src/include/acpi/acpi.h 3 files changed, 144 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32350/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 5 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit November 2020