Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46842
to look at the new patch set (#11).
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
......................................................................
soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)
Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).
Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.
Align pad group as per EDS and pin-ctrl driver in linux kernel.
Reference: DOC#618876 (EDS volume 2)
BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.
Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/jasperlake/gpio.c
1 file changed, 11 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/11
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 )
Change subject: [WIP]src/arch/x86:Add support for low power idle table
......................................................................
Patch Set 5:
@Angel opinions on this? https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c#1331
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 )
Change subject: [WIP]src/arch/x86:Add support for low power idle table
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c@1331
PS5, Line 1331: soc_residency_counter(&lpit->lpit_soc);
> Michael. Again should this be in "src/arch/x86/acpi. […]
acpi_create_lpit is right in src/acpi/acpi.c IMO; I'm not sure about system_residency_counter and soc_residency_counter which could be better in src/arch/x86/acpi.c
@Angel what do you think?
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Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 )
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
......................................................................
Patch Set 10:
Rebased patchset 9 to avoid merge conflict.
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Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46842
to look at the new patch set (#10).
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
......................................................................
soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)
Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).
Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.
Align pad group as per EDS and pin-ctrl driver in linux kernel.
Reference: DOC#618876 (EDS volume 2)
BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.
Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/jasperlake/gpio.c
1 file changed, 11 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/10
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Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 )
Change subject: [WIP]src/arch/x86:Add support for low power idle table
......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/32350/5/src/acpi/acpi.c@1331
PS5, Line 1331: soc_residency_counter(&lpit->lpit_soc);
Michael. Again should this be in "src/arch/x86/acpi.c" ?
https://review.coreboot.org/c/coreboot/+/32350/5/src/arch/x86/Kconfig
File src/arch/x86/Kconfig:
https://review.coreboot.org/c/coreboot/+/32350/5/src/arch/x86/Kconfig@264
PS5, Line 264: help
Michael, do you think this should be here or src/Kconfig. LPIT doc says its Intel specific feature so i moved it here. Please suggest?
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Change subject: [WIP]src/arch/x86:Add support for low power idle table
......................................................................
Patch Set 5:
This is still WIP, not finished working on all the comments. i am uploading a WIP patch here as the old patch was too outdated and had few merge conflicts while trying to cherry pick.
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Justin TerAvest, Paul Menzel, Duncan Laurie, Patrick Rudolph, Karthikeyan Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: [WIP]src/arch/x86:Add support for low power idle table
......................................................................
[WIP]src/arch/x86:Add support for low power idle table
Add coreboot support for LPIT residency.Residencies for each low power state
can be read via FFH (Function fixed hardware) or a memory mapped interface.
On platforms supporting S0ix sleep states, there can be two types of
residencies:
CPU PKG C10 (Read via FFH interface)
Platform Controller Hub (PCH) SLP_S0 (Read via memory mapped interface)
The following attributes are added dynamically to the cpuidle sysfs attribute
group:
/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
The “low_power_idle_cpu_residency_us” attribute shows time spent by the CPU
package in PKG C10.
The “low_power_idle_system_residency_us” attribute shows SLP_S0 residency, or
system time spent with the SLP_S0# signal asserted. This is the lowest possible
system power state, achieved only when CPU is in PKG C10 and all functional
blocks in PCH are in a low power state. In this patch we can set the residency
via FFH or memory mapped depending on how we set the residency counter address.
Example:
1. For CNL: space_id:0,residency_counter.addrl:0x632 and ACPI_LPIT
selected in soc Kconfig sysfs file thet kernel creates is
/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us.
2. For CNL: space_id:0, residency_counter.addrl:0xfe000000 + 0x193C
and ACPI_LPIT elected in soc Kconfig sysfs file thet kernel creates is
/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us
Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com>
Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137
---
M src/acpi/acpi.c
M src/arch/x86/Kconfig
M src/include/acpi/acpi.h
3 files changed, 144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32350/5
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 )
Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 32: 0,
> SG. I didn't mean to say that it should be done as part of this CL. […]
ack :-)
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