Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthikeyan Ramasubramanian,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: soc/intel/common/acpi: drop return value for disabled PEPD function 2
......................................................................
soc/intel/common/acpi: drop return value for disabled PEPD function 2
PEPD function 2 is currently unused and disabled. Thus, drop the return
value, which matches the default return value.
Change-Id: Ia95b8b36fcb78e8976b66de15ec214a38c178cda
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi/pep.asl
1 file changed, 0 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/47139/8
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47247
to look at the new patch set (#3).
Change subject: soc/intel/common/acpi: rename PEPD/LPI macros for clarification
......................................................................
soc/intel/common/acpi: rename PEPD/LPI macros for clarification
`ARG2` in the macro's names does not really provide any useful
information. Drop it and add `LPI` to clarify the relation to only
low-power idle states.
Change-Id: I8d44c9e4974c7f34aa5c32ba00328725f536fda6
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi/pep.asl
1 file changed, 14 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47247/3
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthikeyan Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46470
to look at the new patch set (#8).
Change subject: soc/intel/common/acpi: rename LPID to PEPD
......................................................................
soc/intel/common/acpi: rename LPID to PEPD
Rename LPID to PEPD for consistency. PEPD means "Power Engine Plug-In
Device" and is the name Intel and vendors usually use, so let's comply.
Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/mainboard/google/drallion/variants/drallion/include/variant/acpi/mainboard.asl
M src/mainboard/google/sarien/variants/arcada/include/variant/acpi/mainboard.asl
M src/mainboard/google/sarien/variants/sarien/include/variant/acpi/mainboard.asl
M src/mainboard/google/volteer/mainboard.asl
M src/soc/intel/common/block/acpi/acpi/pep.asl
5 files changed, 20 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/46470/8
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Angel Pons, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#5).
Change subject: soc/intel/common/acpi: move S0ix UUID to the condition
......................................................................
soc/intel/common/acpi: move S0ix UUID to the condition
Move the UUID to the condition, since there is no need to assign a name
when it is only used once. Also add a comment to make clear that the
functions inside that condition are only used by the Low Power Idle S0
functionality, while the PEPD in general can be present on boards
without S0ix capability, too. For details check CB:46469.
Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi/pep.asl
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/46468/5
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Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, Venkata Krishna Nimmagadda,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47246
to look at the new patch set (#3).
Change subject: soc/intel/common/acpi: drop the southridge scope around PEPD
......................................................................
soc/intel/common/acpi: drop the southridge scope around PEPD
PEPD will get included directly in the southbridge. Thus, drop the
scope around it.
Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
M src/soc/intel/common/block/acpi/acpi/pep.asl
1 file changed, 74 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47246/3
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 )
Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 32: 0,
> I agree with what Angel said. We should eventually move this to SSDT. […]
I don't plan to implement this atm tbh, since I have a) not the time and b) still don't see a reason to do this. If anyone finds a real advantage of doing so, feel free to implement it.
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Gerrit-MessageType: comment
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 )
Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 32: 0,
> Anything can be considered unreadable when one does not want to read :) […]
I agree with what Angel said. We should eventually move this to SSDT. It definitely provides more flexibility to do board-level configuration as well.
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Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 )
Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 32: 0,
> Option 2 doesn't look too bad? Or does that seem unreadable as well?
Anything can be considered unreadable when one does not want to read :)
Thinking forward, we might want to have this generated depending on board settings, e.g. through a SSDT. It shouldn't be too hard since we have the devicetree and device ACPI names can easily be obtained in C through acpi_name function pointers.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 )
Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 32: 0,
> hm, I've tried it but it makes it so damn unreadable... […]
Option 2 doesn't look too bad? Or does that seem unreadable as well?
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