coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… PS8, Line 32: 0, > will do hm, I've tried it but it makes it so damn unreadable... does that really provide useful information? I mean... it's a dummy package Option 1: ~~~ 39 If(Arg2 == PEPD_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { 40 Return (Package() { 41 Package() { 42 /* \DUMY - not existent */ 43 "\\DUMY", 44 /* disabled, no constraints */ 45 0, 46 Package() { 47 /* revision */ 48 0, 49 Package() { 50 /* apply to all LPIT states */ 51 0xff, 52 /* minimum D-state */ 53 0 54 } 55 } 56 } 57 } 58 ) 59 } ~~~ Option 2: ~~~ 39 If(Arg2 == PEPD_DSM_ARG2_GET_DEVICE_CONSTRAINTS) { 40 Return (Package() { 41 Package() { 42 "\\DUMY", /* \DUMY - not existent */ 43 0, /* disabled, no constraints */ 44 Package() { 45 0, /* revision */ 46 Package() { 47 0xff, /* apply to all LPIT states */ 48 0 49 } 50 } 51 } 52 } 53 ) 54 } ~~~ -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Nov 2020 23:42:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… PS8, Line 31: DUMMY > I'd use CPU0 just because it should exist everywhere. well, \DUMY should be ok then -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Nov 2020 22:58:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Disable C1 Cstate Demotion
by Ravishankar Sarawadi (Code Review) 05 Nov '20

05 Nov '20

Ravishankar Sarawadi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46438 ) Change subject: soc/intel/tigerlake: Disable C1 Cstate Demotion ...................................................................... soc/intel/tigerlake: Disable C1 Cstate Demotion Disable C1 state auto demotion to improve SoC power. When set, processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information. BUG=b:161215906 TEST=Measure and confirm power usage reduction for key use cases eg 'Google Meets video call' Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Signed-off-by: Shweta Malik <shweta.malik(a)intel.com> Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1 --- M src/soc/intel/tigerlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/46438/1 diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 38f444b..f9f17f8 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -357,6 +357,10 @@ /* EnableMultiPhaseSiliconInit for running MultiPhaseSiInit */ params->EnableMultiPhaseSiliconInit = 1; + + /* Disable C1 Cstate Demotion */ + params->C1StateAutoDemotion = 0; + mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46438 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I649cafbaf03917d76521aa5f76ec58d218e1a1b1 Gerrit-Change-Number: 46438 Gerrit-PatchSet: 1 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Angel Pons (Code Review) 05 Nov '20

05 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… PS8, Line 31: DUMMY > Agree that Linux doesn't really check it. […] I'd use CPU0 just because it should exist everywhere. -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Nov 2020 22:57:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Furquan Shaikh (Code Review) 05 Nov '20

05 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block… PS8, Line 31: DUMMY > well, neither windows nor Linux complains 😄 (we could use CPU0 here for example). […] Agree that Linux doesn't really check it. But, I think it would be good to have a valid namestring as per ACPI spec -- not necessarily a device that exists, but a string that is valid. Even DUMY could work? No idea about Windows. -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Nov 2020 22:54:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: drop the southridge scope around PEPD
by Nico Huber (Code Review) 05 Nov '20

05 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47246 ) Change subject: soc/intel/common/acpi: drop the southridge scope around PEPD ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG@9 PS2, Line 9: PEPD will get included directly in the southbridge. > IMO that's not an argument. […] I agree with Michael. Also, other devices in this directory also don't specify their exact scope (and I think for this PEPD, it matters even less, probably just needs to be somewhere below _SB). -- To view, visit https://review.coreboot.org/c/coreboot/+/47246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87 Gerrit-Change-Number: 47246 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 22:50:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: drop the southridge scope around PEPD
by Furquan Shaikh (Code Review) 05 Nov '20

05 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47246 ) Change subject: soc/intel/common/acpi: drop the southridge scope around PEPD ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG@9 PS2, Line 9: PEPD will get included directly in the southbridge. > IMO that's not an argument. […] I typically add the Scope in common code especially when it is known that the content of that file must end in some specific scope. It reduces the effort required for debugging later in case it is not included correctly in SoC or mainboard code or some refactor changes things. I understand it is upto the caller to ensure that, but I think of it as belt and suspenders. Anyways, if you feel strongly about dropping the scope around the device, I think at minimum having a comment in the file w.r.t. expectations would be good. -- To view, visit https://review.coreboot.org/c/coreboot/+/47246 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb7a40e476966a7aca36bee055ee71d181508b87 Gerrit-Change-Number: 47246 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 22:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC]mb/ocp/deltalake: append Linuxboot command line option
by Jonathan Zhang (Code Review) 05 Nov '20

05 Nov '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47055 ) Change subject: [RFC]mb/ocp/deltalake: append Linuxboot command line option ...................................................................... [RFC]mb/ocp/deltalake: append Linuxboot command line option If Linuxboot is used as payload, and if corresponding VPD variable is set, use the value to append Linuxboot command line option as defined at build time. With this, user can customize linuxboot boot behavior without needing a different image. For example, user can increase log level. Note that this code should not be in mainboard, I hope to get community feedback on where it should be. TESTED=tested on DeltaLake, with this VPD setting: vpd -f build/coreboot.rom -i RW_VPD -s linux_command_line="loglevel=7 cpuidle.off=1" Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Signed-off-by: Bryant Ou <Bryant.Ou.Q(a)gmail.com> Change-Id: I5f5cde3957c2716864f55d70f18f47b493164ed8 --- M src/mainboard/ocp/deltalake/ramstage.c M src/mainboard/ocp/deltalake/vpd.h 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/47055/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 9d57090..800ad5a 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -5,11 +5,13 @@ #include <bootstate.h> #include <drivers/ipmi/ipmi_ops.h> #include <drivers/ocp/dmi/ocp_dmi.h> +#include <drivers/vpd/vpd.h> #include <gpio.h> #include <soc/lewisburg_pch_gpio_defs.h> #include <soc/ramstage.h> #include <soc/soc_util.h> #include <stdio.h> +#include <stdlib.h> #include <string.h> #include <smbios.h> #include <device/pci_def.h> @@ -18,10 +20,15 @@ #include <hob_iiouds.h> #include <hob_memmap.h> #include <cpxsp_dl_gpio.h> +#include <program_loading.h> #include "ipmi.h" +#include "vpd.h" #define SLOT_ID_LEN 2 +/* copied from util/cbfstool/linux_trampoline.h */ +#define COMMAND_LINE_LOC 0x91000 +#define LINUX_CMD_LEN 72 extern struct fru_info_str fru_strings; static char slot_id_str[SLOT_ID_LEN]; @@ -307,3 +314,42 @@ } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, pull_post_complete_pin, NULL); + +#if CONFIG_PAYLOAD_LINUX +/* + * If Linuxboot is the payload, and if LINUX_COMMAND_LINE is defined as VPD + * variable, use the value to append original Linux command line option as + * defined at build time + */ +void platform_segment_loaded(uintptr_t start, size_t size, int flags) +{ + if (start != COMMAND_LINE_LOC) + return; + + char cmdline[LINUX_CMD_LEN] = ""; + if (!vpd_gets(LINUX_COMMAND_LINE, cmdline, LINUX_CMD_LEN, VPD_RW_THEN_RO)) + return; + + char *orig_cmdline = strdup((char *)start); + char *new_cmdline = NULL; + size_t new_cmdline_len; + printk(BIOS_INFO, "Build time defined Linux command line: %s\n", + orig_cmdline); + printk(BIOS_INFO, "VPD defined Linux command line: %s\n", cmdline); + + new_cmdline = strconcat(orig_cmdline, " "); + new_cmdline = strconcat(new_cmdline, cmdline); + new_cmdline_len = strlen(new_cmdline); + printk(BIOS_INFO, "Updated Linux command line: %s, len: %ld\n", new_cmdline, new_cmdline_len); + if (new_cmdline_len >= size) { + printk(BIOS_ERR, "Updated Linux command line has size %ld bigger than %ld.\n", + new_cmdline_len, size); + free(new_cmdline); + return; + } + + memset((uint8_t *)start, 0, size); + memcpy((uint8_t *)start, new_cmdline, strlen(new_cmdline)); + free(new_cmdline); +} +#endif diff --git a/src/mainboard/ocp/deltalake/vpd.h b/src/mainboard/ocp/deltalake/vpd.h index 43070c2..cb9588b 100644 --- a/src/mainboard/ocp/deltalake/vpd.h +++ b/src/mainboard/ocp/deltalake/vpd.h @@ -36,4 +36,7 @@ #define COREBOOT_LOG_LEVEL "coreboot_log_level" #define COREBOOT_LOG_LEVEL_DEFAULT 4 +/* Linuxboot kernel command line */ +#define LINUX_COMMAND_LINE "linux_command_line" + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5cde3957c2716864f55d70f18f47b493164ed8 Gerrit-Change-Number: 47055 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Enable PCH thermal depending on devicetree
by Benjamin Doron (Code Review) 05 Nov '20

05 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47116 ) Change subject: soc/intel/skylake: Enable PCH thermal depending on devicetree ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84bac2cec079370370ecf1e5e4742e6704921d40 Gerrit-Change-Number: 47116 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 22:30:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46471 ) Change subject: soc/intel/common/acpi,mb/*: replace the two obsolete LPID with PEPD ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/c/coreboot/+/46471/4/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/46471/4/src/soc/intel/common/block… PS4, Line 17: Device(PEPD) > refcode and vendor add Name(_UID, 0x1) seems to be optional -- To view, visit https://review.coreboot.org/c/coreboot/+/46471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Gerrit-Change-Number: 46471 Gerrit-PatchSet: 11 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 22:20:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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coreboot-gerrit November 2020