Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47205 )
Change subject: soc/amd/picasso: move MAX_CPUS setting from mainbaord to SoC Kconfig
......................................................................
soc/amd/picasso: move MAX_CPUS setting from mainbaord to SoC Kconfig
Since the mainboard Kconfig is sourced before the SoC one, it's still
possible to override that setting on per-mainboard basis. The maximum
CPU for Picasso is 8, since the chips have only up to 4 cores with up to
two threads each.
Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
---
M src/mainboard/amd/mandolin/Kconfig
M src/mainboard/google/zork/Kconfig
M src/soc/amd/picasso/Kconfig
3 files changed, 4 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47205/1
diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig
index 8e2bd8b..f4032d4 100644
--- a/src/mainboard/amd/mandolin/Kconfig
+++ b/src/mainboard/amd/mandolin/Kconfig
@@ -52,10 +52,6 @@
string
default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
-config MAX_CPUS
- int
- default 8
-
config ONBOARD_VGA_IS_PRIMARY
bool
default y
diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig
index c4f6bf7..eb9092a 100644
--- a/src/mainboard/google/zork/Kconfig
+++ b/src/mainboard/google/zork/Kconfig
@@ -96,10 +96,6 @@
string
default "Google_Zork"
-config MAX_CPUS
- int
- default 8
-
config ONBOARD_VGA_IS_PRIMARY
bool
default y
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 605b0ea..bae2d28 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -193,6 +193,10 @@
hex
default 0x4000000
+config MAX_CPUS
+ int
+ default 8
+
config VGA_BIOS_ID
string
default "1002,15d8,c1"
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Gerrit-Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Gerrit-Change-Number: 47205
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47246 )
Change subject: soc/intel/common/acpi: drop the southridge scope around PEPD
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/47246/2//COMMIT_MSG@9
PS2, Line 9: PEPD will get included directly in the southbridge.
Does it hurt to have the scope around PEPD? Just in case mainboard/SoC including it doesn't use the right scope.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47139 )
Change subject: soc/intel/common/acpi: drop return value for disabled PEPD function 2
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47139/7/src/soc/intel/common/block…
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/47139/7/src/soc/intel/common/block…
PS7, Line 62: }
Maybe add a comment here saying that this is not supported yet. And so function 0 does not advertise support for this function.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 )
Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
......................................................................
Patch Set 8:
(4 comments)
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
File src/soc/intel/common/block/acpi/acpi/pep.asl:
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 23: 1
You can skip the count here and below.
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 23: DEVY
Why create a named object when it is really used once (same logic as your previous CL for UUID)?
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 31: DUMMY
I don't think we can use "DUMMY" here. This has to be a fully-qualified namestring as per the spec.
https://review.coreboot.org/c/coreboot/+/47138/8/src/soc/intel/common/block…
PS8, Line 32: 0,
I know you have captured this in the comment above already. But can you please add individual comments for the package elements too? It is just easier to read without having to go back to spec. e.g. /* Disabled, no constraints */ on this line.
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