Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47175 )
Change subject: ec/google/chromeec: Lower the severity of the debug statement
......................................................................
ec/google/chromeec: Lower the severity of the debug statement
Integrated TypeC MUX is used only in certain SoCs and hence the missing
devicetree configuration is not an error. Lower the severity of the
debug statement.
BUG=b:172186858
TEST=Build and boot to OS in Drawlat.
Change-Id: Ieb76e1ccfd04f1628617b2665b05be6718a25f81
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/ec/google/chromeec/ec_acpi.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/47175/1
diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c
index 344f5f4..3d1e5a9 100644
--- a/src/ec/google/chromeec/ec_acpi.c
+++ b/src/ec/google/chromeec/ec_acpi.c
@@ -141,7 +141,7 @@
continue;
if (!config->mux_conn[i])
- printk(BIOS_ERR, "ERROR: Mux connector info missing for Type-C port "
+ printk(BIOS_INFO, "Mux connector info missing for Type-C port "
"#%d\n", i);
usb2_port = NULL;
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47247 )
Change subject: soc/intel/common/acpi: rename PEPD/LPI macros for clarification
......................................................................
Patch Set 2:
This change is ready for review.
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Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 )
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
......................................................................
Patch Set 9: Code-Review+2
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Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46842
to look at the new patch set (#9).
Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
......................................................................
soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
In gpio.c file, we have community group array for each comm,
representing gpio groups within that community. Like there might be
group H,D, VGPIO and C within community 1. Community also may have
some reserved gpio and we also define those in an array which indicates
OS can't use those GPIO (through PAD_BASE_NONE)
Now when we define reserved pads in the middle of actual community
pads, it creates an issue while calculating an offset for GPIO
host own pad register. This is because function actually checks
current gpio index (lets say vgpio_39 in our case) and tries to get
group index from an array which we have defined. If we have defined
reserved gpios in between 2 communities, index calculated will also
account for reserved GPIO and register offset calculation will move
to next set of register (offset 0xC instead of offset 0x8).
Because of this coreboot won't configure HOST_OWN_PAD register correctly
and driver will not be able to get non-SMI interrupts for related gpio.
Align pad group as per EDS and pin-ctrl driver in linux kernel.
Reference: DOC#618876 (EDS volume 2)
BUG=None
BRANCH=None
TEST=VGPIO community index is correctly calculated. Drawlat board
boots fine with this change and warm reset also works.
Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
---
M src/soc/intel/jasperlake/gpio.c
1 file changed, 11 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/9
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Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23002 )
Change subject: mainboard/asus/am1i-a: add support for board ASUS AM1I-A
......................................................................
Patch Set 9:
How did you figured out these IRQ tables? Really need your help at CB:46587
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 )
Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/…
File src/soc/intel/common/acpi/lpit.asl:
https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/…
PS1, Line 26: debugging
> That doesn't explain why you want to say that here in a comment. The […]
Done
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47246 )
Change subject: soc/intel/common/acpi: drop the southridge scope around PEPD
......................................................................
Patch Set 2:
This change is ready for review.
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