coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Matt DeVillier, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Nico Huber, Christian Walter, Tim Wawrzynczak, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47138 to look at the new patch set (#6). Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards Windows does not comply with the Low Power Idle S0 specification and crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does not return at least one device constraint, even when function 1 is announced as being not available by the enum function. Returning an empty package does not work. At least the following Windows versions were verified to be affected: - Windows 8.1 x64, release 6.3.9600 - Windoes 10 x64, version 1809, build 17763.379 - Windows 10 x64, version 1903, build 18362.53 - Windows 10 x64, version 2004, build 19041.508 - Windows 10 x64, version 20H2 / 2009, build 19042.450 To make Windows work on S0ix-enabled boards, return a dummy constraint package with a disabled dummy device. Since the device constraints are only used for debugging low power states in Linux and probably also in Windows, there shouldn't be any negative effect to S0ix. Real device constraint entries could be added at a later point, if needed. Note: to fully prevent the BSOD mentioned above the LPIT table is required on Windows, too. The patch for this is WIP, see CB:32350. If you want to test this, you need to applie the whole ACPI patch series including the hacky LPIT test implementation from CB:47242: https://review.coreboot.org/q/topic:%22low_power_idle_fix%22 Test: no bluescreen anymore on Clevo L140CU on all Windows versions listed above and S0ix gets detected in `powercfg -a`. Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/acpi/lpit.asl 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47138/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 5: Added a note for testing in the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Nov 2020 13:31:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Matt DeVillier, Paul Menzel, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Nico Huber, Christian Walter, Tim Wawrzynczak, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47138 to look at the new patch set (#5). Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards Windows does not comply with the Low Power Idle S0 specification and crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does not return at least one device constraint, even when function 1 is announced as being not available by the enum function. Returning an empty package does not work. At least the following Windows versions were verified to be affected: - Windows 8.1 x64, release 6.3.9600 - Windoes 10 x64, version 1809, build 17763.379 - Windows 10 x64, version 1903, build 18362.53 - Windows 10 x64, version 2004, build 19041.508 - Windows 10 x64, version 20H2 / 2009, build 19042.450 To make Windows work on S0ix-enabled boards, return a dummy constraint package with a disabled dummy device. Since the device constraints are only used for debugging low power states in Linux and probably also in Windows, there shouldn't be any negative effect to S0ix. Real device constraint entries could be added at a later point, if needed. Note: to fully prevent the BSOD mentioned above the LPIT table is required on Windows, too. The patch for this is WIP, see CB:32350. If you want to test this, first apply the hacky test implementation from CB:47242, then apply the whole ACPI patch series: https://review.coreboot.org/q/topic:%22low_power_idle_fix%22 Test: no bluescreen anymore on Clevo L140CU on all Windows versions listed above and S0ix gets detected in `powercfg -a`. Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/acpi/lpit.asl 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47138/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 5 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/arch/x86:Add support for low power idle table
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32350 ) Change subject: src/arch/x86:Add support for low power idle table ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/c/coreboot/+/32350/4/src/arch/x86/acpi.c@1253 PS4, Line 1253: __weak void soc_residency_counter(struct acpi_lpit_native *lpit_native) > I guess we can keep it in file src/soc/intel/common/block/acpi/acpi. […] We can also have the generic code in src/acpi/acpi.c btw. see CB:47242 for my hacky test implementation. Then for now we can have the table in soc/intel/common until some SoC gets released that differs -- To view, visit https://review.coreboot.org/c/coreboot/+/32350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie76ab0d50f09c98762bc674c2758520d53789137 Gerrit-Change-Number: 32350 Gerrit-PatchSet: 4 Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 13:27:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shaunak Saha <shaunak.saha(a)intel.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 05 Nov '20

05 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 4: Code-Review-1 need to block this again, since there are still BSOD reports, even though I can't reproduce them, yet (even not with the same windows version...) -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 05 Nov 2020 13:00:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_mini: Drop DW0/DW1 from GPIO config comments
by Matt DeVillier (Code Review) 05 Nov '20

05 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47200 ) Change subject: mb/purism/librem_mini: Drop DW0/DW1 from GPIO config comments ...................................................................... mb/purism/librem_mini: Drop DW0/DW1 from GPIO config comments These were generated by an earlier version of intelp2m and then adjusted by hand, and are in many cases incorrect and do not reflect the DW values reported by inteltool from the stock AMI firmware. Change-Id: Ie337cca5bc0e87a5426cceae8d7ec29ab14a1729 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c 1 file changed, 0 insertions(+), 188 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/47200/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 04c8614..e0661b3 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -8,771 +8,583 @@ /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* GPP_A1 - LAD0 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* GPP_A2 - LAD1 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* GPP_A3 - LAD2 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* GPP_A4 - LAD3 */ - /* DW0: 0x44000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* GPP_A5 - LFRAME# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* GPP_A6 - SERIRQ */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A7, 0, DEEP), /* GPP_A8 - CLKRUN# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* GPP_A9 - CLKOUT_LPC0 */ - /* DW0: 0x44000700, DW1: 0x00001000 */ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* GPP_A10 - CLKOUT_LPC1 */ - /* DW0: 0x44000700, DW1: 0x00001000 */ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* GPP_A11 - GPIO */ - /* DW0: 0x80880201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPP_A12 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A12, 1, PLTRST), /* GPP_A13 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A13, 1, PLTRST), /* GPP_A14 - SUS_STAT# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* GPP_A15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A15, 1, PLTRST), /* GPP_A16 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST), /* GPP_A17 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A17, 1, PLTRST), /* GPP_A18 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A18, UP_20K), /* GPP_A19 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A19, UP_20K), /* GPP_A20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A20, UP_20K), /* GPP_A21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A21, UP_20K), /* GPP_A22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A22, UP_20K), /* GPP_A23 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_A23, UP_20K), /* ------- GPIO Group GPP_B ------- */ /* GPP_B0 - Reserved */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* GPP_B1 - Reserved */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* GPP_B2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B2, 1, PLTRST), /* GPP_B3 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B3, 1, PLTRST), /* GPP_B4 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* GPP_B5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B5, NONE), /* GPP_B6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B6, NONE), /* GPP_B7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B7, NONE), /* GPP_B8 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B8, NONE), /* GPP_B9 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B9, NONE), /* GPP_B10 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_B10, NONE), /* GPP_B11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B11, 1, PLTRST), /* GPP_B12 - SLP_S0# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 - PLTRST# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), /* GPP_B15 - GSPI0_CS0# */ - /* DW0: 0x00000701, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1), /* GPP_B16 - GSPI0_CLK */ - /* DW0: 0x84000601, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), /* GPP_B17 - GSPI0_MISO */ - /* DW0: 0x44000502, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* GPP_B18 - GSPI0_MOSI */ - /* DW0: 0x84000601, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1), /* GPP_B19 - GSPI1_CS0# */ - /* DW0: 0x84000400, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1), /* GPP_B20 - GSPI1_CLK */ - /* DW0: 0x84000400, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1), /* GPP_B21 - GSPI1_MISO */ - /* DW0: 0x84000402, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1), /* GPP_B22 - GSPI1_MOSI */ - /* DW0: 0x84000400, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1), /* GPP_B23 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* ------- GPIO Group GPP_G ------- */ /* GPP_G0 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00001000 */ PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK), /* GPP_G1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G1, NONE), /* GPP_G2 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G2, NONE), /* GPP_G3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G3, NONE), /* GPP_G4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G4, NONE), /* GPP_G5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_G5, UP_20K), /* GPP_G6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_G6, NONE), /* GPP_G7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00001000 */ PAD_NC(GPP_G7, DN_20K), /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D0, NONE), /* GPP_D1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D1, NONE), /* GPP_D2 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D2, NONE), /* GPP_D3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D3, NONE), /* GPP_D4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D4, NONE), /* GPP_D5 - ISH_I2C0_SDA */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* GPP_D6 - ISH_I2C0_SCL */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* GPP_D7 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D7, 1, PLTRST), /* GPP_D8 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D8, 0, PLTRST), /* GPP_D9 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D9, 1, PLTRST), /* GPP_D10 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D10, 1, PLTRST), /* GPP_D11 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP), /* GPP_D12 - GPIO */ - /* DW0: 0x42100102, DW1: 0x00003000 */ PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), /* GPP_D13 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D13, 1, RSMRST), /* GPP_D14 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* GPP_D15 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D15, 1, DEEP), /* GPP_D16 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D16, 0, RSMRST), /* GPP_D17 - DMIC_CLK1 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* GPP_D18 - DMIC_DATA1 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* GPP_D19 - DMIC_CLK0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* GPP_D20 - DMIC_DATA0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* GPP_D21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D21, NONE), /* GPP_D22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D22, NONE), /* GPP_D23 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_D23, NONE), /* ------- GPIO Group GPP_F ------- */ /* GPP_F0 - GPIO */ - /* DW0: 0x00000301, DW1: 0x00000000 */ PAD_NC(GPP_F0, NONE), /* GPP_F1 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_F1, 0, RSMRST), /* GPP_F2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), /* GPP_F3 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), /* GPP_F4 - CNV_BRI_DT */ - /* DW0: 0x44000700, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1), /* GPP_F5 - CNV_BRI_RSP */ - /* DW0: 0x44000702, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1), /* GPP_F6 - CNV_RGI_DT */ - /* DW0: 0x44000700, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), /* GPP_F7 - CNV_RGI_RSP */ - /* DW0: 0x44000702, DW1: 0x00003000 */ PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1), /* GPP_F8 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F8, NONE), /* GPP_F9 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F9, NONE), /* GPP_F10 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* GPP_F11 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F11, NONE), /* GPP_F12 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F12, NONE), /* GPP_F13 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F13, NONE), /* GPP_F14 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F14, NONE), /* GPP_F15 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F15, NONE), /* GPP_F16 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F16, NONE), /* GPP_F17 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F17, NONE), /* GPP_F18 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F18, NONE), /* GPP_F19 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F19, NONE), /* GPP_F20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F20, NONE), /* GPP_F21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F21, NONE), /* GPP_F22 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_F22, NONE), /* GPP_F23 - A4WP_PRESENT */ - /* DW0: 0x44000700, DW1: 0x00001000 */ PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1), /* ------- GPIO Group GPP_H ------- */ /* GPP_H0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_H0, UP_20K), /* GPP_H1 - CNV_RF_RESET# */ - /* DW0: 0x44000f00, DW1: 0x00003000 */ PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3), /* GPP_H2 - MODEM_CLKREQ */ - /* DW0: 0x44000f00, DW1: 0x00003000 */ PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3), /* GPP_H3 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00003000 */ PAD_NC(GPP_H3, UP_20K), /* GPP_H4 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_H4, NONE), /* GPP_H5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_H5, NONE), /* GPP_H6 - I2C3_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* GPP_H7 - I2C3_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* GPP_H8 - I2C4_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* GPP_H9 - I2C4_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* GPP_H10 - I2C5_SDA */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1), /* GPP_H11 - I2C5_SCL */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1), /* GPP_H12 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H12, 1, PLTRST), /* GPP_H13 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPP_H14 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* GPP_H15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPP_H16 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H16, 1, RSMRST), /* GPP_H17 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H17, 1, RSMRST), /* GPP_H18 - CPU_C10_GATE# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* GPP_H19 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPP_H20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H21, 0, DEEP), /* GPP_H22 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H22, 1, PLTRST), /* GPP_H23 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H23, 0, DEEP), /* ------- GPIO Group GPD ------- */ /* GPD0 - BATLOW# */ - /* DW0: 0x04000702, DW1: 0x00000000 */ PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), /* GPD1 - ACPRESENT */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), /* GPD2 - LAN_WAKE# */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), /* GPD3 - PRWBTN# */ - /* DW0: 0x04000702, DW1: 0x00003000 */ PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), /* GPD4 - SLP_S3# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), /* GPD5 - SLP_S4# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), /* GPD6 - SLP_A# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), /* GPD7 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPD7, 0, RSMRST), /* GPD8 - SUSCLK */ - /* DW0: 0x04000700, DW1: 0x00000000 */ PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), /* GPD9 - SLP_WLAN# */ - /* DW0: 0x04000700, DW1: 0x00000000 */ PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), /* GPD10 - SLP_S5# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), /* GPD11 - LANPHYPC */ - /* DW0: 0x04000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* GPP_C1 - SMBDATA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* GPP_C2 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C2, 1, DEEP), /* GPP_C3 - SML0CLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* GPP_C4 - SML0DATA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* GPP_C5 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C5, 1, PLTRST), /* GPP_C6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C6, NONE), /* GPP_C7 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C7, NONE), /* GPP_C8 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C8, 1, PLTRST), /* GPP_C9 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C9, 1, PLTRST), /* GPP_C10 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPP_C11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C11, 1, PLTRST), /* GPP_C12 - UART1_RXD */ - /* DW0: 0x84000603, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1), /* GPP_C13 - UART1_TXD */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* GPP_C14 - UART1_RTS# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* GPP_C15 - UART1_CTS# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* GPP_C16 - I2C0_SDA */ - /* DW0: 0x84000402, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1), /* GPP_C17 - I2C0_SCL */ - /* DW0: 0x84000402, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1), /* GPP_C18 - I2C1_SDA */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* GPP_C19 - I2C1_SCL */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* GPP_C20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C20, NONE), /* GPP_C21 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_C21, NONE), /* GPP_C22 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_C22, 1, PLTRST), /* GPP_C23 - GPIO */ - /* DW0: 0x40100102, DW1: 0x00001000 */ PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE), /* ------- GPIO Group GPP_E ------- */ /* GPP_E0 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E0, NONE), /* GPP_E1 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E1, NONE), /* GPP_E2 - SATAXPCIE2 */ - /* DW0: 0x84000502, DW1: 0x00003000 */ PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1), /* GPP_E3 - GPIO */ - /* DW0: 0x82040102, DW1: 0x00000000 */ PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), /* GPP_E4 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_E4, 1, PLTRST), /* GPP_E5 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E5, NONE), /* GPP_E6 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ PAD_NC(GPP_E6, NONE), /* GPP_E7 - GPIO */ - /* DW0: 0x82000102, DW1: 0x00000000 */ PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI), /* GPP_E8 - SATALED# */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* GPP_E9 - RESERVED */ - /* DW0: 0x44001700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5), /* GPP_E10 - RESERVED */ - /* DW0: 0x44001700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5), /* GPP_E11 - USB2_OC2# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* GPP_E12 - USB2_OC3# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* GPP_E13 - DDPB_HPD0 */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* GPP_E14 - DDPC_HPD1 */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* GPP_E15 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_E15, 1, PLTRST), /* GPP_E16 - GPIO */ - /* DW0: 0x80880102, DW1: 0x00003000 */ PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT), /* GPP_E17 - EDP_HPD */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* GPP_E18 - DPPB_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* GPP_E19 - DPPB_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* GPP_E20 - DPPC_CTRLCLK */ - /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* GPP_E21 - DPPC_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22 - DPPD_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* GPP_E23 - DPPD_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47200 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie337cca5bc0e87a5426cceae8d7ec29ab14a1729 Gerrit-Change-Number: 47200 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/gigabyte: Add GA-D510UD
by Arthur Heymans (Code Review) 05 Nov '20

05 Nov '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40465 ) Change subject: mb/gigabyte: Add GA-D510UD ...................................................................... Patch Set 6: Code-Review+2 (1 comment) The code looks good. LGTM https://review.coreboot.org/c/coreboot/+/40465/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40465/6//COMMIT_MSG@11 PS6, Line 11: M > The one thing that doesn't work is the 2nd DIMM slot. […] I remember that the raminit is somewhat picky (when there are 2 DIMMs). -- To view, visit https://review.coreboot.org/c/coreboot/+/40465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Gerrit-Change-Number: 40465 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Nov 2020 11:18:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Angel Pons (Code Review) 05 Nov '20

05 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 3: > Patch Set 3: > > Tim/Angel, Good to merge this CL? Sounds good to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 11:14:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Subrata Banik (Code Review) 05 Nov '20

05 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 3: Tim/Angel, Good to merge this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 11:04:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/gigabyte: Add GA-D510UD
by Angel Pons (Code Review) 05 Nov '20

05 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40465 ) Change subject: mb/gigabyte: Add GA-D510UD ...................................................................... Patch Set 6: (2 comments) https://review.coreboot.org/c/coreboot/+/40465/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40465/6//COMMIT_MSG@11 PS6, Line 11: M > What does not work, or is untested yet? The one thing that doesn't work is the 2nd DIMM slot. The rest I think is working, but I'd like to re-check. https://review.coreboot.org/c/coreboot/+/40465/6/src/mainboard/gigabyte/ga-… File src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/40465/6/src/mainboard/gigabyte/ga-… PS6, Line 1: > Remove file? Can't remove it, southbridge ASL always tries to include this file... -- To view, visit https://review.coreboot.org/c/coreboot/+/40465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Gerrit-Change-Number: 40465 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Nov 2020 10:24:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2020