coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3242 discussions

Change in coreboot[master]: mb/gigabyte: Add GA-D510UD
by Christian Walter (Code Review) 05 Nov '20

05 Nov '20

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40465 ) Change subject: mb/gigabyte: Add GA-D510UD ...................................................................... Patch Set 6: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/40465/6//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40465/6//COMMIT_MSG@11 PS6, Line 11: M What does not work, or is untested yet? https://review.coreboot.org/c/coreboot/+/40465/6/src/mainboard/gigabyte/ga-… File src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl: https://review.coreboot.org/c/coreboot/+/40465/6/src/mainboard/gigabyte/ga-… PS6, Line 1: Remove file? -- To view, visit https://review.coreboot.org/c/coreboot/+/40465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Gerrit-Change-Number: 40465 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Nov 2020 10:22:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/gigabyte: Add GA-D510UD
by Angel Pons (Code Review) 05 Nov '20

05 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40465 to look at the new patch set (#6). Change subject: mb/gigabyte: Add GA-D510UD ...................................................................... mb/gigabyte: Add GA-D510UD I call this the Pineview potato. Booted fine on the first try. Most things work properly, but I haven't tested them thoroughly. Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/gigabyte/ga-d510ud/Kconfig A src/mainboard/gigabyte/ga-d510ud/Kconfig.name A src/mainboard/gigabyte/ga-d510ud/Makefile.inc A src/mainboard/gigabyte/ga-d510ud/acpi/ec.asl A src/mainboard/gigabyte/ga-d510ud/acpi/ich7_pci_irqs.asl A src/mainboard/gigabyte/ga-d510ud/acpi/superio.asl A src/mainboard/gigabyte/ga-d510ud/acpi_tables.c A src/mainboard/gigabyte/ga-d510ud/board_info.txt A src/mainboard/gigabyte/ga-d510ud/cmos.default A src/mainboard/gigabyte/ga-d510ud/cmos.layout A src/mainboard/gigabyte/ga-d510ud/cstates.c A src/mainboard/gigabyte/ga-d510ud/data.vbt A src/mainboard/gigabyte/ga-d510ud/devicetree.cb A src/mainboard/gigabyte/ga-d510ud/dsdt.asl A src/mainboard/gigabyte/ga-d510ud/early_init.c A src/mainboard/gigabyte/ga-d510ud/gpio.c A src/mainboard/gigabyte/ga-d510ud/hda_verb.c 17 files changed, 493 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/40465/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/40465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4 Gerrit-Change-Number: 40465 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in em100[master]: Add install and uninstall targets to Makefile
by Stefan Reinauer (Code Review) 05 Nov '20

05 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/46927 ) Change subject: Add install and uninstall targets to Makefile ...................................................................... Add install and uninstall targets to Makefile - Will install em100 to /usr/local/bin - Will install udev rule to /etc/udev/rules.d Assumes that there is a plugdev group (some systems may not have it) Signed-off-by: Alexander Amelkin <a.amelkin(a)yadro.com> Change-Id: Ibfcd6f9f2f577b1f7d8d2d4b0a89405d38264d3d --- M Makefile 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/27/46927/1 diff --git a/Makefile b/Makefile index a5b8c33..14c928e 100644 --- a/Makefile +++ b/Makefile @@ -71,6 +71,14 @@ distclean: clean rm -f em100pro_chips.h +install: em100 60-dediprog-em100pro.rules + install -m 644 60-dediprog-em100pro.rules /etc/udev/rules.d/ + install -s -m 750 -g plugdev em100 /usr/local/bin/ + +uninstall: /usr/local/bin/em100 + rm -f /etc/udev/rules.d/60-dediprog-em100pro.rules + rm -f /usr/local/bin/em100 + -include .dependencies .PHONY: clean distclean tarballs -- To view, visit https://review.coreboot.org/c/em100/+/46927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Ibfcd6f9f2f577b1f7d8d2d4b0a89405d38264d3d Gerrit-Change-Number: 46927 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 10

Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Maulik V Vaghela (Code Review) 05 Nov '20

05 Nov '20

Hello build bot (Jenkins), Furquan Shaikh, Subrata Banik, Ronak Kanabar, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46842 to look at the new patch set (#8). Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... soc/intel/jasperlake: Correct GPIO pad sequence for community pad group In gpio.c file, we have community group array for each comm, representing gpio groups within that community. Like there might be group H,D, VGPIO and C within community 1. Community also may have some reserved gpio and we also define those in an array which indicates OS can't use those GPIO (through PAD_BASE_NONE) Now when we define reserved pads in the middle of actual community pads, it creates an issue while calculating an offset for GPIO host own pad register. This is because function actually checks current gpio index (lets say vgpio_39 in our case) and tries to get group index from an array which we have defined. If we have defined reserved gpios in between 2 communities, index calculated will also account for reserved GPIO and register offset calculation will move to next set of register (offset 0xC instead of offset 0x8). Because of this coreboot won't configure HOST_OWN_PAD register correctly and driver will not be able to get non-SMI interrupts for related gpio. Align pad group as per EDS and pin-ctrl driver in linux kernel. Reference: DOC#618876 (EDS volume 2) BUG=None BRANCH=None TEST=VGPIO community index is correctly calculated. Drawlat board boots fine with this change and warm reset also works. Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/gpio.c 1 file changed, 14 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/46842/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 8 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/intel/adlrvp: Add support for DDR5 memory
by Subrata Banik (Code Review) 05 Nov '20

05 Nov '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46485 ) Change subject: mb/intel/adlrvp: Add support for DDR5 memory ...................................................................... mb/intel/adlrvp: Add support for DDR5 memory This patch adds DDR5 memory configuration parameters to FSP. TEST=Able to build and boot ADLRVP with DDR5 memory. Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c M src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h 3 files changed, 21 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 209ee6a..672c597 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -36,7 +36,7 @@ .spd_spec.spd_index = get_spd_index(), }; - const struct spd_info ddr4_spd_info = { + const struct spd_info ddr4_ddr5_spd_info = { .read_type = READ_SMBUS, .spd_spec = { .spd_smbus_address = { @@ -51,7 +51,8 @@ switch (board_id) { case ADL_P_DDR4_1: case ADL_P_DDR4_2: - memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated); + case ADL_P_DDR5: + memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_ddr5_spd_info, half_populated); break; case ADL_P_LP4_1: case ADL_P_LP4_2: diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c index c730b99..ec7ae88 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c @@ -54,6 +54,20 @@ .UserBd = BOARD_TYPE_MOBILE, }; +static const struct mb_cfg ddr5_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {50, 30, 30, 30, 27}, + + .dq_pins_interleaved = true, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + const struct mb_cfg *variant_memory_params(void) { int board_id = get_board_id(); @@ -62,6 +76,8 @@ return &lpddr4_mem_config; else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) return &ddr4_mem_config; + else if (board_id == ADL_P_DDR5) + return &ddr5_mem_config; die("unsupported board id : 0x%x\n", board_id); } diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 005ec83..537e624 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -12,6 +12,8 @@ /* ADL-P LPDDR4 RVPs */ ADL_P_LP4_1 = 0x10, ADL_P_LP4_2 = 0x11, + /* ADL-P DDR5 RVPs */ + ADL_P_DDR5 = 0x12, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, -- To view, visit https://review.coreboot.org/c/coreboot/+/46485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Gerrit-Change-Number: 46485 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/volteer: Add boldar GPIO configuration
by Aamir Bohra (Code Review) 05 Nov '20

05 Nov '20

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46131 ) Change subject: mb/google/volteer: Add boldar GPIO configuration ...................................................................... mb/google/volteer: Add boldar GPIO configuration Change-Id: I214a615e8104c181c96c88dae6bd9278ed6250ab Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/mainboard/google/volteer/variants/boldar/Makefile.inc A src/mainboard/google/volteer/variants/boldar/gpio.c 2 files changed, 301 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/46131/1 diff --git a/src/mainboard/google/volteer/variants/boldar/Makefile.inc b/src/mainboard/google/volteer/variants/boldar/Makefile.inc new file mode 100644 index 0000000..13269db --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/Makefile.inc @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/boldar/gpio.c b/src/mainboard/google/volteer/variants/boldar/gpio.c new file mode 100644 index 0000000..f429adf --- /dev/null +++ b/src/mainboard/google/volteer/variants/boldar/gpio.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + + /* A5 : USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_A5, 1, DEEP), + /* A6 : USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_A6, 1, DEEP), + /* A8 : EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A8, NONE, DEEP), + /* A9 : ESPI_CLK */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : ESPI_RST_L */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A16 : USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A23, 1, DEEP), + + /* B3 : PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + /* B7 : ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + /* B8 : ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + /* B9 : NC */ + PAD_NC(GPP_B9, UP_20K), + /* B10 : NC */ + PAD_NC(GPP_B10, UP_20K), + /* B15 : FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, LEVEL), + /* B16 : PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + /* B17 : PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* B18 : EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), + /* B19 : NC */ + PAD_NC(GPP_B19, UP_20K), + /* B20 : NC */ + PAD_NC(GPP_B20, UP_20K), + /* B21 : NC */ + PAD_NC(GPP_B21, UP_20K), + /* B22 : NC */ + PAD_NC(GPP_B22, UP_20K), + + /* C0 : EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : USI_RST_L */ + PAD_CFG_GPO(GPP_C1, 0, DEEP), + /* C3 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT) + /* C4 : EN_PP5000_PEN */ + PAD_CFG_GPO(GPP_C4, 1, DEEP), + /* C7 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + + /* D0 : SSD_RTD3_EN */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D1 : ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D6 : WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D8 : SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_D9, NONE, DEEP), + /* D10 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), + /* D11 : PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_D11, NONE, DEEP), + /* D12 : PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_D12, 0, DEEP) + /* D13 : UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + /* D17 : EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + /* D18 : FCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_D18, 0, DEEP), + + /* E1 : PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 0, DEEP), + /* E7 : USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E8 : SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + + /* E10 : PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + /* E15 : TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E16 : WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + + /* F6 : WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_F6, NONE, DEEP), + /* A7 : EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F7, 1, DEEP), + /* F9 : HP_INT_L */ + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH), + /* F10 : EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + /* F11 : PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + /* F12 : PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + /* F13 : PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + /* F14 : WLAN_RST_ODL */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F15 : RCAM_RST_L */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* F16 : PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : WWAN_RST_ODL */ + PAD_CFG_GPI(GPP_F20, NONE, DEEP), + /* F21 : WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + + /* H3 : SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : PCH_I2C0_MISC_SCL */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : PCH_I2C0_MISC_SDA */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : PCH_I2C1_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : PCH_I2C1_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + /* H11 : UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + /* H12 : WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H14 : RCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_H13, 0, DEEP), + /* H15 : DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* H17 : DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : USB_C1_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H19, 1, DEEP), + /* H20 : EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* H21 : CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* R0 : I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : DMIC_CLK0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : DMIC_DATA0 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1), + /* R7 : SAR0_INT_L */ + PAD_CFG_GPI_APIC(GPP_R7, NONE, PLTRST, LEVEL, NONE), + + /* S0 : I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF2), + /* S1 : I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF2), + /* S2 : I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF3), + /* S3 : I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF3), + /* S5 : SPKR_INT_L */ + PAD_CFG_GPI_APIC(GPP_S5, NONE, PLTRST, LEVEL, NONE), + /* S6 : DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S7 : DMIC_DATA1 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD9: SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + /* A7 : MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_A7, NONE, DEEP), + /* A12 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A19 : MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_A19, NONE, DEEP), + /* A20 : MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_A20, NONE, DEEP), + + /* B11 : PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* C0 : EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C1, NONE, PLTRST, LEVEL, INVERT), + + /* D10 : EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_D10, 1, DEEP), + /* D12 : PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_D12, 0, DEEP), + /* D15 : MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : EN_PP3300_SD */ + PAD_NC(GPP_D16, UP_20K), + + /* E10 : PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + /* E12 : PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + + /* F14 : WLAN_PERST_L */ + PAD_CFG_GPO(GPP_F14, 1, DEEP), + /* F20 : WWAN_RST_ODL + To meet timing constrains - drive reset low. + Deasserted in ramstage. */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I214a615e8104c181c96c88dae6bd9278ed6250ab Gerrit-Change-Number: 46131 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

5 25

Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Maulik V Vaghela (Code Review) 05 Nov '20

05 Nov '20

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46842/7/src/soc/intel/jasperlake/i… File src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h: PS7: > Maulik - can you please push the renaming of GPIOs as a separate CL? I think it will keep the change […] Ack Sure Furquan..Let me push one more base patch with renames of GPIO -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Nov 2020 06:37:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group
by Furquan Shaikh (Code Review) 05 Nov '20

05 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46842 ) Change subject: soc/intel/jasperlake: Correct GPIO pad sequence for community pad group ...................................................................... Patch Set 7: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/46842/7/src/soc/intel/jasperlake/i… File src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h: https://review.coreboot.org/c/coreboot/+/46842/7/src/soc/intel/jasperlake/i… PS7, Line 306: #define GPIO_RSVD_24 240 : #define GPIO_RSVD_25 241 : #define GPIO_RSVD_26 242 : #define GPIO_RSVD_27 243 : #define GPIO_RSVD_28 244 : #define GPIO_RSVD_29 245 : #define GPIO_RSVD_30 246 : #define GPIO_RSVD_31 247 : #define GPIO_RSVD_32 248 : #define GPIO_RSVD_33 249 : #define GPIO_RSVD_34 250 : #define GPIO_RSVD_35 251 : #define GPIO_RSVD_36 252 > Since these are the reserved at the end of the community, It won't impact the offset calculation wit […] SG. PS7: Maulik - can you please push the renaming of GPIOs as a separate CL? I think it will keep the changes cleaner and easier for anyone to read/review as well. Patch 1 - Reorganize the pad groups in the communities in gpio.c Patch 2 - Rename the reserved GPIOs to use actual names and drop the ones you are currently done in COM4. -- To view, visit https://review.coreboot.org/c/coreboot/+/46842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id6013914c88c50f4b8c60ca9a9285a8e1b214d11 Gerrit-Change-Number: 46842 Gerrit-PatchSet: 7 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 05 Nov 2020 06:10:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Sumeet R Pawnikar (Code Review) 05 Nov '20

05 Nov '20

Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 ) Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 95: 65 > Yes that is correct. I could have moved the difference into a . […] Thanks for this info. https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden : register "options.tsr[0].desc" = ""Memory"" : register "options.tsr[1].desc" = ""Ambient"" : register "options.tsr[2].desc" = ""Charger"" : register "options.tsr[3].desc" = ""5V regulator"" > I may be wrong, but I am not aware of any such option. […] Tim, do you have any suggestion here ? Please, let's know. This TSR1 trip value depends on tuning as per current on-going discussion with ODM on b:169691800 -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 06:09:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Karthik Ramasubramanian (Code Review) 05 Nov '20

05 Nov '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 ) Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… File src/mainboard/google/dedede/variants/drawcia/overridetree.cb: https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 95: 65 > After comparison of existing and these new added entries, observed that only this temperature trip v […] Yes that is correct. I could have moved the difference into a .C file to override only that passive policy. But I am afraid, developers may not notice it and that will lead to more confusion. Hence added it in the device tree so that it will be more clear. https://review.coreboot.org/c/coreboot/+/47010/5/src/mainboard/google/deded… PS5, Line 139: # Default DPTF Policy for all drawcia boards if not overridden : register "options.tsr[0].desc" = ""Memory"" : register "options.tsr[1].desc" = ""Ambient"" : register "options.tsr[2].desc" = ""Charger"" : register "options.tsr[3].desc" = ""5V regulator"" > Is it possible to define these sensor description entries only once, instead of keeping for both the […] I may be wrong, but I am not aware of any such option. Do you see any issue moving the TSR1 trip value to 65 for the devices of all form factors. If so, then I am fine with moving to that value. That way we don't have to duplicate the common entries. -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 05 Nov 2020 05:45:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020