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Change in coreboot[master]: soc/intel/broadwell/pch: Use common PCIe ACPI code
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46763 ) Change subject: soc/intel/broadwell/pch: Use common PCIe ACPI code ...................................................................... soc/intel/broadwell/pch: Use common PCIe ACPI code Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/pch.asl D src/soc/intel/broadwell/pch/acpi/pcie.asl D src/soc/intel/broadwell/pch/acpi/pcie_port.asl 3 files changed, 1 insertion(+), 214 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/46763/1 diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 5a94bca..7b57859 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -45,7 +45,7 @@ #include "adsp.asl" // PCI Express Ports 0:1c.x -#include "pcie.asl" +#include <southbridge/intel/common/acpi/pcie.asl> // USB EHCI 0:1d.0 #include "ehci.asl" diff --git a/src/soc/intel/broadwell/pch/acpi/pcie.asl b/src/soc/intel/broadwell/pch/acpi/pcie.asl deleted file mode 100644 index 72993f93..0000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie.asl +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Intel PCH PCIe support */ - -Method (IRQM, 1, Serialized) { - - /* Interrupt Map INTA->INTA, INTB->INTB, INTC->INTC, INTD->INTD */ - Name (IQAA, Package() { - Package() { 0x0000ffff, 0, 0, 16 }, - Package() { 0x0000ffff, 1, 0, 17 }, - Package() { 0x0000ffff, 2, 0, 18 }, - Package() { 0x0000ffff, 3, 0, 19 } }) - Name (IQAP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 } }) - - /* Interrupt Map INTA->INTB, INTB->INTC, INTC->INTD, INTD->INTA */ - Name (IQBA, Package() { - Package() { 0x0000ffff, 0, 0, 17 }, - Package() { 0x0000ffff, 1, 0, 18 }, - Package() { 0x0000ffff, 2, 0, 19 }, - Package() { 0x0000ffff, 3, 0, 16 } }) - Name (IQBP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 } }) - - /* Interrupt Map INTA->INTC, INTB->INTD, INTC->INTA, INTD->INTB */ - Name (IQCA, Package() { - Package() { 0x0000ffff, 0, 0, 18 }, - Package() { 0x0000ffff, 1, 0, 19 }, - Package() { 0x0000ffff, 2, 0, 16 }, - Package() { 0x0000ffff, 3, 0, 17 } }) - Name (IQCP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 } }) - - /* Interrupt Map INTA->INTD, INTB->INTA, INTC->INTB, INTD->INTC */ - Name (IQDA, Package() { - Package() { 0x0000ffff, 0, 0, 19 }, - Package() { 0x0000ffff, 1, 0, 16 }, - Package() { 0x0000ffff, 2, 0, 17 }, - Package() { 0x0000ffff, 3, 0, 18 } }) - Name (IQDP, Package() { - Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 } }) - - Switch (ToInteger (Arg0)) { - /* PCIe Root Port 1 and 5 */ - Case (Package() { 1, 5 }) { - If (PICM) { - Return (IQAA) - } Else { - Return (IQAP) - } - } - - /* PCIe Root Port 2 and 6 */ - Case (Package() { 2, 6 }) { - If (PICM) { - Return (IQBA) - } Else { - Return (IQBP) - } - } - - /* PCIe Root Port 3 and 7 */ - Case (Package() { 3, 7 }) { - If (PICM) { - Return (IQCA) - } Else { - Return (IQCP) - } - } - - /* PCIe Root Port 4 and 8 */ - Case (Package() { 4, 8 }) { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - - Default { - If (PICM) { - Return (IQDA) - } Else { - Return (IQDP) - } - } - } -} - -Device (RP01) -{ - Name (_ADR, 0x001c0000) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP02) -{ - Name (_ADR, 0x001c0001) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP03) -{ - Name (_ADR, 0x001c0002) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP04) -{ - Name (_ADR, 0x001c0003) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP05) -{ - Name (_ADR, 0x001c0004) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP06) -{ - Name (_ADR, 0x001c0005) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP07) -{ - Name (_ADR, 0x001c0006) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} - -Device (RP08) -{ - Name (_ADR, 0x001c0007) - - #include "pcie_port.asl" - - Method (_PRT) - { - Return (IRQM (RPPN)) - } -} diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl deleted file mode 100644 index 988c817..0000000 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Included in each PCIe Root Port device */ - -OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) -Field (RPCS, AnyAcc, NoLock, Preserve) -{ - Offset (0x4c), // Link Capabilities - , 24, - RPPN, 8, // Root Port Number - Offset (0x5A), - , 3, - PDC, 1, - Offset (0xDF), - , 6, - HPCS, 1, -} -- To view, visit https://review.coreboot.org/c/coreboot/+/46763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f41ce943e25dceab79c7d7ee2ed797c392dcd52 Gerrit-Change-Number: 46763 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/pch/acpi: Add PCIe register offsets
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46761 ) Change subject: soc/intel/broadwell/pch/acpi: Add PCIe register offsets ...................................................................... soc/intel/broadwell/pch/acpi: Add PCIe register offsets These are present in common southbridge ACPI code, and also exist on Broadwell. Thus, add the definitions to align with common ACPI code. Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/pcie_port.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46761/1 diff --git a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl index d48ecd0..988c817 100644 --- a/src/soc/intel/broadwell/pch/acpi/pcie_port.asl +++ b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl @@ -8,4 +8,10 @@ Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number + Offset (0x5A), + , 3, + PDC, 1, + Offset (0xDF), + , 6, + HPCS, 1, } -- To view, visit https://review.coreboot.org/c/coreboot/+/46761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Gerrit-Change-Number: 46761 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/broadwell/gma.c: Align struct with Haswell
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46732 ) Change subject: soc/intel/broadwell/gma.c: Align struct with Haswell ...................................................................... soc/intel/broadwell/gma.c: Align struct with Haswell Change-Id: Ifd1fb02497e1d326b6b9c5752f471f52b145a8ef Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/gma.c 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/46732/1 diff --git a/src/soc/intel/broadwell/gma.c b/src/soc/intel/broadwell/gma.c index 3889be3..d42eebc 100644 --- a/src/soc/intel/broadwell/gma.c +++ b/src/soc/intel/broadwell/gma.c @@ -588,12 +588,12 @@ } static struct device_operations igd_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &igd_init, - .ops_pci = &pci_dev_ops_pci, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = igd_init, .acpi_fill_ssdt = gma_generate_ssdt, + .ops_pci = &pci_dev_ops_pci, }; static const unsigned short pci_device_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/46732 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd1fb02497e1d326b6b9c5752f471f52b145a8ef Gerrit-Change-Number: 46732 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/common/acpi/pcie.asl: Generalise file comment
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46762 ) Change subject: sb/intel/common/acpi/pcie.asl: Generalise file comment ...................................................................... sb/intel/common/acpi/pcie.asl: Generalise file comment This file is no longer specific to 6 and 7 series PCHs. Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/acpi/pcie.asl 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46762/1 diff --git a/src/southbridge/intel/common/acpi/pcie.asl b/src/southbridge/intel/common/acpi/pcie.asl index 8f496d3..c1bfcfd 100644 --- a/src/southbridge/intel/common/acpi/pcie.asl +++ b/src/southbridge/intel/common/acpi/pcie.asl @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* Intel 6/7 Series PCH PCIe support */ - -// PCI Express Ports +/* Intel southbridge PCIe support */ Method (IRQM, 1, Serialized) { -- To view, visit https://review.coreboot.org/c/coreboot/+/46762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib89378bd6ba1d80281b92a79d37b9fdeaaed40fb Gerrit-Change-Number: 46762 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46760 ) Change subject: sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics ...................................................................... sb/intel/common/acpi/irqlinks.asl: Clean up cosmetics Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I8562fc3278144380b0ab842d88176114821be823 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/common/acpi/irqlinks.asl 1 file changed, 88 insertions(+), 88 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/46760/1 diff --git a/src/southbridge/intel/common/acpi/irqlinks.asl b/src/southbridge/intel/common/acpi/irqlinks.asl index 3f3386d..54c6989 100644 --- a/src/southbridge/intel/common/acpi/irqlinks.asl +++ b/src/southbridge/intel/common/acpi/irqlinks.asl @@ -8,13 +8,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -23,15 +23,15 @@ { Name (RTLA, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLA, 1, IRQ0) + CreateWordField (RTLA, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -39,19 +39,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,13 +67,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -82,15 +82,15 @@ { Name (RTLB, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLB, 1, IRQ0) + CreateWordField (RTLB, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f) Return (RTLB) } @@ -98,19 +98,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,13 +126,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -141,15 +141,15 @@ { Name (RTLC, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLC, 1, IRQ0) + CreateWordField (RTLC, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f) Return (RTLC) } @@ -157,19 +157,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,13 +185,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -200,15 +200,15 @@ { Name (RTLD, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLD, 1, IRQ0) + CreateWordField (RTLD, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f) Return (RTLD) } @@ -216,19 +216,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,13 +244,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -259,15 +259,15 @@ { Name (RTLE, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLE, 1, IRQ0) + CreateWordField (RTLE, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f) Return (RTLE) } @@ -275,19 +275,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,13 +303,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -318,15 +318,15 @@ { Name (RTLF, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLF, 1, IRQ0) + CreateWordField (RTLF, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f) Return (RTLF) } @@ -334,19 +334,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,13 +362,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -377,15 +377,15 @@ { Name (RTLG, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLG, 1, IRQ0) + CreateWordField (RTLG, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f) Return (RTLG) } @@ -393,19 +393,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,13 +421,13 @@ // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } // Possible Resource Settings for this Link Name (_PRS, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) + IRQ (Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) @@ -436,15 +436,15 @@ { Name (RTLH, ResourceTemplate() { - IRQ(Level, ActiveLow, Shared) {} + IRQ (Level, ActiveLow, Shared) {} }) - CreateWordField(RTLH, 1, IRQ0) + CreateWordField (RTLH, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f) Return (RTLH) } @@ -452,19 +452,19 @@ // Set Resource Setting for this IRQ link Method (_SRS, 1, Serialized) { - CreateWordField(Arg0, 1, IRQ0) + CreateWordField (Arg0, 1, IRQ0) // Which bit is set? - FindSetRightBit(IRQ0, Local0) + FindSetRightBit (IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) -- To view, visit https://review.coreboot.org/c/coreboot/+/46760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8562fc3278144380b0ab842d88176114821be823 Gerrit-Change-Number: 46760 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: soc/intel/broadwell: Use common irqlinks.asl
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46759 ) Change subject: soc/intel/broadwell: Use common irqlinks.asl ...................................................................... soc/intel/broadwell: Use common irqlinks.asl Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I9179c1b449925cc66628fc3266652b8237ab49e5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- D src/soc/intel/broadwell/pch/acpi/irqlinks.asl M src/soc/intel/broadwell/pch/acpi/lpc.asl 2 files changed, 1 insertion(+), 474 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/46759/1 diff --git a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl deleted file mode 100644 index 8a63ba5..0000000 --- a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl +++ /dev/null @@ -1,473 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device (LNKA) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 1) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTA) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLA, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLA, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTA - ShiftLeft (1, And (PRTA, 0x0f), IRQ0) - - Return (RTLA) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTA) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTA, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKB) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 2) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTB) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLB, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLB, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTB - ShiftLeft (1, And (PRTB, 0x0f), IRQ0) - - Return (RTLB) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTB) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTB, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKC) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 3) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTC) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLC, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLC, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTC - ShiftLeft (1, And (PRTC, 0x0f), IRQ0) - - Return (RTLC) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTC) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTC, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKD) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 4) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTD) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLD, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLD, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTD - ShiftLeft (1, And (PRTD, 0x0f), IRQ0) - - Return (RTLD) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTD) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTD, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKE) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 5) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTE) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLE, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLE, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTE - ShiftLeft (1, And (PRTE, 0x0f), IRQ0) - - Return (RTLE) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTE) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTE, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKF) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 6) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTF) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLF, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLF, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTF - ShiftLeft (1, And (PRTF, 0x0f), IRQ0) - - Return (RTLF) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTF) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTF, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKG) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 7) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTG) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLG, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLG, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTG - ShiftLeft (1, And (PRTG, 0x0f), IRQ0) - - Return (RTLG) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTG) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTG, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} - -Device (LNKH) -{ - Name (_HID, EISAID("PNP0C0F")) - Name (_UID, 8) - - // Disable method - Method (_DIS, 0, Serialized) - { - Store (0x80, PRTH) - } - - // Possible Resource Settings for this Link - Name (_PRS, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } - }) - - // Current Resource Settings for this link - Method (_CRS, 0, Serialized) - { - Name (RTLH, ResourceTemplate() - { - IRQ (Level, ActiveLow, Shared) {} - }) - CreateWordField (RTLH, 1, IRQ0) - - // Clear the WordField - Store (Zero, IRQ0) - - // Set the bit from PRTH - ShiftLeft (1, And (PRTH, 0x0f), IRQ0) - - Return (RTLH) - } - - // Set Resource Setting for this IRQ link - Method (_SRS, 1, Serialized) - { - CreateWordField (Arg0, 1, IRQ0) - - // Which bit is set? - FindSetRightBit (IRQ0, Local0) - - Decrement(Local0) - Store (Local0, PRTH) - } - - // Status - Method (_STA, 0, Serialized) - { - If(And (PRTH, 0x80)) { - Return (0x9) - } Else { - Return (0xb) - } - } -} diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl index 5bdfea2..f2abe6e 100644 --- a/src/soc/intel/broadwell/pch/acpi/lpc.asl +++ b/src/soc/intel/broadwell/pch/acpi/lpc.asl @@ -180,7 +180,7 @@ } #include "gpio.asl" - #include "irqlinks.asl" + #include <southbridge/intel/common/acpi/irqlinks.asl> #include <acpi/ec.asl> #include <acpi/superio.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/46759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9179c1b449925cc66628fc3266652b8237ab49e5 Gerrit-Change-Number: 46759 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46758 ) Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ...................................................................... soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs) added these IRQs for Lynx Point and earlier southbridges. Follow suit for Broadwell, since it also supports them. Vendor firmware of the Asus X555LAB laptop also contains these IRQs, as per the disassembled DSDT. Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/irqlinks.asl 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46758/1 diff --git a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl index 0661ff8..8a63ba5 100644 --- a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl @@ -15,7 +15,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -74,7 +74,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -133,7 +133,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -192,7 +192,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -251,7 +251,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -310,7 +310,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -369,7 +369,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link @@ -428,7 +428,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } }) // Current Resource Settings for this link -- To view, visit https://review.coreboot.org/c/coreboot/+/46758 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73 Gerrit-Change-Number: 46758 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46757 ) Change subject: soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint ...................................................................... soc/intel/broadwell: Align ACPI with Haswell/Lynxpoint Drop unnecessary smbus.asl in favor of southbridge common code. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 does not change. Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/acpi/ctdp.asl M src/soc/intel/broadwell/pch/acpi/pch.asl D src/soc/intel/broadwell/pch/acpi/smbus.asl 3 files changed, 40 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46757/1 diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl index 8391482..b18ec78 100644 --- a/src/soc/intel/broadwell/acpi/ctdp.asl +++ b/src/soc/intel/broadwell/acpi/ctdp.asl @@ -9,8 +9,7 @@ Name (CTCU, 2) /* CTDP Up Select */ Name (SPL1, 0) /* Saved PL1 value */ - OperationRegion (MCHB, SystemMemory, - Add (MCH_BASE_ADDRESS, 0x5000), 0x1000) + OperationRegion (MCHB, SystemMemory, MCH_BASE_ADDRESS + 0x5000, 0x1000) Field (MCHB, DWordAcc, Lock, Preserve) { Offset (0x930), /* PACKAGE_POWER_SKU */ @@ -51,7 +50,7 @@ } /* - * Search CPU0 _PSS looking for control=arg0 and then + * Search CPU0 _PSS looking for control = arg0 and then * return previous P-state entry number for new _PPC * * Format of _PSS: @@ -62,17 +61,16 @@ External (\_SB.CP00._PSS) Method (PSSS, 1, NotSerialized) { - Store (One, Local0) /* Start at P1 */ - Store (SizeOf (\_SB.CP00._PSS), Local1) + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) - While (LLess (Local0, Local1)) { + While (Local0 < Local1) { /* Store _PSS entry Control value to Local2 */ - ShiftRight (DeRefOf (Index (DeRefOf (Index - (\_SB.CP00._PSS, Local0)), 4)), 8, Local2) - If (LEqual (Local2, Arg0)) { - Return (Subtract (Local0, 1)) + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) } - Increment (Local0) + Local0++ } Return (0) @@ -83,7 +81,7 @@ { /* Haswell ULT PL2 = 25W */ /* FIXME: update for broadwell */ - Return (Multiply (25, 8)) + Return (25 * 8) } /* Set Config TDP Down */ @@ -92,31 +90,31 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCD, CTCC)) { + If (CTCD == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Down", Debug) + Debug = "Set TDP Down" /* Set CTC */ - Store (CTCD, CTCS) + CTCS = CTCD /* Set TAR */ - Store (TARD, TARS) + TARS = TARD /* Set PPC limit and notify OS */ - Store (PSSS (TARD), PPCM) + PPCM = PSSS (TARD) PPCN () /* Set PL2 */ - Store (CPL2 (CTDD), PL2V) + PL2V = CPL2 (CTDD) /* Set PL1 */ - Store (CTDD, PL1V) + PL1V = CTDD /* Store the new TDP Down setting */ - Store (CTCD, CTCC) + CTCC = CTCD Release (CTCM) Return (1) @@ -128,31 +126,31 @@ If (Acquire (CTCM, 100)) { Return (0) } - If (LEqual (CTCN, CTCC)) { + If (CTCN == CTCC) { Release (CTCM) Return (0) } - Store ("Set TDP Nominal", Debug) + Debug = "Set TDP Nominal" /* Set PL1 */ - Store (CTDN, PL1V) + PL1V = CTDN /* Set PL2 */ - Store (CPL2 (CTDN), PL2V) + PL2V = CPL2 (CTDN) /* Set PPC limit and notify OS */ - Store (PSSS (TARN), PPCM) + PPCM = PSSS (TARN) PPCN () /* Set TAR */ - Store (TARN, TARS) + TARS = TARN /* Set CTC */ - Store (CTCN, CTCS) + CTCS = CTCN /* Store the new TDP Nominal setting */ - Store (CTCN, CTCC) + CTCC = CTCN Release (CTCM) Return (1) @@ -161,7 +159,7 @@ /* Calculate PL1 value based on requested TDP */ Method (TDPP, 1, NotSerialized) { - Return (Multiply (ShiftLeft (Subtract (PUNI, 1), 2), Arg0)) + Return (((PUNI - 1) << 2) * Arg0) } /* Enable Controllable TDP to limit PL1 to requested value */ @@ -171,22 +169,22 @@ Return (0) } - Store ("Enable PL1 Limit", Debug) + Debug = "Enable PL1 Limit" /* Set _PPC to LFM */ - Store (PSSS (LFM_), Local0) - Add (Local0, 1, PPCM) + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 \PPCN () /* Set TAR to LFM-1 */ - Subtract (LFM_, 1, TARS) + TARS = LFM_ - 1 /* Set PL1 to desired value */ - Store (PL1V, SPL1) - Store (TDPP (Arg0), PL1V) + SPL1 = PL1V + PL1V = TDPP (Arg0) /* Set PL1 CLAMP bit */ - Store (One, PL1C) + PL1C = 1 Release (CTCM) Return (1) @@ -199,19 +197,19 @@ Return (0) } - Store ("Disable PL1 Limit", Debug) + Debug = "Disable PL1 Limit" /* Clear PL1 CLAMP bit */ - Store (Zero, PL1C) + PL1C = 0 /* Set PL1 to normal value */ - Store (SPL1, PL1V) + PL1V = SPL1 /* Set TAR to 0 */ - Store (Zero, TARS) + TARS = 0 /* Set _PPC to 0 */ - Store (Zero, PPCM) + PPCM = 0 \PPCN () Release (CTCM) diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl index 07db9f7..5a94bca 100644 --- a/src/soc/intel/broadwell/pch/acpi/pch.asl +++ b/src/soc/intel/broadwell/pch/acpi/pch.asl @@ -60,7 +60,7 @@ #include "sata.asl" // SMBus 0:1f.3 -#include "smbus.asl" +#include <southbridge/intel/common/acpi/smbus.asl> // Serial IO #include "serialio.asl" diff --git a/src/soc/intel/broadwell/pch/acpi/smbus.asl b/src/soc/intel/broadwell/pch/acpi/smbus.asl deleted file mode 100644 index 32b0b9c..0000000 --- a/src/soc/intel/broadwell/pch/acpi/smbus.asl +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Intel SMBus Controller 0:1f.3 - -Device (SBUS) -{ - Name (_ADR, 0x001f0003) -} -- To view, visit https://review.coreboot.org/c/coreboot/+/46757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13b35d2155a2cede0a56846b8bf8a79d4ebfc7b3 Gerrit-Change-Number: 46757 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: nb/intel/haswell: Place CTDP ASL code in a separate scope
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46756 ) Change subject: nb/intel/haswell: Place CTDP ASL code in a separate scope ...................................................................... nb/intel/haswell: Place CTDP ASL code in a separate scope This is just to align the code with what Broadwell does. Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl 2 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/46756/1 diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl index 7e59fb5..84c0f2f 100644 --- a/src/northbridge/intel/haswell/acpi/ctdp.asl +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -//Scope (\_SB.PCI0.MCHC) -//{ +Scope (\_SB.PCI0.MCHC) +{ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ Name (CTCC, 0) /* CTDP Current Selection */ Name (CTCN, 0) /* CTDP Nominal Select */ @@ -219,4 +219,4 @@ Release (CTCM) Return (1) } -//} +} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index ad38f4d..08f4471 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -80,8 +80,6 @@ Offset (0xbc), // Top of Low Used Memory TLUD, 32, } - - #include "ctdp.asl" } // Current Resource Settings @@ -227,3 +225,6 @@ Return (MCRS) } + +/* Configurable TDP */ +#include "ctdp.asl" -- To view, visit https://review.coreboot.org/c/coreboot/+/46756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52fb1546d049ca9fa09d0c54304ca1d79f6c4c3e Gerrit-Change-Number: 46756 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: nb/intel/haswell/acpi: Align with Broadwell
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46755 ) Change subject: nb/intel/haswell/acpi: Align with Broadwell ...................................................................... nb/intel/haswell/acpi: Align with Broadwell Align cosmetics and move CTDP-specific ASL into its own file. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/northbridge/intel/haswell/acpi/ctdp.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl 2 files changed, 229 insertions(+), 223 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/46755/1 diff --git a/src/northbridge/intel/haswell/acpi/ctdp.asl b/src/northbridge/intel/haswell/acpi/ctdp.asl new file mode 100644 index 0000000..7e59fb5 --- /dev/null +++ b/src/northbridge/intel/haswell/acpi/ctdp.asl @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +//Scope (\_SB.PCI0.MCHC) +//{ + Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ + Name (CTCC, 0) /* CTDP Current Selection */ + Name (CTCN, 0) /* CTDP Nominal Select */ + Name (CTCD, 1) /* CTDP Down Select */ + Name (CTCU, 2) /* CTDP Up Select */ + Name (SPL1, 0) /* Saved PL1 value */ + + OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) + Field (MCHB, DWordAcc, Lock, Preserve) + { + Offset (0x930), /* PACKAGE_POWER_SKU */ + CTDN, 15, /* CTDP Nominal PL1 */ + Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ + PUNI, 4, /* Power Units */ + , 4, + EUNI, 5, /* Energy Units */ + , 3, + TUNI, 4, /* Time Units */ + Offset (0x958), /* PLATFORM_INFO */ + , 40, + LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ + Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ + PL1V, 15, /* Power Limit 1 Value */ + PL1E, 1, /* Power Limit 1 Enable */ + PL1C, 1, /* Power Limit 1 Clamp */ + PL1T, 7, /* Power Limit 1 Time */ + Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ + PL2V, 15, /* Power Limit 2 Value */ + PL2E, 1, /* Power Limit 2 Enable */ + PL2C, 1, /* Power Limit 2 Clamp */ + PL2T, 7, /* Power Limit 2 Time */ + Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ + TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ + Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ + CTDD, 15, /* CTDP Down PL1 */ + , 1, + TARD, 8, /* CTDP Down Turbo Activation Ratio */ + Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ + CTDU, 15, /* CTDP Up PL1 */ + , 1, + TARU, 8, /* CTDP Up Turbo Activation Ratio */ + Offset (0xf50), /* CONFIG_TDP_CONTROL */ + CTCS, 2, /* CTDP Select */ + Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ + TARS, 8, /* Turbo Activation Ratio Select */ + } + + /* + * Search CPU0 _PSS looking for control = arg0 and then + * return previous P-state entry number for new _PPC + * + * Format of _PSS: + * Name (_PSS, Package () { + * Package (6) { freq, power, tlat, blat, control, status } + * } + */ + External (\_SB.CP00._PSS) + Method (PSSS, 1, NotSerialized) + { + Local0 = 1 /* Start at P1 */ + Local1 = SizeOf (\_SB.CP00._PSS) + + While (Local0 < Local1) { + /* Store _PSS entry Control value to Local2 */ + Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 + If (Local2 == Arg0) { + Return (Local0 - 1) + } + Local0++ + } + + Return (0) + } + + /* Calculate PL2 based on chip type */ + Method (CPL2, 1, NotSerialized) + { + If (\ISLP ()) { + /* Haswell ULT PL2 = 25W */ + Return (25 * 8) + } Else { + /* Haswell Mobile PL2 = 1.25 * PL1 */ + Return ((Arg0 * 125) / 100) + } + } + + /* Set Config TDP Down */ + Method (STND, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (CTCD == CTCC) { + Release (CTCM) + Return (0) + } + + Debug = "Set TDP Down" + + /* Set CTC */ + CTCS = CTCD + + /* Set TAR */ + TARS = TARD + + /* Set PPC limit and notify OS */ + PPCM = PSSS (TARD) + PPCN () + + /* Set PL2 */ + PL2V = CPL2 (CTDD) + + /* Set PL1 */ + PL1V = CTDD + + /* Store the new TDP Down setting */ + CTCC = CTCD + + Release (CTCM) + Return (1) + } + + /* Set Config TDP Nominal from Down */ + Method (STDN, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + If (CTCN == CTCC) { + Release (CTCM) + Return (0) + } + + Debug = "Set TDP Nominal" + + /* Set PL1 */ + PL1V = CTDN + + /* Set PL2 */ + PL2V = CPL2 (CTDN) + + /* Set PPC limit and notify OS */ + PPCM = PSSS (TARN) + PPCN () + + /* Set TAR */ + TARS = TARN + + /* Set CTC */ + CTCS = CTCN + + /* Store the new TDP Nominal setting */ + CTCC = CTCN + + Release (CTCM) + Return (1) + } + + /* Calculate PL1 value based on requested TDP */ + Method (TDPP, 1, NotSerialized) + { + Return (((PUNI - 1) << 2) * Arg0) + } + + /* Enable Controllable TDP to limit PL1 to requested value */ + Method (CTLE, 1, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + + Debug = "Enable PL1 Limit" + + /* Set _PPC to LFM */ + Local0 = PSSS (LFM_) + PPCM = Local0 + 1 + \PPCN () + + /* Set TAR to LFM-1 */ + TARS = LFM_ - 1 + + /* Set PL1 to desired value */ + SPL1 = PL1V + PL1V = TDPP (Arg0) + + /* Set PL1 CLAMP bit */ + PL1C = 1 + + Release (CTCM) + Return (1) + } + + /* Disable Controllable TDP */ + Method (CTLD, 0, Serialized) + { + If (Acquire (CTCM, 100)) { + Return (0) + } + + Debug = "Disable PL1 Limit" + + /* Clear PL1 CLAMP bit */ + PL1C = 0 + + /* Set PL1 to normal value */ + PL1V = SPL1 + + /* Set TAR to 0 */ + TARS = 0 + + /* Set _PPC to 0 */ + PPCM = 0 + \PPCN () + + Release (CTCM) + Return (1) + } +//} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 1d4eba6..ad38f4d 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,15 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -Name(_HID,EISAID("PNP0A08")) // PCIe -Name(_CID,EISAID("PNP0A03")) // PCI +Name (_HID, EISAID ("PNP0A08")) // PCIe +Name (_CID, EISAID ("PNP0A03")) // PCI -Name(_BBN, 0) +Name (_BBN, 0) Device (MCHC) { - Name(_ADR, 0x00000000) // 0:0.0 + Name (_ADR, 0x00000000) // 0:0.0 - OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) Field (MCHP, DWordAcc, NoLock, Preserve) { Offset (0x40), // EPBAR @@ -81,223 +81,7 @@ TLUD, 32, } - Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */ - Name (CTCC, 0) /* CTDP Current Selection */ - Name (CTCN, 0) /* CTDP Nominal Select */ - Name (CTCD, 1) /* CTDP Down Select */ - Name (CTCU, 2) /* CTDP Up Select */ - Name (SPL1, 0) /* Saved PL1 value */ - - OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR + 0x5000, 0x1000) - Field (MCHB, DWordAcc, Lock, Preserve) - { - Offset (0x930), /* PACKAGE_POWER_SKU */ - CTDN, 15, /* CTDP Nominal PL1 */ - Offset (0x938), /* PACKAGE_POWER_SKU_UNIT */ - PUNI, 4, /* Power Units */ - , 4, - EUNI, 5, /* Energy Units */ - , 3, - TUNI, 4, /* Time Units */ - Offset (0x958), /* PLATFORM_INFO */ - , 40, - LFM_, 8, /* Maximum Efficiency Ratio (LFM) */ - Offset (0x9a0), /* TURBO_POWER_LIMIT1 */ - PL1V, 15, /* Power Limit 1 Value */ - PL1E, 1, /* Power Limit 1 Enable */ - PL1C, 1, /* Power Limit 1 Clamp */ - PL1T, 7, /* Power Limit 1 Time */ - Offset (0x9a4), /* TURBO_POWER_LIMIT2 */ - PL2V, 15, /* Power Limit 2 Value */ - PL2E, 1, /* Power Limit 2 Enable */ - PL2C, 1, /* Power Limit 2 Clamp */ - PL2T, 7, /* Power Limit 2 Time */ - Offset (0xf3c), /* CONFIG_TDP_NOMINAL */ - TARN, 8, /* CTDP Nominal Turbo Activation Ratio */ - Offset (0xf40), /* CONFIG_TDP_LEVEL1 */ - CTDD, 15, /* CTDP Down PL1 */ - , 1, - TARD, 8, /* CTDP Down Turbo Activation Ratio */ - Offset (0xf48), /* MSR_CONFIG_TDP_LEVEL2 */ - CTDU, 15, /* CTDP Up PL1 */ - , 1, - TARU, 8, /* CTDP Up Turbo Activation Ratio */ - Offset (0xf50), /* CONFIG_TDP_CONTROL */ - CTCS, 2, /* CTDP Select */ - Offset (0xf54), /* TURBO_ACTIVATION_RATIO */ - TARS, 8, /* Turbo Activation Ratio Select */ - } - - /* - * Search CPU0 _PSS looking for control = arg0 and then - * return previous P-state entry number for new _PPC - * - * Format of _PSS: - * Name (_PSS, Package () { - * Package (6) { freq, power, tlat, blat, control, status } - * } - */ - External (\_SB.CP00._PSS) - Method (PSSS, 1, NotSerialized) - { - Local0 = 1 /* Start at P1 */ - Local1 = SizeOf (\_SB.CP00._PSS) - - While (Local0 < Local1) { - /* Store _PSS entry Control value to Local2 */ - Local2 = DeRefOf (Index (DeRefOf (Index (\_SB.CP00._PSS, Local0)), 4)) >> 8 - If (Local2 == Arg0) { - Return (Local0 - 1) - } - Local0++ - } - - Return (0) - } - - /* Calculate PL2 based on chip type */ - Method (CPL2, 1, NotSerialized) - { - If (\ISLP ()) { - /* Haswell ULT PL2 = 25W */ - Return (25 * 8) - } Else { - /* Haswell Mobile PL2 = 1.25 * PL1 */ - Return ((Arg0 * 125) / 100) - } - } - - /* Set Config TDP Down */ - Method (STND, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCD == CTCC) { - Release (CTCM) - Return (0) - } - - Debug = "Set TDP Down" - - /* Set CTC */ - CTCS = CTCD - - /* Set TAR */ - TARS = TARD - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARD) - PPCN () - - /* Set PL2 */ - PL2V = CPL2 (CTDD) - - /* Set PL1 */ - PL1V = CTDD - - /* Store the new TDP Down setting */ - CTCC = CTCD - - Release (CTCM) - Return (1) - } - - /* Set Config TDP Nominal from Down */ - Method (STDN, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - If (CTCN == CTCC) { - Release (CTCM) - Return (0) - } - - Debug = "Set TDP Nominal" - - /* Set PL1 */ - PL1V = CTDN - - /* Set PL2 */ - PL2V = CPL2 (CTDN) - - /* Set PPC limit and notify OS */ - PPCM = PSSS (TARN) - PPCN () - - /* Set TAR */ - TARS = TARN - - /* Set CTC */ - CTCS = CTCN - - /* Store the new TDP Nominal setting */ - CTCC = CTCN - - Release (CTCM) - Return (1) - } - - /* Calculate PL1 value based on requested TDP */ - Method (TDPP, 1, NotSerialized) - { - Return (((PUNI - 1) << 2) * Arg0) - } - - /* Enable Controllable TDP to limit PL1 to requested value */ - Method (CTLE, 1, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Debug = "Enable PL1 Limit" - - /* Set _PPC to LFM */ - Local0 = PSSS (LFM_) - PPCM = Local0 + 1 - \PPCN () - - /* Set TAR to LFM-1 */ - TARS = LFM_ - 1 - - /* Set PL1 to desired value */ - SPL1 = PL1V - PL1V = TDPP (Arg0) - - /* Set PL1 CLAMP bit */ - PL1C = 1 - - Release (CTCM) - Return (1) - } - - /* Disable Controllable TDP */ - Method (CTLD, 0, Serialized) - { - If (Acquire (CTCM, 100)) { - Return (0) - } - - Debug = "Disable PL1 Limit" - - /* Clear PL1 CLAMP bit */ - PL1C = 0 - - /* Set PL1 to normal value */ - PL1V = SPL1 - - /* Set TAR to 0 */ - TARS = 0 - - /* Set _PPC to 0 */ - PPCM = 0 - \PPCN () - - Release (CTCM) - Return (1) - } + #include "ctdp.asl" } // Current Resource Settings @@ -439,7 +223,7 @@ PMIN = Local0 PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1 - PLEN = PMAX - PMIN + 1 + PLEN = (PMAX - PMIN) + 1 Return (MCRS) } -- To view, visit https://review.coreboot.org/c/coreboot/+/46755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I476a4e01016caa3658177b0fa8916576f4a5e0e5 Gerrit-Change-Number: 46755 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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