coreboot-gerrit November 2020

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Change in coreboot[master]: util/rockchip: port make_idb.py to python3
by Stefan Reinauer (Code Review) 04 Nov '20

04 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42319 ) Change subject: util/rockchip: port make_idb.py to python3 ...................................................................... util/rockchip: port make_idb.py to python3 converted with 2to3 and manually changed shebang to reflect python3. Tested by calling the script on the command line. Change-Id: I0e399c491ab07cd3e7fda24231cf3f7611b341e3 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/rockchip/make_idb.py 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/42319/1 diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py index 12cd130..4f04676 100755 --- a/util/rockchip/make_idb.py +++ b/util/rockchip/make_idb.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # SPDX-License-Identifier: BSD-2-Clause import struct @@ -7,10 +7,10 @@ class IDBTool: def __init__(self): - print "Initialize IDBTool" + print("Initialize IDBTool") def p_rc4(self, buf, length): - key = (124,78,3,4,85,5,9,7,45,44,123,56,23,13,23,17) + key = (124, 78, 3, 4, 85, 5, 9, 7, 45, 44, 123, 56, 23, 13, 23, 17) K = key * 16 S = [i for i in range(256)] @@ -79,7 +79,7 @@ fout.write(''.join(idblock)) fout.write(''.join(blank)) - for s in xrange(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): + for s in range(0, sectors * SECTOR_SIZE, PAGE_ALIGN * SECTOR_SIZE): fout.write(''.join(buf[s : s + PAGE_ALIGN * SECTOR_SIZE])) fout.write(''.join(blank)) else: @@ -90,11 +90,11 @@ sys.exit("Failed to write data to : " + to_file) finally: fout.close() - print "DONE" + print("DONE") def usage(): - print "Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in" - print " --chip: default is RK32" + print("Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in") + print(" --chip: default is RK32") if __name__ == '__main__': rc4_flag = align_flag = False -- To view, visit https://review.coreboot.org/c/coreboot/+/42319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e399c491ab07cd3e7fda24231cf3f7611b341e3 Gerrit-Change-Number: 42319 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/exynos: Port *_cksum.py to python3
by Stefan Reinauer (Code Review) 04 Nov '20

04 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42321 ) Change subject: util/exynos: Port *_cksum.py to python3 ...................................................................... util/exynos: Port *_cksum.py to python3 Manually changed shebang to reflect python3, no further porting needed. Tested by calling the scripts on the command line. Change-Id: I116696576081460a7d503ee4a032c5430a430888 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/exynos/fixed_cksum.py M util/exynos/variable_cksum.py 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/42321/1 diff --git a/util/exynos/fixed_cksum.py b/util/exynos/fixed_cksum.py index c6a9ddae..25537de 100755 --- a/util/exynos/fixed_cksum.py +++ b/util/exynos/fixed_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause diff --git a/util/exynos/variable_cksum.py b/util/exynos/variable_cksum.py index 62a76cc..f908049 100755 --- a/util/exynos/variable_cksum.py +++ b/util/exynos/variable_cksum.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # SPDX-License-Identifier: BSD-3-Clause -- To view, visit https://review.coreboot.org/c/coreboot/+/42321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I116696576081460a7d503ee4a032c5430a430888 Gerrit-Change-Number: 42321 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/purism/librem/ec.asl: End comment
by Stefan Reinauer (Code Review) 04 Nov '20

04 Nov '20

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47115 ) Change subject: ec/purism/librem/ec.asl: End comment ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Gerrit-Change-Number: 47115 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 19:23:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Nico Huber (Code Review) 04 Nov '20

04 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG@18 PS4, Line 18: entry is added. > What do you mean with "a section"... […] Yes, I meant an ELF section. And you are right, compression probably makes it too complex. The difference to Kconfig options would be that you get to use the exact same code. However, personally I'd just use Kconfig. You mean verification schemes as in hashes and digital signatures? Actually, I would want them to change. If it's really for x86 with its memory mapped flash, VPD isn't much overhead either, is it? I didn't look much at the code, but why would it be heavier than the CMOS option table? Anyway, I didn't see x86 written on this patch. Was that the intention? -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 19:15:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… PS2, Line 76: case ADL_P_LP4_1: > It's an old habit of mine that would give you a heuristic to catch unintended fallthroughs. […] Our current compiler flags make GCC complain on potentially-incorrect implicit fallthroughs unless there's a comment. Since having contiguous cases fall through is commonly intentional, GCC does not warn on these. -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 19:09:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Tim Wawrzynczak (Code Review) 04 Nov '20

04 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… PS2, Line 76: case ADL_P_LP4_1: > I would agree in other cases, but I'd say this case is pretty self-explanatory already. […] It's an old habit of mine that would give you a heuristic to catch unintended fallthroughs. This case isn't too bad, but I will also note that C++17 added support for a [[fallthrough]] attribute, which I think you can finagle into an error if the compiler catches an unmarked one. I guess code review is our tool to make sure things like this are correct here. -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 18:47:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in em100[master]: Add enter/exit 4-byte and quad io mode commands
by Stefan Reinauer (Code Review) 04 Nov '20

04 Nov '20

Stefan Reinauer has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/46925 ) Change subject: Add enter/exit 4-byte and quad io mode commands ...................................................................... Add enter/exit 4-byte and quad io mode commands Signed-off-by: Alexander Amelkin <a.amelkin(a)yadro.com> Change-Id: I1f022b4f9803d5e9657484349541776fe8a746cf --- M trace.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/25/46925/1 diff --git a/trace.c b/trace.c index 5e98acb..448a469 100644 --- a/trace.c +++ b/trace.c @@ -124,6 +124,10 @@ {"read JEDEC ID", 0x9f, 0, 0}, {"chip erase", 0xc7, 0, 0}, {"sector erase", 0xd8, 1, 0}, + {"enter 4-byte address mode", 0xb7, 0, 0}, + {"exit 4-byte address mode", 0xe9, 0, 0}, + {"enter quad i/o mode", 0x35, 0, 0}, + {"exit quat i/o mode", 0xf5, 0, 0}, {"unknown command", 0xff, 0, 0} }; -- To view, visit https://review.coreboot.org/c/em100/+/46925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: I1f022b4f9803d5e9657484349541776fe8a746cf Gerrit-Change-Number: 46925 Gerrit-PatchSet: 1 Gerrit-Owner: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/purism/librem/ec.asl: End comment
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47115 ) Change subject: ec/purism/librem/ec.asl: End comment ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Gerrit-Change-Number: 47115 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 18:39:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: ec/purism/librem/ec.asl: End comment
by Benjamin Doron (Code Review) 04 Nov '20

04 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47115 ) Change subject: ec/purism/librem/ec.asl: End comment ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Gerrit-Change-Number: 47115 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 16:49:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for DDR5 memory
by Subrata Banik (Code Review) 04 Nov '20

04 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46485 ) Change subject: mb/intel/adlrvp: Add support for DDR5 memory ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… PS7, Line 62: .rcomp_targets = {50, 30, 30, 30, 27}, > No, I meant to have something like: […] Sounds good Angel, will wait for your observation, you can modify this later as well -- To view, visit https://review.coreboot.org/c/coreboot/+/46485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Gerrit-Change-Number: 46485 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 15:39:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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coreboot-gerrit November 2020