coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: ec/purism/librem/ec.asl: End comment
by Benjamin Doron (Code Review) 04 Nov '20

04 Nov '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47115 ) Change subject: ec/purism/librem/ec.asl: End comment ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/47115 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id192d665a22a8885d7cec56cd6b8ea207fb54402 Gerrit-Change-Number: 47115 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 16:49:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for DDR5 memory
by Subrata Banik (Code Review) 04 Nov '20

04 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46485 ) Change subject: mb/intel/adlrvp: Add support for DDR5 memory ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… PS7, Line 62: .rcomp_targets = {50, 30, 30, 30, 27}, > No, I meant to have something like: […] Sounds good Angel, will wait for your observation, you can modify this later as well -- To view, visit https://review.coreboot.org/c/coreboot/+/46485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Gerrit-Change-Number: 46485 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 15:39:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for DDR5 memory
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46485 ) Change subject: mb/intel/adlrvp: Add support for DDR5 memory ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… PS7, Line 62: .rcomp_targets = {50, 30, 30, 30, 27}, > Sure Angel. Nice feedback. […] No, I meant to have something like: const uint16_t rcomp_targets_ddr5_p[5] = {50, 30, 30, 30, 27}; Then, one should be able to simply use the array as initializer: .rcomp_targets = rcomp_targets_ddr5_p, I haven't tested this, though. I would also like to ensure these Rcomp targets are reasonable defaults. I can try to do this for SKL and CFL as an example, since I know the platforms better. I mean, I've desoldered measured the Rcomp resistors on a SKL-S CPU 😄 -- To view, visit https://review.coreboot.org/c/coreboot/+/46485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Gerrit-Change-Number: 46485 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 15:30:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subrata.banik(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Subrata Banik (Code Review) 04 Nov '20

04 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 13:52:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/xeon_sp: Add a smm_region function
by Arthur Heymans (Code Review) 04 Nov '20

04 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46657 ) Change subject: soc/intel/xeon_sp: Add a smm_region function ...................................................................... soc/intel/xeon_sp: Add a smm_region function This reports where TSEG is located and will be used when setting up SMM. Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Makefile.inc A src/soc/intel/xeon_sp/memmap.c 2 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/1 diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 3bbf6b7..ea5f253 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -6,8 +6,8 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c -romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c +romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c memmap.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c new file mode 100644 index 0000000..08ea732 --- /dev/null +++ b/src/soc/intel/xeon_sp/memmap.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <device/pci.h> +#include <cpu/x86/smm.h> +#include <soc/pci_devs.h> + +void smm_region(uintptr_t *start, size_t *size) +{ + uintptr_t tseg_base = pci_read_config32(PCI_DEV(0, VTD_DEV, VTD_FUNC), + VTD_TSEG_BASE_CSR); + uintptr_t tseg_limit = pci_read_config32(PCI_DEV(0, VTD_DEV, VTD_FUNC), + VTD_TSEG_LIMIT_CSR); + + tseg_base &= 0xfff00000; + tseg_limit &= 0xfff00000; + /* Only the upper [31:20] bits of an address are checked against + * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this effectively means + * +1MiB for the limit. + */ + tseg_limit += 1 * MiB; + + *start = tseg_base; + *size = tseg_limit - tseg_base; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/46657 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd Gerrit-Change-Number: 46657 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Replace if-else-if ladder with switch construct
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47054 ) Change subject: mb/intel/adlrvp: Replace if-else-if ladder with switch construct ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/47054/2/src/mainboard/intel/adlrvp… PS2, Line 76: case ADL_P_LP4_1: > Because missing a 'break' (or return, etc.) in switch statements is a common mistake, I like to add […] I would agree in other cases, but I'd say this case is pretty self-explanatory already. Generally, I only add a comment about falling through when one case executes something and then falls through another case. Here's an example: /* Ensure magic is not power gated before reading the status */ pci_and_config8(dev, MAGIC_CONTROL_REG, ~POWER_GATE_MAGIC); enum magic_power_level magic_power = pci_read_config8(dev, MAGIC_STATUS_REG); switch (magic_power) { case NO_MAGIC: printk(BIOS_DEBUG, "Magic is disabled\n"); /* Power off magic to save power */ pci_or_config8(dev, MAGIC_CONTROL_REG, POWER_GATE_MAGIC); /* Intentional fallthrough */ case MINIMUM_MAGIC: /* Ensure advanced magic is off */ pci_and_config8(dev, MAGIC_CONTROL_REG, ~ADVANCED_MAGIC_ENABLE); break; case STANDARD_MAGIC: case MORE_MAGIC: pci_write_config8(dev, MAGIC_POWER_SELECT_REG, magic_power); udelay(400); /* Magic power changes need some time to complete */ /* Only enable advanced magic after power has been configured */ pci_or_config8(dev, MAGIC_CONTROL_REG, ADVANCED_MAGIC_ENABLE); break; default: /* Cannot safely handle too much magic */ die("Requested magic power %u is unsafe\n", magic_power); } Yes, it might not make much sense, but this magic hardware is programmed using magic sequences. -- To view, visit https://review.coreboot.org/c/coreboot/+/47054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268db8bc63aaf64d4a91c9a44ef5282154b20a53 Gerrit-Change-Number: 47054 Gerrit-PatchSet: 2 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Comment-Date: Wed, 04 Nov 2020 13:39:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for DDR5 memory
by Subrata Banik (Code Review) 04 Nov '20

04 Nov '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46485 ) Change subject: mb/intel/adlrvp: Add support for DDR5 memory ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… PS7, Line 62: .rcomp_targets = {50, 30, 30, 30, 27}, > It would be nice to provide const arrays for the recommended Rcomp target values in SoC code. Sure Angel. Nice feedback. i believe you meant to make rcomp_resistor and rcomp_targets both const? https://github.com/coreboot/coreboot/blob/master/src/soc/intel/alderlake/in… -- To view, visit https://review.coreboot.org/c/coreboot/+/46485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Gerrit-Change-Number: 46485 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 13:23:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/adlrvp: Add support for DDR5 memory
by Angel Pons (Code Review) 04 Nov '20

04 Nov '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46485 ) Change subject: mb/intel/adlrvp: Add support for DDR5 memory ...................................................................... Patch Set 7: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… File src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c: https://review.coreboot.org/c/coreboot/+/46485/7/src/mainboard/intel/adlrvp… PS7, Line 62: .rcomp_targets = {50, 30, 30, 30, 27}, It would be nice to provide const arrays for the recommended Rcomp target values in SoC code. -- To view, visit https://review.coreboot.org/c/coreboot/+/46485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Gerrit-Change-Number: 46485 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.bmg(a)gmail.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 13:05:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cnl: Fix `PcieClkSrcUsage` setting
by Felix Singer (Code Review) 04 Nov '20

04 Nov '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/39795 to review the following change. Change subject: soc/intel/cnl: Fix `PcieClkSrcUsage` setting ...................................................................... soc/intel/cnl: Fix `PcieClkSrcUsage` setting Remove unnecessary for-loop because the setting gets overwritten with memcpy afterwards. Change-Id: Idb2192e68e29ae53fcdd0775ac7fd6cea2930a0e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/39795/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 4634806..bbacfc1 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -320,10 +320,6 @@ params->PchCnviMode = 0; #endif /* PCI Express */ - for (i = 0; i < ARRAY_SIZE(config->PcieClkSrcUsage); i++) { - if (config->PcieClkSrcUsage[i] == 0) - config->PcieClkSrcUsage[i] = PCIE_CLK_NOTUSED; - } memcpy(params->PcieClkSrcUsage, config->PcieClkSrcUsage, sizeof(config->PcieClkSrcUsage)); memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, -- To view, visit https://review.coreboot.org/c/coreboot/+/39795 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb2192e68e29ae53fcdd0775ac7fd6cea2930a0e Gerrit-Change-Number: 39795 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/samsung/lumpy: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46214 ) Change subject: mb/samsung/lumpy: Convert to ASL 2.0 syntax ...................................................................... mb/samsung/lumpy: Convert to ASL 2.0 syntax Change-Id: I7ad79a31142af8ae1b62497ade0b4ba7bac3a93c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/samsung/lumpy/acpi/mainboard.asl M src/mainboard/samsung/lumpy/acpi/platform.asl M src/mainboard/samsung/lumpy/acpi/thermal.asl 3 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/46214/1 diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl index 9b5ae77..d9c9d61 100644 --- a/src/mainboard/samsung/lumpy/acpi/mainboard.asl +++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl @@ -8,7 +8,7 @@ Name(_HID, EisaId("PNP0C0D")) Method(_LID, 0) { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) + \LIDS = \_SB.PCI0.LPCB.EC0.LIDS Return (\LIDS) } diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl index 579308d..0b83f50 100644 --- a/src/mainboard/samsung/lumpy/acpi/platform.asl +++ b/src/mainboard/samsung/lumpy/acpi/platform.asl @@ -6,43 +6,43 @@ Method(_PTS,1) { - Store (Zero, GP35) // Disable WLAN - Store (Zero, GP38) // Disable WWAN + GP35 = 0 // Disable WLAN + GP38 = 0 // Disable WWAN If (S33G) { - Store (Zero, GP43) // Enable HSPA + GP43 = 0 // Enable HSPA } Else { - Store (One, GP43) // Disable HSPA + GP43 = 1 // Disable HSPA } - If (LEqual (Arg0, 3)) { + If (Arg0 == 3) { // NVS has a flag to determine USB policy in S3 If (S3U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S3 If (S3U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } - If (LEqual (Arg0, 5)) { + If (Arg0 == 5) { // NVS has a flag to determine USB policy in S5 If (S5U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S5 If (S5U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } } @@ -52,10 +52,10 @@ Method(_WAK,1) { /* Update in case state changed while asleep */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, \PWRS) + \PWRS = \_SB.PCI0.LPCB.EC0.ACEX /* Enable OS control of fan */ - Store (One, \_SB.PCI0.LPCB.EC0.FCOS) + \_SB.PCI0.LPCB.EC0.FCOS = 1 Return(Package(){0,0}) } diff --git a/src/mainboard/samsung/lumpy/acpi/thermal.asl b/src/mainboard/samsung/lumpy/acpi/thermal.asl index dd85181..55923bd 100644 --- a/src/mainboard/samsung/lumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/lumpy/acpi/thermal.asl @@ -26,10 +26,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -55,27 +55,27 @@ Method (_TMP, 0, Serialized) { // Get CPU Temperature from the Embedded Controller - Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.CPUT // Re-read from EC if the temperature is very high to // avoid OS shutdown if we got a bad reading. - If (LGreaterEqual (Local0, \TCRT)) { - Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0) - If (LGreaterEqual (Local0, \TCRT)) { + If (Local0 >= \TCRT) { + Local0 = \_SB.PCI0.LPCB.EC0.CPUT + If (Local0 >= \TCRT) { // Check if this is an early read - If (LLess (CRDC, IRDC)) { - Store (0, Local0) + If (CRDC < IRDC) { + Local0 = 0 } } } // Keep track of first few reads by the OS - If (LLess (CRDC, IRDC)) { - Increment (CRDC) + If (CRDC < IRDC) { + CRDC++ } // Invalid reading, ensure fan is spinning - If (LGreaterEqual (Local0, 0x80)) { + If (Local0 >= 0x80) { Return (CTOK (\F4ON)) } @@ -83,7 +83,7 @@ } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -91,7 +91,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -99,7 +99,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -107,7 +107,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -115,7 +115,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) -- To view, visit https://review.coreboot.org/c/coreboot/+/46214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7ad79a31142af8ae1b62497ade0b4ba7bac3a93c Gerrit-Change-Number: 46214 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020