Change in coreboot[master]: soc/intel/xeon_sp: Add a smm_region function

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/memmap.c
2 files changed, 28 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/1

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 3bbf6b7..ea5f253 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -6,8 +6,8 @@
 subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx

bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
-romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
-ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c
+romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
+ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c memmap.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
 postcar-y += spi.c

diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
new file mode 100644
index 0000000..08ea732
--- /dev/null
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define __SIMPLE_DEVICE__
+
+#include <device/pci.h>
+#include <cpu/x86/smm.h>
+#include <soc/pci_devs.h>
+
+void smm_region(uintptr_t *start, size_t *size)
+{
+	uintptr_t tseg_base = pci_read_config32(PCI_DEV(0, VTD_DEV, VTD_FUNC),
+						  VTD_TSEG_BASE_CSR);
+	uintptr_t tseg_limit = pci_read_config32(PCI_DEV(0, VTD_DEV, VTD_FUNC),
+						   VTD_TSEG_LIMIT_CSR);
+
+	tseg_base &= 0xfff00000;
+	tseg_limit &= 0xfff00000;
+	/* Only the upper [31:20] bits of an address are checked against
+	 * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this effectively means
+	 * +1MiB for the limit.
+	 */
+	tseg_limit += 1 * MiB;
+
+	*start = tseg_base;
+	*size = tseg_limit - tseg_base;
+}

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 1: Code-Review+1

(4 comments)

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
File src/soc/intel/xeon_sp/memmap.c:

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 5: pci
pci_ops ?

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 11: PCI_DEV(0, VTD_DEV, VTD_FUNC)
Maybe #define this?

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 16: 	tseg_base &= 0xfff00000;
I'd use:

tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB);

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 19:  this effectively means
nit: Move this part to the next line, so that the comment is more rectangular

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46657

to look at the new patch set (#2).

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/soc_util.c
5 files changed, 57 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/2

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 1:

(4 comments)

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
File src/soc/intel/xeon_sp/memmap.c:

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 5: pci
> pci_ops ?

Done

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 11: PCI_DEV(0, VTD_DEV, VTD_FUNC)
> Maybe #define this?

Done

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 16: 	tseg_base &= 0xfff00000;
> I'd use: […]

Done

https://review.coreboot.org/c/coreboot/+/46657/1/src/soc/intel/xeon_sp/memma... 
PS1, Line 19:  this effectively means
> nit: Move this part to the next line, so that the comment is more rectangular

Done

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 2:

(4 comments)

https://review.coreboot.org/c/coreboot/+/46657/2/src/soc/intel/xeon_sp/cpx/i... 
File src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/46657/2/src/soc/intel/xeon_sp/cpx/i... 
PS2, Line 85: #define VTD_DEV(bus)		pcidev_path_on_bus((bus), PCIDEV_FN(VTD_DEV_NUM, VTD_FUNC_NUM)
Macros with complex values should be enclosed in parentheses

https://review.coreboot.org/c/coreboot/+/46657/2/src/soc/intel/xeon_sp/cpx/i... 
PS2, Line 91: #define VTD_DEV(bus)		pcidev_path_on_bus((bus), PCIDEV_FN(VTD_DEV_NUM, VTD_FUNC_NUM)
Macros with complex values should be enclosed in parentheses

https://review.coreboot.org/c/coreboot/+/46657/2/src/soc/intel/xeon_sp/skx/i... 
File src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h:

https://review.coreboot.org/c/coreboot/+/46657/2/src/soc/intel/xeon_sp/skx/i... 
PS2, Line 134: #define VTD_DEV(bus)		pcidev_path_on_bus((bus), PCIDEV_FN(VTD_DEV_NUM, VTD_FUNC_NUM)
Macros with complex values should be enclosed in parentheses

https://review.coreboot.org/c/coreboot/+/46657/2/src/soc/intel/xeon_sp/skx/i... 
PS2, Line 140: #define VTD_DEV(bus)		pcidev_path_on_bus((bus), PCIDEV_FN(VTD_DEV_NUM, VTD_FUNC_NUM)
Macros with complex values should be enclosed in parentheses

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46657

to look at the new patch set (#3).

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
M src/soc/intel/xeon_sp/skx/soc_util.c
5 files changed, 57 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/3

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 3: Code-Review+2

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46657

to look at the new patch set (#4).

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
4 files changed, 42 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/4

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 4: Code-Review+2

[Christian Walter (Code Review)]

Christian Walter has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 4: Code-Review+2

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Christian Walter, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46657

to look at the new patch set (#5).

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
4 files changed, 42 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/5

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 5: Code-Review+2

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Christian Walter, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46657

to look at the new patch set (#7).

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans 
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
4 files changed, 40 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/7

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 7: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

Patch Set 7: Code-Review+2

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46657 )

Change subject: soc/intel/xeon_sp: Add a smm_region function
......................................................................

soc/intel/xeon_sp: Add a smm_region function

This reports where TSEG is located and will be used when setting up
SMM.

Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657
Tested-by: build bot (Jenkins) 
Reviewed-by: Patrick Rudolph 
Reviewed-by: Angel Pons 
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
4 files changed, 40 insertions(+), 5 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 40a1020..07fe3de 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -6,8 +6,9 @@
 subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx

bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
-romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
+romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
 ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c
+ramstage-y += memmap.c
 ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index bb0f877..68dee28 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -77,8 +77,14 @@
 #define VMD_FUNC_NUM            0x05

#define MMAP_VTD_CFG_REG_DEVID		0x2024
-#define VTD_DEV				0x5
-#define VTD_FUNC			0x0
+#define VTD_DEV_NUM			0x5
+#define VTD_FUNC_NUM			0x0
+
+#if !defined(__SIMPLE_DEVICE__)
+#define VTD_DEV(bus)		pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM))
+#else
+#define VTD_DEV(bus)		PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
+#endif

#define APIC_DEV_NUM            0x05
 #define APIC_FUNC_NUM           0x04
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
new file mode 100644
index 0000000..79ab47e
--- /dev/null
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <cpu/x86/smm.h>
+#include <soc/pci_devs.h>
+
+void smm_region(uintptr_t *start, size_t *size)
+{
+	uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR);
+	uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR);
+
+	tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB);
+	tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB);
+	/* Only the upper [31:20] bits of an address are checked against
+	 * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this
+	 * effectively means +1MiB for the limit.
+	 */
+	tseg_limit += 1 * MiB;
+
+	*start = tseg_base;
+	*size = tseg_limit - tseg_base;
+}
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 6b84f70..b500c28 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -126,8 +126,14 @@
 #define HPET0_FUNC_NUM          0x00

#define MMAP_VTD_CFG_REG_DEVID		0x2024
-#define VTD_DEV				5
-#define VTD_FUNC			0
+#define VTD_DEV_NUM			0x5
+#define VTD_FUNC_NUM			0x0
+
+#if !defined(__SIMPLE_DEVICE__)
+#define VTD_DEV(bus)		pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM))
+#else
+#define VTD_DEV(bus)		PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
+#endif

#define PCH_DEV_SLOT_LPC        0x1f
 #define  PCH_DEVFN_LPC          _PCH_DEVFN(LPC, 0)