Arthur Heymans has uploaded this change for review.
soc/intel/xeon_sp: Add a smm_region function
This reports where TSEG is located and will be used when setting up
SMM.
Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/soc/intel/xeon_sp/Makefile.inc
A src/soc/intel/xeon_sp/memmap.c
2 files changed, 28 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/46657/1
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 3bbf6b7..ea5f253 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -6,8 +6,8 @@
subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
-romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
-ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c
+romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
+ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c memmap.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
new file mode 100644
index 0000000..08ea732
--- /dev/null
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define __SIMPLE_DEVICE__
+
+#include <device/pci.h>
+#include <cpu/x86/smm.h>
+#include <soc/pci_devs.h>
+
+void smm_region(uintptr_t *start, size_t *size)
+{
+ uintptr_t tseg_base = pci_read_config32(PCI_DEV(0, VTD_DEV, VTD_FUNC),
+ VTD_TSEG_BASE_CSR);
+ uintptr_t tseg_limit = pci_read_config32(PCI_DEV(0, VTD_DEV, VTD_FUNC),
+ VTD_TSEG_LIMIT_CSR);
+
+ tseg_base &= 0xfff00000;
+ tseg_limit &= 0xfff00000;
+ /* Only the upper [31:20] bits of an address are checked against
+ * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this effectively means
+ * +1MiB for the limit.
+ */
+ tseg_limit += 1 * MiB;
+
+ *start = tseg_base;
+ *size = tseg_limit - tseg_base;
+}
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