Philipp Deppenwiese submitted this change.
soc/intel/xeon_sp: Add a smm_region function
This reports where TSEG is located and will be used when setting up
SMM.
Change-Id: I9a89cc79b08e2dcf1ffb91aa27d92c387cc93bfd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
M src/soc/intel/xeon_sp/Makefile.inc
M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
4 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc
index 40a1020..07fe3de 100644
--- a/src/soc/intel/xeon_sp/Makefile.inc
+++ b/src/soc/intel/xeon_sp/Makefile.inc
@@ -6,8 +6,9 @@
subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx
bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c
-romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c
+romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c memmap.c
ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c chip_common.c
+ramstage-y += memmap.c
ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
postcar-y += spi.c
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
index bb0f877..68dee28 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h
@@ -77,8 +77,14 @@
#define VMD_FUNC_NUM 0x05
#define MMAP_VTD_CFG_REG_DEVID 0x2024
-#define VTD_DEV 0x5
-#define VTD_FUNC 0x0
+#define VTD_DEV_NUM 0x5
+#define VTD_FUNC_NUM 0x0
+
+#if !defined(__SIMPLE_DEVICE__)
+#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM))
+#else
+#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
+#endif
#define APIC_DEV_NUM 0x05
#define APIC_FUNC_NUM 0x04
diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c
new file mode 100644
index 0000000..79ab47e
--- /dev/null
+++ b/src/soc/intel/xeon_sp/memmap.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/pci_ops.h>
+#include <cpu/x86/smm.h>
+#include <soc/pci_devs.h>
+
+void smm_region(uintptr_t *start, size_t *size)
+{
+ uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR);
+ uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR);
+
+ tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB);
+ tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB);
+ /* Only the upper [31:20] bits of an address are checked against
+ * VTD_TSEG_LIMIT_CSR[31:20] which must be below or equal, so this
+ * effectively means +1MiB for the limit.
+ */
+ tseg_limit += 1 * MiB;
+
+ *start = tseg_base;
+ *size = tseg_limit - tseg_base;
+}
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
index 6b84f70..b500c28 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h
@@ -126,8 +126,14 @@
#define HPET0_FUNC_NUM 0x00
#define MMAP_VTD_CFG_REG_DEVID 0x2024
-#define VTD_DEV 5
-#define VTD_FUNC 0
+#define VTD_DEV_NUM 0x5
+#define VTD_FUNC_NUM 0x0
+
+#if !defined(__SIMPLE_DEVICE__)
+#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM))
+#else
+#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM)
+#endif
#define PCH_DEV_SLOT_LPC 0x1f
#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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