coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer
by Jacob Garber (Code Review) 04 Nov '20

04 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46729 ) Change subject: soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer ...................................................................... soc/intel/xeon_sp: Pass IIO_RESOURCE_INSTANCE as pointer IIO_RESOURCE_INSTANCE is a large struct, so it should be passed as a constant pointer rather than making a copy. Found-by: Coverity CID 1432759 Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510 --- M src/soc/intel/xeon_sp/nb_acpi.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/46729/1 diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 1329feb..8bd8c41 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -195,16 +195,16 @@ * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, - int port, int stack, IIO_RESOURCE_INSTANCE iio_resource, uint32_t pcie_seg, + int port, int stack, const IIO_RESOURCE_INSTANCE *iio_resource, uint32_t pcie_seg, bool is_atsr, bool *first) { if (get_stack_for_port(port) != stack) return 0; - const uint32_t bus = iio_resource.StackRes[stack].BusBase; - const uint32_t dev = iio_resource.PcieInfo.PortInfo[port].Device; - const uint32_t func = iio_resource.PcieInfo.PortInfo[port].Function; + const uint32_t bus = iio_resource->StackRes[stack].BusBase; + const uint32_t dev = iio_resource->PcieInfo.PortInfo[port].Device; + const uint32_t func = iio_resource->PcieInfo.PortInfo[port].Function; const uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), PCI_VENDOR_ID); @@ -301,7 +301,7 @@ hob->PlatformData.IIO_resource[socket]; for (int p = PORT_0; p < MAX_PORTS; ++p) current += acpi_create_dmar_ds_pci_br_for_port(current, p, stack, - iio_resource, pcie_seg, false, NULL); + &iio_resource, pcie_seg, false, NULL); // Add VMD if (hob->PlatformData.VMDStackEnable[socket][stack] && @@ -365,7 +365,7 @@ if (socket == 0 && p == PORT_0) continue; current += acpi_create_dmar_ds_pci_br_for_port(current, p, - stack, iio_resource, pcie_seg, true, &first); + stack, &iio_resource, pcie_seg, true, &first); } } if (tmp != current) -- To view, visit https://review.coreboot.org/c/coreboot/+/46729 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebbb4d292f4d956e767bda28cbf20b0318586510 Gerrit-Change-Number: 46729 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/sconfig: Report which key is duplicate
by Patrick Georgi (Code Review) 04 Nov '20

04 Nov '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47103 ) Change subject: util/sconfig: Report which key is duplicate ...................................................................... util/sconfig: Report which key is duplicate It slightly helps debugging issues when you know what to look out for. Change-Id: I21eafaf8291701316aa920e458ba74535121b0a1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/sconfig/main.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/47103/1 diff --git a/util/sconfig/main.c b/util/sconfig/main.c index a7b2ce6..1fd4404 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -872,7 +872,7 @@ for (cur = *head; cur != NULL; prev = cur, cur = cur->next) { const int sort = strcmp(r->key, cur->key); if (sort == 0) { - printf("ERROR: duplicate 'register' key.\n"); + printf("ERROR: duplicate 'register' key '%s'.\n", r->key); exit(1); } if (sort < 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/47103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21eafaf8291701316aa920e458ba74535121b0a1 Gerrit-Change-Number: 47103 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulate/qemu-aarch64: Add a timestamp region
by Arthur Heymans (Code Review) 04 Nov '20

04 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47105 ) Change subject: mb/emulate/qemu-aarch64: Add a timestamp region ...................................................................... mb/emulate/qemu-aarch64: Add a timestamp region The romstage region is moved up a bit more to satisfy the MMU. Change-Id: I00c2b4972495fa669d4dc2a52f298a0e4d0cf5ff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-aarch64/memlayout.ld 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47105/1 diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld index f739ddf..cee77cd 100644 --- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld +++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld @@ -21,7 +21,8 @@ BOOTBLOCK(0x60010000, 64K) STACK(0x60020000, 62K) FMAP_CACHE(0x6002F800, 2K) - ROMSTAGE(0x60030000, 128K) + TIMESTAMP(0x60030000, 1K) + ROMSTAGE(0x60031000, 128K) TTB(0x60070000, 128K) RAMSTAGE(0x600b0000, 16M) -- To view, visit https://review.coreboot.org/c/coreboot/+/47105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00c2b4972495fa669d4dc2a52f298a0e4d0cf5ff Gerrit-Change-Number: 47105 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: clang-format of mainboard.c
by Jes Klinke (Code Review) 04 Nov '20

04 Nov '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47048 to review the following change. Change subject: mb/google/volteer: clang-format of mainboard.c ...................................................................... mb/google/volteer: clang-format of mainboard.c This CL is entirely generated by running the autmatic formatter on this one file. BUG=None TEST=abuild -t GOOGLE_VOLTEER2 -c max -x Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Signed-off-by: Jes Bodi Klinke <jbk(a)chromium.org> --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 7 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47048/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 03a78fd..b4d6676 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -51,8 +51,7 @@ return; } - if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && - cr50_is_long_interrupt_pulse_enabled()) { + if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) { printk(BIOS_INFO, "Enabling S0i3.4\n"); } else { /* @@ -75,8 +74,7 @@ base_pads = variant_base_gpio_table(&base_num); override_pads = variant_override_gpio_table(&override_num); - gpio_configure_pads_with_override(base_pads, base_num, - override_pads, override_num); + gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num); } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -84,14 +82,13 @@ bool has_usb4; /* If device doesn't have USB4 hardware, disable tbt */ - has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) || - fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); + has_usb4 = (fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN2)) + || fw_config_probe(FW_CONFIG(DB_USB, USB4_GEN3))); if (!has_usb4) - memset(params->ITbtPcieRootPortEn, - 0, - ARRAY_SIZE(params->ITbtPcieRootPortEn) * - sizeof(*params->ITbtPcieRootPortEn)); + memset(params->ITbtPcieRootPortEn, 0, + ARRAY_SIZE(params->ITbtPcieRootPortEn) + * sizeof(*params->ITbtPcieRootPortEn)); } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/47048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdd8cc2222e7af11c11df963b088ca2db07a3214 Gerrit-Change-Number: 47048 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Set tcc offset to 1
by Patrick Rudolph (Code Review) 04 Nov '20

04 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47094 ) Change subject: mb/prodrive/hermes: Set tcc offset to 1 ...................................................................... mb/prodrive/hermes: Set tcc offset to 1 Prevent early throttling when the ambient temperature is high. Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/47094/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index 04e6774..be1f4ee 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -124,7 +124,7 @@ register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Thermal - register "tcc_offset" = "6" # TCC of 94C + register "tcc_offset" = "1" # TCC of 99C # Disable S0ix -- To view, visit https://review.coreboot.org/c/coreboot/+/47094 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6881c9c0942aae3e43509170352271a74244d42 Gerrit-Change-Number: 47094 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
by Arthur Heymans (Code Review) 04 Nov '20

04 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46895 ) Change subject: soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T ...................................................................... soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size. FSP-M seems to have a very large stack usage so it would overflow other car symbols located below the coreboot stack such as timestamps and the pre-ram console, which are now fixed. TEST: boot with ocp/deltalake. Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 12 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46895/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 975afc9..28e7b83 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -27,22 +27,25 @@ config DCACHE_RAM_BASE hex - default 0xfe8b0000 + default 0xfe800000 config DCACHE_RAM_SIZE hex - default 0x170000 + default 0x1fff00 help The size of the cache-as-ram region required during bootblock - and/or romstage. + and/or romstage. FSP-T reserves the upper 0x100 for + FspReservedBuffer. config DCACHE_BSP_STACK_SIZE hex - default 0xA0000 + default 0x140000 help The amount of anticipated stack usage in CAR by bootblock and other stages. It needs to include FSP-M stack requirement and - CB romstage stack requirement. + CB romstage stack requirement. The integration documentation + says this needs to be 256KiB, but practice show this needs to + be a lot more. config CPU_MICROCODE_CBFS_LOC hex @@ -67,11 +70,13 @@ config FSP_TEMP_RAM_SIZE hex depends on FSP_USES_CB_STACK - default 0xA0000 + default 0x40000 help The amount of anticipated heap usage in CAR by FSP. Refer to Platform FSP integration guide document to know - the exact FSP requirement for Heap setup. + the exact FSP requirement for Heap setup. The FSP integration + documentation says this needs to be at least 128KiB, but practice + show this needs to be 256KiB or more. config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y -- To view, visit https://review.coreboot.org/c/coreboot/+/46895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4 Gerrit-Change-Number: 46895 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Peichao Wang (Code Review) 04 Nov '20

04 Nov '20

Peichao Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… File src/mainboard/google/dedede/variants/boten/gpio.c: https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… PS10, Line 11: 1 > Peichao […] LCFC will go on testing this CL. Tracking issue: https://partnerissuetracker.corp.google.com/issues/163100335 -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Wed, 04 Nov 2020 04:55:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Peichao Wang (Code Review) 04 Nov '20

04 Nov '20

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 04 Nov '20

04 Nov '20

Sugnan Prabhu S has uploaded a new patch set (#62) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 8 files changed, 696 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/62 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 62 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Add support to enable ISH FSP UPDs
by Bora Guvendik (Code Review) 04 Nov '20

04 Nov '20

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47104 ) Change subject: soc/intel/tigerlake: Add support to enable ISH FSP UPDs ...................................................................... soc/intel/tigerlake: Add support to enable ISH FSP UPDs Add support to enable PchIshI2cEnable and PchIshGpEnable fsp upds from devicetree. BUG=none TEST=Build mainboard using TGL. Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I3ba05e9588ba2e75c9f49168568ff9850ab67abe --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 3 files changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/47104/1 diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 492d6fd4..f902449 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -109,6 +109,14 @@ hex default 0x10000 +config MAX_ISH_GP_PINS + int + default 8 + +config MAX_ISH_I2C_CONTROLLERS + int + default 3 + config MAX_ROOT_PORTS int default 12 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index f752b5f..8462571 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -492,6 +492,10 @@ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; + + /* Ish related */ + uint8_t PchIshGpEnable[CONFIG_MAX_ISH_GP_PINS]; + uint8_t PchIshI2cEnable[CONFIG_MAX_ISH_I2C_CONTROLLERS]; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 887241b..c209230 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -188,6 +188,13 @@ params->PcieRpHotPlug[i] = config->PcieRpHotPlug[i]; } + /* Ish Configs */ + for (i = 0; i < CONFIG_MAX_ISH_GP_PINS; i++) + params->PchIshGpEnable[i] = config->PchIshGpEnable[i]; + + for (i = 0; i < CONFIG_MAX_ISH_I2C_CONTROLLERS; i++) + params->PchIshI2cEnable[i] = config->PchIshI2cEnable[i]; + /* Enable ClkReqDetect for enabled port */ memcpy(params->PcieRpClkReqDetect, config->PcieRpClkReqDetect, sizeof(config->PcieRpClkReqDetect)); -- To view, visit https://review.coreboot.org/c/coreboot/+/47104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ba05e9588ba2e75c9f49168568ff9850ab67abe Gerrit-Change-Number: 47104 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit November 2020