Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47105 )
Change subject: mb/emulate/qemu-aarch64: Add a timestamp region
......................................................................
mb/emulate/qemu-aarch64: Add a timestamp region
The romstage region is moved up a bit more to satisfy the MMU.
Change-Id: I00c2b4972495fa669d4dc2a52f298a0e4d0cf5ff
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/emulation/qemu-aarch64/memlayout.ld
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/47105/1
diff --git a/src/mainboard/emulation/qemu-aarch64/memlayout.ld b/src/mainboard/emulation/qemu-aarch64/memlayout.ld
index f739ddf..cee77cd 100644
--- a/src/mainboard/emulation/qemu-aarch64/memlayout.ld
+++ b/src/mainboard/emulation/qemu-aarch64/memlayout.ld
@@ -21,7 +21,8 @@
BOOTBLOCK(0x60010000, 64K)
STACK(0x60020000, 62K)
FMAP_CACHE(0x6002F800, 2K)
- ROMSTAGE(0x60030000, 128K)
+ TIMESTAMP(0x60030000, 1K)
+ ROMSTAGE(0x60031000, 128K)
TTB(0x60070000, 128K)
RAMSTAGE(0x600b0000, 16M)
--
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Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46895 )
Change subject: soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
......................................................................
soc/intel/xeon_sp/cpx: Align coreboot CAR symbols to FSP-T
The CAR set up by FSP-T is at base 0xfe800000 and has a 0x200000 size.
FSP-M seems to have a very large stack usage so it would overflow
other car symbols located below the coreboot stack such as timestamps
and the pre-ram console, which are now fixed.
TEST: boot with ocp/deltalake.
Change-Id: I886f9391ad79fcfa0724109393e3781a08d954b4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/xeon_sp/cpx/Kconfig
1 file changed, 12 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/46895/1
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 975afc9..28e7b83 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -27,22 +27,25 @@
config DCACHE_RAM_BASE
hex
- default 0xfe8b0000
+ default 0xfe800000
config DCACHE_RAM_SIZE
hex
- default 0x170000
+ default 0x1fff00
help
The size of the cache-as-ram region required during bootblock
- and/or romstage.
+ and/or romstage. FSP-T reserves the upper 0x100 for
+ FspReservedBuffer.
config DCACHE_BSP_STACK_SIZE
hex
- default 0xA0000
+ default 0x140000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages. It needs to include FSP-M stack requirement and
- CB romstage stack requirement.
+ CB romstage stack requirement. The integration documentation
+ says this needs to be 256KiB, but practice show this needs to
+ be a lot more.
config CPU_MICROCODE_CBFS_LOC
hex
@@ -67,11 +70,13 @@
config FSP_TEMP_RAM_SIZE
hex
depends on FSP_USES_CB_STACK
- default 0xA0000
+ default 0x40000
help
The amount of anticipated heap usage in CAR by FSP.
Refer to Platform FSP integration guide document to know
- the exact FSP requirement for Heap setup.
+ the exact FSP requirement for Heap setup. The FSP integration
+ documentation says this needs to be at least 128KiB, but practice
+ show this needs to be 256KiB or more.
config SOC_INTEL_COMMON_BLOCK_P2SB
def_bool y
--
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Peichao Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 )
Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence
......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede…
File src/mainboard/google/dedede/variants/boten/gpio.c:
https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede…
PS10, Line 11: 1
> Peichao […]
LCFC will go on testing this CL. Tracking issue: https://partnerissuetracker.corp.google.com/issues/163100335
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Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence
......................................................................
Patch Set 10: -Code-Review
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Sugnan Prabhu S has uploaded a new patch set (#62) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 )
Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT
......................................................................
soc/intel/basecode: Add support for updating ucode loaded via FIT
Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch)
loading mechanism patches the microcode before CPU reset. In the current
Chromebooks, field updatable FW has to be first verified by vboot. Since
the MCU is loaded before reset, vboot cannot verify the same and hence we
end up restricting FIT based MCU update only from RO.
This patch implements a scheme which will allow chromebooks to update
MCU in the field.
Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their
own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin)
which resides in RO section. This will be used in the recovery scenario and
also when booting with top-swap disabled i.e, RTC reset.
Second bootblock (Normal mode) is identical to the first one except the FIT.
Insert an additional pointer to a MCU that will reside in a staging area.
Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address
of the staging area into FIT.
Top swap control bit in RTC BUC register (0x3414) is used to switch between
the two bootblocks.
Reserve a region in the FMAP which is equal to or greater than the MCU size
specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is
192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will
be copied to this region during boot. Protect this staging area with a FPR.
Basic update flow:
In non-recovery mode, Once a slot has been selected and loaded, check if the
current slot MCU and RW staging MCU are same. If not, update the staging area
with the MCU found in the current slot and reset the system.
Also, make sure that the top-swap is enabled in normal/developer mode and
disabled in recovery mode.
In order to enable the update feature:
* The mainboard chromeos.fmd should include a new region for staging MCU
e.g, RW_UCODE_STAGED.
* Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE.
* Implement a call to check_and_update_ucode() and handle the failure
appropriately.
Add documentation to describing the MCU update procedure.
Update config name and Makefile.inc
TODO: Since this update mechanism is dealing mostly with a single MCU
it is best suited for systems where the CPU is soldered down and not
replaceable (socketed). Extend the update mechanism to systems where the
CPU is replaceable, by including multiple MCU for different CPUs.
TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate
shellball with a newer MCU and perform an update. Make sure that the
currently loaded microcode version matches the one in firmwareupdate.
Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com>
Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com>
---
M Documentation/soc/intel/index.md
A Documentation/soc/intel/ucode_update/flash_layout.svg
A Documentation/soc/intel/ucode_update/microcode_update_model.md
M Makefile.inc
A src/soc/intel/common/basecode/fw_update/Kconfig
A src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
8 files changed, 696 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/62
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 )
Change subject: console: Allow VPD to disable an otherwise enabled coreboot console
......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG@18
PS4, Line 18: entry is added.
> This demand to customize binaries pops up rather often lately. I was […]
What do you mean with "a section"... like, just a special ELF section, with some header magic so tools can find and hack around in it on the completed binary?
I mean, I find that kind of silly because I feel at that point people can also just change Kconfigs and recompile. But if that's really such a big barrier for enough people then yeah, I guess, that's an option. It definitely solves all the "big, early dependencies" problems.
Of course this won't play nice with verification schemes (whereas VPD and the CMOS option table do), and it would also cause issues with compressed stages. I guess with enough work in cbfstool you could decompress a stage on the fly to muck with it, but you still run the risk that the recompressed changed stage will not fit in the space taken up by the old version anymore.
I still kinda feel like all these cases where this had come up recently would be best served with the existing CMOS option table solution (I haven't heard from anyone caring about it on a non-x86 board yet).
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