coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Julius Werner (Code Review) 04 Nov '20

04 Nov '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG@18 PS4, Line 18: entry is added. > This demand to customize binaries pops up rather often lately. I was […] What do you mean with "a section"... like, just a special ELF section, with some header magic so tools can find and hack around in it on the completed binary? I mean, I find that kind of silly because I feel at that point people can also just change Kconfigs and recompile. But if that's really such a big barrier for enough people then yeah, I guess, that's an option. It definitely solves all the "big, early dependencies" problems. Of course this won't play nice with verification schemes (whereas VPD and the CMOS option table do), and it would also cause issues with compressed stages. I guess with enough work in cbfstool you could decompress a stage on the fly to muck with it, but you still run the risk that the recompressed changed stage will not fit in the space taken up by the old version anymore. I still kinda feel like all these cases where this had come up recently would be best served with the existing CMOS option table solution (I haven't heard from anyone caring about it on a non-x86 board yet). -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Wed, 04 Nov 2020 00:26:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/volteer: Log EC events in case of S0ix resume
by Furquan Shaikh (Code Review) 03 Nov '20

03 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47142 ) Change subject: mb/google/volteer: Log EC events in case of S0ix resume ...................................................................... mb/google/volteer: Log EC events in case of S0ix resume This change adds the callback `elog_gsmi_cb_mainboard_log_wake_source()` to volteer to enable logging of EC events in case of S0ix resume. BUG=b:172272078 BRANCH=volteer TEST=Verified that EC events are logged correctly for S0ix resume: 11 | 2020-11-02 14:11:05 | S0ix Enter 12 | 2020-11-02 14:11:08 | S0ix Exit 13 | 2020-11-02 14:11:08 | Wake Source | Power Button | 0 14 | 2020-11-02 14:11:08 | EC Event | Power Button 15 | 2020-11-02 14:11:17 | S0ix Enter 16 | 2020-11-02 14:11:21 | S0ix Exit 17 | 2020-11-02 14:11:21 | Wake Source | GPE # | 112 18 | 2020-11-02 14:11:21 | EC Event | Lid Open Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I7aa9dc2470da3226925927f2a0cc39fdd426e3b1 --- M src/mainboard/google/volteer/smihandler.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47142/1 diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c index 5b3e38c..adb60fe 100644 --- a/src/mainboard/google/volteer/smihandler.c +++ b/src/mainboard/google/volteer/smihandler.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <cpu/x86/smm.h> +#include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/smm.h> +#include <elog.h> #include <intelblocks/smihandler.h> #include <variant/ec.h> @@ -22,3 +24,8 @@ MAINBOARD_EC_SMI_EVENTS); return 0; } + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7aa9dc2470da3226925927f2a0cc39fdd426e3b1 Gerrit-Change-Number: 47142 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix
by Furquan Shaikh (Code Review) 03 Nov '20

03 Nov '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47141 ) Change subject: soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix ...................................................................... soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix This change adds elog.c to smm-y for Tiger lake and Jasper Lake platforms to enable the logging of wake sources in eventlog for S0ix. BUG=b:172272078,b:169731044 BRANCH=volteer TEST=Verified on volteer that wake sources are correctly logged for S0ix: 8 | 2020-11-02 13:54:27 | S0ix Enter 9 | 2020-11-02 13:54:33 | S0ix Exit 10 | 2020-11-02 13:54:33 | Wake Source | RTC Alarm | 0 11 | 2020-11-02 13:54:49 | S0ix Enter 12 | 2020-11-02 13:54:54 | S0ix Exit 13 | 2020-11-02 13:54:54 | Wake Source | Power Button | 0 14 | 2020-11-02 13:55:04 | S0ix Enter 15 | 2020-11-02 13:55:10 | S0ix Exit 16 | 2020-11-02 13:55:10 | Wake Source | GPE # | 112 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6 --- M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/tigerlake/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/47141/1 diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 1cba218..209d8a2 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -51,6 +51,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c verstage-y += gpio.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index c4f71c7..a25d0a4 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -50,6 +50,7 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c +smm-y += elog.c verstage-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/47141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1c40dfba6c82ca45a21d35c5a2725e4d30855d6 Gerrit-Change-Number: 47141 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: sb/intel/lynxpoint/sata.c: Don't enable Bus Master
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47031 ) Change subject: sb/intel/lynxpoint/sata.c: Don't enable Bus Master ...................................................................... sb/intel/lynxpoint/sata.c: Don't enable Bus Master Bus Master is not required and reference code does not set it. Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/sata.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/47031/1 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 4174e1f..d8eb2a8 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -51,9 +51,8 @@ /* SATA configuration */ - /* Enable BARs */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + /* Enable memory space decoding for ABAR */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO); printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/47031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a84da5b712e6fa569ad9f412c440afeb6a8cc5d Gerrit-Change-Number: 47031 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Michael Niewöhner (Code Review) 03 Nov '20

03 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46470/4/src/soc/intel/common/acpi/… File src/soc/intel/common/acpi/lpit.asl: https://review.coreboot.org/c/coreboot/+/46470/4/src/soc/intel/common/acpi/… PS4, Line 3: PEPD_DSM_ARG2_ENUM_FUNCTIONS > I think it would be good to have LPI(Low Power Idle) in the name to make it clear that it is specifi […] yeah, sounds good -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Nov 2020 22:42:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/block/acpi: add code for CPPC entries generation
by Tim Wawrzynczak (Code Review) 03 Nov '20

03 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45535 ) Change subject: soc/intel/block/acpi: add code for CPPC entries generation ...................................................................... Patch Set 32: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/45535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fcc2d0d7c6b6f35f8dd011f55dab8469be99d47 Gerrit-Change-Number: 45535 Gerrit-PatchSet: 32 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Elyes HAOUAS Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt Delco <delco(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 03 Nov 2020 22:40:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Michael Niewöhner (Code Review) 03 Nov '20

03 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46470/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46470/4//COMMIT_MSG@7 PS4, Line 7: PEPD > `PNP0D80` is the class ID for the Power Management Controller, but `INT33A1` is called "Intel Power […] Oh, and it's the name used in refcode and by IBVs -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Nov 2020 22:34:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Michael Niewöhner (Code Review) 03 Nov '20

03 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46470/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46470/4//COMMIT_MSG@7 PS4, Line 7: PEPD > Can we instead rename this to PMCD? PEPD is something very Windows-specific and I see it being used […] `PNP0D80` is the class ID for the Power Management Controller, but `INT33A1` is called "Intel Power Engine" by ACPICA: http://web.mit.edu/freebsd/head/sys/contrib/dev/acpica/common/ahids.c -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Nov 2020 22:32:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 03 Nov '20

03 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47138/3//COMMIT_MSG@7 PS3, Line 7: fix > it *is* broken atm reworded as discussed on irc -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 03 Nov 2020 22:28:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi,mb/*: replace LPID with PEPD
by Michael Niewöhner (Code Review) 03 Nov '20

03 Nov '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, Karthikeyan Ramasubramanian, Venkata Krishna Nimmagadda, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46471 to look at the new patch set (#8). Change subject: soc/intel/common/acpi,mb/*: replace LPID with PEPD ...................................................................... soc/intel/common/acpi,mb/*: replace LPID with PEPD Replace the two duplicate LPID with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 uuid on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/google/deltaur/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/cannonlake/acpi/southbridge.asl D src/soc/intel/common/acpi/lpit.asl A src/soc/intel/common/block/acpi/acpi/pep.asl D src/soc/intel/common/block/acpi/acpi/pmc.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 13 files changed, 133 insertions(+), 160 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46471/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/46471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Gerrit-Change-Number: 46471 Gerrit-PatchSet: 8 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020