coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 03 Nov '20

03 Nov '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Christian Walter, Paul Menzel, Tim Wawrzynczak, Angel Pons, Subrata Banik, Arthur Heymans, Patrick Rudolph, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47138 to look at the new patch set (#4). Change subject: soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards ...................................................................... soc/intel/common/acpi: work around Windows crash on S0ix-enabled boards Windows does not comply with the Low Power Idle S0 specification and crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does not return at least one device constraint, even when function 1 is announced as being not available by the enum function. Returning an empty package does not work. At least the following Windows versions were verified to be affected: - Windows 8.1 x64, release 6.3.9600 - Windoes 10 x64, version 1809, build 17763.379 - Windows 10 x64, version 1903, build 18362.53 - Windows 10 x64, version 2004, build 19041.508 - Windows 10 x64, version 20H2 / 2009, build 19042.450 To make Windows work on S0ix-enabled boards, return a dummy constraint package with a disabled dummy device. Since the device constraints are only used for debugging low power states in Linux and probably also in Windows, there shouldn't be any negative effect to S0ix. Real device constraint entries could be added at a later point, if needed. Test: no bluescreen anymore on Clevo L140CU on all Windows versions listed above and S0ix gets detected in `powercfg -a`. Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/acpi/lpit.asl 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47138/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 03 Nov '20

03 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/47138/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47138/3//COMMIT_MSG@7 PS3, Line 7: fix > Rather `prevent` because it's not broken atm. […] it *is* broken atm -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 03 Nov 2020 22:04:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Furquan Shaikh (Code Review) 03 Nov '20

03 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/46470/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46470/4//COMMIT_MSG@7 PS4, Line 7: PEPD Can we instead rename this to PMCD? PEPD is something very Windows-specific and I see it being used in Intel documents specific to Windows only. On the other hand, both Microsoft documentation(https://docs.microsoft.com/en-us/windows-hardware/drivers/bri… and Linux kernel(https://github.com/torvalds/linux/blob/master/drivers/acpi/sleep.c#L… refer to this class of devices as "System Power Management Controller". I think it would be good to use the same in coreboot as well? i.e. PMCD - Power Management Controller Device. https://review.coreboot.org/c/coreboot/+/46470/4/src/soc/intel/common/acpi/… File src/soc/intel/common/acpi/lpit.asl: https://review.coreboot.org/c/coreboot/+/46470/4/src/soc/intel/common/acpi/… PS4, Line 3: PEPD_DSM_ARG2_ENUM_FUNCTIONS I think it would be good to have LPI(Low Power Idle) in the name to make it clear that it is specific to Low Power S0 Idle. I think we can drop ARG2 since that is not really helpful. PMCD_DSM_LPI_ENUM_FUNCTIONS PMCD_DSM_LPI_GET_DEVICE_CONSTRAINTS and so on -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Nov 2020 21:48:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards
by Nico Huber (Code Review) 03 Nov '20

03 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/c/coreboot/+/47138/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47138/1//COMMIT_MSG@9 PS1, Line 9: Windows > I will test more and add the tested versions Done https://review.coreboot.org/c/coreboot/+/47138/1//COMMIT_MSG@22 PS1, Line 22: Windows > It’d be great if you specified the version, you tested with. Done https://review.coreboot.org/c/coreboot/+/47138/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/47138/3//COMMIT_MSG@7 PS3, Line 7: fix Rather `prevent` because it's not broken atm.? https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/… File src/soc/intel/common/acpi/lpit.asl: https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/… PS1, Line 26: debugging > Also see comment from Tim at line 38 here: https://review.coreboot. […] That doesn't explain why you want to say that here in a comment. The truth would be something along "[...] device constraints for low power states (may be used for debugging [in] Linux)." IMO, too much imple- mentation specific information. So why not leave it to what the spec intended? -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 3 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Tue, 03 Nov 2020 21:02:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: console: Allow VPD to disable an otherwise enabled coreboot console
by Nico Huber (Code Review) 03 Nov '20

03 Nov '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45208 ) Change subject: console: Allow VPD to disable an otherwise enabled coreboot console ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/45208/4//COMMIT_MSG@18 PS4, Line 18: entry is added. > No, that's not true. […] This demand to customize binaries pops up rather often lately. I was wondering if we can find a generic and efficient solution. From the top of my head: A section per stage reserved for a handful of key+value pairs and use that as a low-priority backend for get_option() (or a new, saner API ^^). Ofc, systems where the bootblock is already too big wouldn't benefit. On the positive side, the data would be implicitly accessible just like the code (i.e. memory mapped or automatically loaded into SRAM/CAR/DRAM). -- To view, visit https://review.coreboot.org/c/coreboot/+/45208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f1f5c45e5ea889176d04e0db438ca2aa7c536ee Gerrit-Change-Number: 45208 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Dossym Nurmukhanov <dossym(a)google.com> Gerrit-Reviewer: Greg Edelston <gredelston(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 20:21:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration
by Tim Wawrzynczak (Code Review) 03 Nov '20

03 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47010 ) Change subject: mb/google/dedede/var/drawcia: Probe and enable DPTF configuration ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf166a2e36fa5775e2dea7c1adcae843cc143d32 Gerrit-Change-Number: 47010 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Evan Green <evgreen(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 19:27:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Karthik Ramasubramanian (Code Review) 03 Nov '20

03 Nov '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… File src/mainboard/google/dedede/variants/boten/gpio.c: https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… PS10, Line 11: 1 > Dear Furquan and Karthik, if set its value equal 0, LTE module can not work, we have do the experime […] Peichao 1) ACPI methods are going to do the same thing as what these GPIO configurations are doing. 2) GPIOs will toggle to low once during the PO because of CSE FW Sync and then go back to high. This is not expected by the LTE module. 3) Configuring both FCPO and RESET as high here will not help to meet the LTE module's other power sequence requirements. -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 03 Nov 2020 19:16:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Relocate PCH ACPI files
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46754 ) Change subject: soc/intel/broadwell: Relocate PCH ACPI files ...................................................................... soc/intel/broadwell: Relocate PCH ACPI files Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/auron/dsdt.asl M src/mainboard/google/jecht/dsdt.asl M src/mainboard/intel/wtm2/dsdt.asl M src/mainboard/purism/librem_bdw/dsdt.asl R src/soc/intel/broadwell/pch/acpi/adsp.asl R src/soc/intel/broadwell/pch/acpi/device_nvs.asl R src/soc/intel/broadwell/pch/acpi/ehci.asl R src/soc/intel/broadwell/pch/acpi/globalnvs.asl R src/soc/intel/broadwell/pch/acpi/gpio.asl R src/soc/intel/broadwell/pch/acpi/hda.asl R src/soc/intel/broadwell/pch/acpi/irqlinks.asl R src/soc/intel/broadwell/pch/acpi/lpc.asl R src/soc/intel/broadwell/pch/acpi/pch.asl R src/soc/intel/broadwell/pch/acpi/pcie.asl R src/soc/intel/broadwell/pch/acpi/pcie_port.asl R src/soc/intel/broadwell/pch/acpi/sata.asl R src/soc/intel/broadwell/pch/acpi/serialio.asl R src/soc/intel/broadwell/pch/acpi/smbus.asl R src/soc/intel/broadwell/pch/acpi/xhci.asl 19 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/46754/1 diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index 32c71de..a61a669 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -16,7 +16,7 @@ #include "acpi/thermal.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -25,7 +25,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 3746d4b..6af99b4 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -17,7 +17,7 @@ #include <variant/acpi/thermal.asl> // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> } } diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index b3b2ca6..c842e8b 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -17,7 +17,7 @@ #include "acpi/platform.asl" // global NVS and variables - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> // CPU #include <cpu/intel/common/acpi/cpu.asl> @@ -26,7 +26,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> } } diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index 4d81e15..a4b5bd8 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -13,7 +13,7 @@ #include <soc/intel/broadwell/acpi/platform.asl> /* Global NVS and variables */ - #include <soc/intel/broadwell/acpi/globalnvs.asl> + #include <soc/intel/broadwell/pch/acpi/globalnvs.asl> /* CPU */ #include <cpu/intel/common/acpi/cpu.asl> @@ -22,7 +22,7 @@ Device (PCI0) { #include <soc/intel/broadwell/acpi/systemagent.asl> - #include <soc/intel/broadwell/acpi/pch.asl> + #include <soc/intel/broadwell/pch/acpi/pch.asl> } } diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/pch/acpi/adsp.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/adsp.asl rename to src/soc/intel/broadwell/pch/acpi/adsp.asl diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/pch/acpi/device_nvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/device_nvs.asl rename to src/soc/intel/broadwell/pch/acpi/device_nvs.asl diff --git a/src/soc/intel/broadwell/acpi/ehci.asl b/src/soc/intel/broadwell/pch/acpi/ehci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/ehci.asl rename to src/soc/intel/broadwell/pch/acpi/ehci.asl diff --git a/src/soc/intel/broadwell/acpi/globalnvs.asl b/src/soc/intel/broadwell/pch/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/globalnvs.asl rename to src/soc/intel/broadwell/pch/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/pch/acpi/gpio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/gpio.asl rename to src/soc/intel/broadwell/pch/acpi/gpio.asl diff --git a/src/soc/intel/broadwell/acpi/hda.asl b/src/soc/intel/broadwell/pch/acpi/hda.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/hda.asl rename to src/soc/intel/broadwell/pch/acpi/hda.asl diff --git a/src/soc/intel/broadwell/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/irqlinks.asl rename to src/soc/intel/broadwell/pch/acpi/irqlinks.asl diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/pch/acpi/lpc.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/lpc.asl rename to src/soc/intel/broadwell/pch/acpi/lpc.asl diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/pch/acpi/pch.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pch.asl rename to src/soc/intel/broadwell/pch/acpi/pch.asl diff --git a/src/soc/intel/broadwell/acpi/pcie.asl b/src/soc/intel/broadwell/pch/acpi/pcie.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie.asl rename to src/soc/intel/broadwell/pch/acpi/pcie.asl diff --git a/src/soc/intel/broadwell/acpi/pcie_port.asl b/src/soc/intel/broadwell/pch/acpi/pcie_port.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/pcie_port.asl rename to src/soc/intel/broadwell/pch/acpi/pcie_port.asl diff --git a/src/soc/intel/broadwell/acpi/sata.asl b/src/soc/intel/broadwell/pch/acpi/sata.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/sata.asl rename to src/soc/intel/broadwell/pch/acpi/sata.asl diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/serialio.asl rename to src/soc/intel/broadwell/pch/acpi/serialio.asl diff --git a/src/soc/intel/broadwell/acpi/smbus.asl b/src/soc/intel/broadwell/pch/acpi/smbus.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/smbus.asl rename to src/soc/intel/broadwell/pch/acpi/smbus.asl diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/pch/acpi/xhci.asl similarity index 100% rename from src/soc/intel/broadwell/acpi/xhci.asl rename to src/soc/intel/broadwell/pch/acpi/xhci.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/46754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f87085c70149d02c544e2d43e1bdb58c7502d6d Gerrit-Change-Number: 46754 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell: Move smmrelocate.c MSR definitions to header
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46733 ) Change subject: cpu/intel/haswell: Move smmrelocate.c MSR definitions to header ...................................................................... cpu/intel/haswell: Move smmrelocate.c MSR definitions to header Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change. Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/smmrelocate.c 2 files changed, 20 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/46733/1 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index e0e1e1c..9349a3d 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -76,6 +76,26 @@ #define MSR_CONFIG_TDP_CONTROL 0x64b #define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) + +#define MSR_PRMRR_PHYS_BASE 0x1f4 +#define MSR_PRMRR_PHYS_MASK 0x1f5 +#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 +#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 + +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) + +/* SMM save state MSRs */ +#define SMBASE_MSR 0xc20 +#define IEDBASE_MSR 0xc22 + +/* MTRR_CAP_MSR bit definitions */ +#define SMRR_SUPPORTED (1 << 11) +#define PRMRR_SUPPORTED (1 << 12) + /* P-state configuration */ #define PSS_MAX_ENTRIES 8 #define PSS_RATIO_STEP 2 diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 2fc20aa..9e3554f 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -17,22 +17,6 @@ #include <smp/node.h> #include "haswell.h" -#define MSR_PRMRR_PHYS_BASE 0x1f4 -#define MSR_PRMRR_PHYS_MASK 0x1f5 -#define MSR_UNCORE_PRMRR_PHYS_BASE 0x2f4 -#define MSR_UNCORE_PRMRR_PHYS_MASK 0x2f5 -#define SMM_MCA_CAP_MSR 0x17d -#define SMM_CPU_SVRSTR_BIT 57 -#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) -#define SMM_FEATURE_CONTROL_MSR 0x4e0 -#define SMM_CPU_SAVE_EN (1 << 1) -/* SMM save state MSRs */ -#define SMBASE_MSR 0xc20 -#define IEDBASE_MSR 0xc22 - -#define SMRR_SUPPORTED (1 << 11) -#define PRMRR_SUPPORTED (1 << 12) - static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, struct smm_relocation_params *relo_params) -- To view, visit https://review.coreboot.org/c/coreboot/+/46733 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia271718477ea227b9ba7e836b0abe02264778129 Gerrit-Change-Number: 46733 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "broadwell: Switch to using common ACPI _SWS code"
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Hello build bot (Jenkins), Patrick Georgi, Duncan Laurie, Paul Menzel, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46734 to review the following change. Change subject: Revert "broadwell: Switch to using common ACPI _SWS code" ...................................................................... Revert "broadwell: Switch to using common ACPI _SWS code" This reverts commit 81a4c85acf664156bb68807f681cd40928bf8267. Reason for revert: Blocks merging Haswell and Broadwell together. Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/acpi/platform.asl M src/soc/intel/broadwell/ramstage.c 3 files changed, 64 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/46734/1 diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 6561fe2..e01d559 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -42,7 +42,6 @@ select UDELAY_TSC select SOC_INTEL_COMMON select HAVE_INTEL_FIRMWARE - select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE config BOOTBLOCK_CPU_INIT string diff --git a/src/soc/intel/broadwell/acpi/platform.asl b/src/soc/intel/broadwell/acpi/platform.asl index c00edeb..d302720 100644 --- a/src/soc/intel/broadwell/acpi/platform.asl +++ b/src/soc/intel/broadwell/acpi/platform.asl @@ -18,9 +18,6 @@ * Foundation, Inc. */ -/* Enable ACPI _SWS methods */ -#include <soc/intel/common/acpi/acpi_wake_source.asl> - /* The APM port can be used for generating software SMIs */ OperationRegion (APMP, SystemIO, 0xb2, 2) @@ -74,3 +71,21 @@ { Return (Package (){ 0, 0 }) } + +Scope (\_SB) +{ + Method (_SWS) + { + /* Index into PM1 for device that caused wake */ + Return (\PM1I) + } +} + +Scope (\_GPE) +{ + Method (_SWS) + { + /* Index into GPE for device that caused wake */ + Return (\GPEI) + } +} diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index c8fb6ed..e699e02 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -27,23 +27,56 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/intel/broadwell/chip.h> -#include <soc/intel/common/acpi.h> -/* Save wake source information for calculating ACPI _SWS values */ -int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) +/* Save bit index for PM1_STS and GPE_STS for ACPI _SWS */ +static void save_acpi_wake_source(global_nvs_t *gnvs) { struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); - static uint32_t gpe0_sts[GPE0_REG_MAX]; - int i; + uint16_t pm1; + int gpe_reg; - *pm1 = ps->pm1_sts & ps->pm1_en; + if (!ps) + return; - /* Mask off GPE0 status bits that are not enabled */ - *gpe0 = &gpe0_sts[0]; - for (i = 0; i < GPE0_REG_MAX; i++) - gpe0_sts[i] = ps->gpe0_sts[i] & ps->gpe0_en[i]; + pm1 = ps->pm1_sts & ps->pm1_en; - return GPE0_REG_MAX; + /* Scan for first set bit in PM1 */ + for (gnvs->pm1i = 0; gnvs->pm1i < 16; gnvs->pm1i++) { + if (pm1 & 1) + break; + pm1 >>= 1; + } + + /* If unable to determine then return -1 */ + if (gnvs->pm1i >= 16) + gnvs->pm1i = -1; + + /* Scan for first set bit in GPE registers */ + gnvs->gpei = -1; + for (gpe_reg = 0; gpe_reg < GPE0_REG_MAX; gpe_reg++) { + u32 gpe = ps->gpe0_sts[gpe_reg] & ps->gpe0_en[gpe_reg]; + int start = gpe_reg * GPE0_REG_SIZE; + int end = start + GPE0_REG_SIZE; + + if (gpe == 0) { + if (!gnvs->gpei) + gnvs->gpei = end; + continue; + } + + for (gnvs->gpei = start; gnvs->gpei < end; gnvs->gpei++) { + if (gpe & 1) + break; + gpe >>= 1; + } + } + + /* If unable to determine then return -1 */ + if (gnvs->gpei >= (GPE0_REG_MAX * GPE0_REG_SIZE)) + gnvs->gpei = -1; + + printk(BIOS_DEBUG, "ACPI _SWS is PM1 Index %lld GPE Index %lld\n", + gnvs->pm1i, gnvs->gpei); } static void s3_resume_prepare(void) @@ -56,6 +89,8 @@ if (!acpi_is_wakeup_s3()) memset(gnvs, 0, sizeof(global_nvs_t)); + else + save_acpi_wake_source(gnvs); } void broadwell_init_pre_device(void *chip_info) -- To view, visit https://review.coreboot.org/c/coreboot/+/46734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29c4ad9174ab84c7e9111daa0491ede9e1d639b4 Gerrit-Change-Number: 46734 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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