coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: [TESTONLY] smm loader v2 fixups for B85M Pro4
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44174 ) Change subject: [TESTONLY] smm loader v2 fixups for B85M Pro4 ...................................................................... [TESTONLY] smm loader v2 fixups for B85M Pro4 Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/smm/smm_module_loaderv2.c M src/include/cpu/x86/smm.h M src/mainboard/asrock/b85m_pro4/Kconfig 4 files changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/44174/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index caed8f4..375c94e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -726,8 +726,18 @@ * the location of the new SMBASE. If using SMM modules then this * calculation needs to match that of the module loader. */ - perm_smbase = mp_state.perm_smbase; - perm_smbase -= cpu * runtime->save_state_size; + if (CONFIG(X86_SMM_LOADER_VERSION2)) { + perm_smbase = smm_get_cpu_smbase(cpu); + mp_state.perm_smbase = perm_smbase; + + if (!perm_smbase) { + printk(BIOS_ERR, "%s: bad SMBASE for CPU %d\n", __func__, cpu); + return; + } + } else { + perm_smbase = mp_state.perm_smbase; + perm_smbase -= cpu * runtime->save_state_size; + } printk(BIOS_DEBUG, "New SMBASE 0x%08lx\n", perm_smbase); diff --git a/src/cpu/x86/smm/smm_module_loaderv2.c b/src/cpu/x86/smm/smm_module_loaderv2.c index c084f74..e6ccfdf 100644 --- a/src/cpu/x86/smm/smm_module_loaderv2.c +++ b/src/cpu/x86/smm/smm_module_loaderv2.c @@ -173,7 +173,7 @@ * input: cpu_num - cpu number which is used as an index into the * map to return the smbase */ -int smm_get_cpu_smbase(unsigned int cpu_num) +u32 smm_get_cpu_smbase(unsigned int cpu_num) { if (cpu_num < CONFIG_MAX_CPUS) { if (cpus[cpu_num].active) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 7838223..084d150 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -149,21 +149,19 @@ struct smm_runtime *runtime; /* The following are only used by X86_SMM_LOADER_VERSION2 */ - #if CONFIG(X86_SMM_LOADER_VERSION2) +#if CONFIG(X86_SMM_LOADER_VERSION2) unsigned int smm_entry; unsigned int smm_main_entry_offset; unsigned int smram_start; unsigned int smram_end; - #endif +#endif }; /* Both of these return 0 on success, < 0 on failure. */ int smm_setup_relocation_handler(struct smm_loader_params *params); int smm_load_module(void *smram, size_t size, struct smm_loader_params *params); -#if CONFIG(X86_SMM_LOADER_VERSION2) -int smm_get_cpu_smbase(unsigned int cpu_num); -#endif +u32 smm_get_cpu_smbase(unsigned int cpu_num); /* Backup and restore default SMM region. */ void *backup_default_smm_area(void); diff --git a/src/mainboard/asrock/b85m_pro4/Kconfig b/src/mainboard/asrock/b85m_pro4/Kconfig index dc65120..2afc334 100644 --- a/src/mainboard/asrock/b85m_pro4/Kconfig +++ b/src/mainboard/asrock/b85m_pro4/Kconfig @@ -17,6 +17,7 @@ select SERIRQ_CONTINUOUS_MODE select SOUTHBRIDGE_INTEL_LYNXPOINT select SUPERIO_NUVOTON_NCT6776 + select X86_SMM_LOADER_VERSION2 config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/44174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I754c661fbad0bc5fbddfab9747607e664ad1e2b6 Gerrit-Change-Number: 44174 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: configs/config.asrock_b85m_pro4...: Clarify its purpose
by Angel Pons (Code Review) 03 Nov '20

03 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47068 ) Change subject: configs/config.asrock_b85m_pro4...: Clarify its purpose ...................................................................... configs/config.asrock_b85m_pro4...: Clarify its purpose The purpose of this config is to build-test the individual options, not their combination. So, for instance, if it would be hard to keep options x, y and z build together in the future, this config shouldn't block a change but should instead be adapted, e.g. split into multiple chunks. Change-Id: Ibd8f6513fae6cd02fcf889d2510dc7e0a97ce40c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/47068/1 diff --git a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 index 11a27bf..62169b5 100644 --- a/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 +++ b/configs/config.asrock_b85m_pro4.debug_smmstore_hotplug_gcov_ubsan_em100 @@ -1,4 +1,7 @@ -# Not meant for actual use. Exercises, among other things: +# Not meant for actual use, but rather to build-test individual options. +# If keeping this combination of options buildable becomes too hard in +# the future, then this config can be split into several smaller chunks. +# Exercises, among other things: # + Code coverage # + UBSAN # + Debug options -- To view, visit https://review.coreboot.org/c/coreboot/+/47068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd8f6513fae6cd02fcf889d2510dc7e0a97ce40c Gerrit-Change-Number: 47068 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: driver/usb/acpi: Add power resources for devices on USB ports
by Furquan Shaikh (Code Review) 03 Nov '20

03 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46713 ) Change subject: driver/usb/acpi: Add power resources for devices on USB ports ...................................................................... Patch Set 2: (1 comment) > Patch Set 2: > > (1 comment) > > > Patch Set 2: > > > > (1 comment) > > > > > Patch Set 2: > > > > > > (1 comment) > > > > > > > Patch Set 2: > > > > > > > > (1 comment) > > > > > > > > Hmm, this makes me want to attack the power resource problem again... > > > > With the devtree alias patches in, expressing power resource dependencies is even cleaner, e.g.,: > > > > > > > > ``` > > > > chip drivers/generic/power_resource/ > > > > register "on" = "{{GPIO_L(GPP_A1), 50}, > > > > {GPIO_L(GPIO_B2), 1},}" > > > > register "off" = "{{GPIO_L(GPP_B2), 1}, > > > > {GPIO(GPP_A1), 10},}" > > > > # or even the current interface in generic/2c with the stop_gpio, reset_gpio, etc. > > > > # but I kind of like this explicit sequencing you get here. > > > > device generic 0 alias i2c1_power_res on end > > > > end > > > > chip drivers/i2c/generic > > > > use i2c1_power_res as power_resource; > > > > device i2c 1f on end > > > > end > > > > chip drivers/spi/generic > > > > use i2c1_power_res as power_resource; > > > > device spi 0 on end > > > > end > > > > ``` > > > > > > > > Each "resource" in the 'on' and 'off' list (i.e., GPIOs) can emit enable/disable methods that use reference counting to keep track of when it's safe to actually assert/deassert the pins. > > > > > > > > WDYT? If you don't want to tackle that right now, factoring out the power resource fields into a common `struct power_resource_config` or similar would be better than copy-pasting these fields around into different drivers. > > > > > > We might want to eventually do something like you recommended i.e. having a separate power resource device especially if multiple devices have to share power resource. Last week you mentioned that this might probably be a use case for the camera device. > > > > > > One thing that we will probably have to think about some more is -- if a driver wants to expose the GPIOs in _CRS in addition to generating the power resource, then it will require both on/off as well as reset/enable GPIOs to be provided by mainboard in the devicetree entry. It might be helpful to write these thoughts in a doc/bug so that we can capture all scenarios. > > > > > > About adding a power_resource structure - I think that can be a quick way forward right now especially if Karthik is looking to unblock the mainboard CLs. However, if you plan to refactor and add a new power_resource driver, do you want to wait until then to decide what the structure should really look like? > > > > Just a strawman for the moment 😊 > > > > There are other considerations too, like ensuring that _PR0/_PR3 get emitted too. I have some thoughts, I should collect them into a doc. > > I will start with aggregating the fields into a common power resource structure and a simple wrapper function to generate the ACPI identifiers. This can be organized something like > drivers/power_resource/chip.h > drivers/power_resource/power_resource.c > > Once we have identified down all the use-cases, I can transform them into a driver covering all the documented use-cases. Does that sound good? Using the common power_resource structure in existing drivers (I2C,SPI,UART) is going to require changing all devicetrees to use power_resource.xyz instead of xyz. I think for now let's just maintain the way things are in this CL and do the clean up in one go for all drivers when we want to add a separate power resource device. Let's see what Tim thinks. https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/chip.h File src/drivers/usb/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/chip.… PS2, Line 47: /* Disable reset and enable GPIO export in _CRS */ : bool disable_gpio_export_in_crs; > Or did you mean not to expose when the GPIOs are meant specifically for power resource i.e. has_power_resource = 1? Correct. If the mainboard wants to expose a power resource, then there is no need to expose the reset/enable GPIO to kernel driver in _CRS. In other cases e.g. bluetooth reset GPIO, we still need to expose the GPIO in _CRS. -- To view, visit https://review.coreboot.org/c/coreboot/+/46713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Gerrit-Change-Number: 46713 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 05:15:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Karthik Ramasubramanian (Code Review) 03 Nov '20

03 Nov '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… File src/mainboard/google/dedede/variants/boten/gpio.c: https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… PS10, Line 11: 1 > Shouldn't this be 0 since it is being enabled by the ACPI methods? That is what I wrote in patchset 9 and it was verified to meet the power sequence requirement. ODM team overwrote it. Peichao Wang/Alec Wang can you please comment on it? -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 03 Nov 2020 05:08:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: driver/usb/acpi: Add power resources for devices on USB ports
by Karthik Ramasubramanian (Code Review) 03 Nov '20

03 Nov '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46713 ) Change subject: driver/usb/acpi: Add power resources for devices on USB ports ...................................................................... Patch Set 2: (1 comment) > Patch Set 2: > > (1 comment) > > > Patch Set 2: > > > > (1 comment) > > > > > Patch Set 2: > > > > > > (1 comment) > > > > > > Hmm, this makes me want to attack the power resource problem again... > > > With the devtree alias patches in, expressing power resource dependencies is even cleaner, e.g.,: > > > > > > ``` > > > chip drivers/generic/power_resource/ > > > register "on" = "{{GPIO_L(GPP_A1), 50}, > > > {GPIO_L(GPIO_B2), 1},}" > > > register "off" = "{{GPIO_L(GPP_B2), 1}, > > > {GPIO(GPP_A1), 10},}" > > > # or even the current interface in generic/2c with the stop_gpio, reset_gpio, etc. > > > # but I kind of like this explicit sequencing you get here. > > > device generic 0 alias i2c1_power_res on end > > > end > > > chip drivers/i2c/generic > > > use i2c1_power_res as power_resource; > > > device i2c 1f on end > > > end > > > chip drivers/spi/generic > > > use i2c1_power_res as power_resource; > > > device spi 0 on end > > > end > > > ``` > > > > > > Each "resource" in the 'on' and 'off' list (i.e., GPIOs) can emit enable/disable methods that use reference counting to keep track of when it's safe to actually assert/deassert the pins. > > > > > > WDYT? If you don't want to tackle that right now, factoring out the power resource fields into a common `struct power_resource_config` or similar would be better than copy-pasting these fields around into different drivers. > > > > We might want to eventually do something like you recommended i.e. having a separate power resource device especially if multiple devices have to share power resource. Last week you mentioned that this might probably be a use case for the camera device. > > > > One thing that we will probably have to think about some more is -- if a driver wants to expose the GPIOs in _CRS in addition to generating the power resource, then it will require both on/off as well as reset/enable GPIOs to be provided by mainboard in the devicetree entry. It might be helpful to write these thoughts in a doc/bug so that we can capture all scenarios. > > > > About adding a power_resource structure - I think that can be a quick way forward right now especially if Karthik is looking to unblock the mainboard CLs. However, if you plan to refactor and add a new power_resource driver, do you want to wait until then to decide what the structure should really look like? > > Just a strawman for the moment 😊 > > There are other considerations too, like ensuring that _PR0/_PR3 get emitted too. I have some thoughts, I should collect them into a doc. I will start with aggregating the fields into a common power resource structure and a simple wrapper function to generate the ACPI identifiers. This can be organized something like drivers/power_resource/chip.h drivers/power_resource/power_resource.c Once we have identified down all the use-cases, I can transform them into a driver covering all the documented use-cases. Does that sound good? https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/chip.h File src/drivers/usb/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/chip.… PS2, Line 47: /* Disable reset and enable GPIO export in _CRS */ : bool disable_gpio_export_in_crs; > Thanks for the background, I had been wondering what the deal was with leaving the GPIOs out of _CRS […] As per the existing use-case, reset_gpio has been already added to _CRS. Should we not expose in the existing use-cases too? I believe BT has been a regular user of the reset GPIO exported by _CRS. Or did you mean not to expose when the GPIOs are meant specifically for power resource i.e. has_power_resource = 1? -- To view, visit https://review.coreboot.org/c/coreboot/+/46713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Gerrit-Change-Number: 46713 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 05:05:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order
by Subrata Banik (Code Review) 03 Nov '20

03 Nov '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47057 ) Change subject: soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order ...................................................................... soc/intel: Select SOC_INTEL_COMMON_BLOCK_CAR as per alphabetical order Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/elkhartlake/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 5 files changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/47057/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index ade2fc1..b10d88c 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -53,7 +54,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index f833178..89da0be 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -54,7 +55,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index e1d474e..67bbcb2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -41,6 +41,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 9ee119f..201afec 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -39,6 +39,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -53,7 +54,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 5967a69..9aa40ed 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -40,6 +40,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -56,7 +57,6 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/47057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7adf430e6ce5f78f68a0c73af841fbdc62bb5dc9 Gerrit-Change-Number: 47057 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 03 Nov '20

03 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45275 ) Change subject: sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax ...................................................................... sb/intel/i82801gx/acpi: Convert *.asl to ASL+ Syntax Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/acpi/lpc.asl M src/southbridge/intel/i82801gx/acpi/usb.asl 2 files changed, 15 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/45275/1 diff --git a/src/southbridge/intel/i82801gx/acpi/lpc.asl b/src/southbridge/intel/i82801gx/acpi/lpc.asl index b93fa96..1f9e701 100644 --- a/src/southbridge/intel/i82801gx/acpi/lpc.asl +++ b/src/southbridge/intel/i82801gx/acpi/lpc.asl @@ -73,7 +73,7 @@ If (HPTE) { // Note: Ancient versions of Windows don't want // to see the HPET in order to work right - If (LGreaterEqual(OSYS, 2001)) { + If (OSYS >= 2001) { Return (0xf) // Enable and show device } Else { Return (0xb) // Enable and don't show device @@ -87,16 +87,16 @@ { If (HPTE) { CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0) - If (Lequal(HPAS, 1)) { - Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0) + If (HPAS == 1) { + HPT0 = CONFIG_HPET_ADDRESS + 0x1000 } - If (Lequal(HPAS, 2)) { - Add(CONFIG_HPET_ADDRESS, 0x2000, HPT0) + If (HPAS == 2) { + HPT0 = CONFIG_HPET_ADDRESS + 0x2000 } - If (Lequal(HPAS, 3)) { - Add(CONFIG_HPET_ADDRESS, 0x3000, HPT0) + If (HPAS == 3) { + HPT0 = CONFIG_HPET_ADDRESS + 0x3000 } } diff --git a/src/southbridge/intel/i82801gx/acpi/usb.asl b/src/southbridge/intel/i82801gx/acpi/usb.asl index 16db175..7c4ef34 100644 --- a/src/southbridge/intel/i82801gx/acpi/usb.asl +++ b/src/southbridge/intel/i82801gx/acpi/usb.asl @@ -21,9 +21,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U1WE) + U1WE = 3 } Else { - Store (0, U1WE) + U1WE = 0 } } @@ -40,7 +40,6 @@ } } - // USB Controller 0:1d.1 Device (USB2) @@ -60,9 +59,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U2WE) + U2WE = 3 } Else { - Store (0, U2WE) + U2WE = 0 } } @@ -80,7 +79,6 @@ } - // USB Controller 0:1d.2 Device (USB3) @@ -100,9 +98,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U3WE) + U3WE = 3 } Else { - Store (0, U3WE) + U3WE = 0 } } @@ -120,7 +118,6 @@ } - // USB Controller 0:1d.3 Device (USB4) @@ -140,9 +137,9 @@ { // USB Controller can wake OS from Sleep State If (Arg0) { - Store (3, U4WE) + U4WE = 3 } Else { - Store (0, U4WE) + U4WE = 0 } } @@ -160,7 +157,6 @@ } - // EHCI Controller 0:1d.7 Device (EHC1) -- To view, visit https://review.coreboot.org/c/coreboot/+/45275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf349bb70b1fee31bfcdb4c87ffa5b4b8359e289 Gerrit-Change-Number: 45275 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 6

Change in coreboot[master]: mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax
by HAOUAS Elyes (Code Review) 03 Nov '20

03 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45281 ) Change subject: mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax ...................................................................... mb/intel/d945gclf/acpi: Convert platform.asl to ASL+ Syntax Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/d945gclf/acpi/platform.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/45281/1 diff --git a/src/mainboard/intel/d945gclf/acpi/platform.asl b/src/mainboard/intel/d945gclf/acpi/platform.asl index 30e4d2c..cf73fc1 100644 --- a/src/mainboard/intel/d945gclf/acpi/platform.asl +++ b/src/mainboard/intel/d945gclf/acpi/platform.asl @@ -20,12 +20,12 @@ // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } -- To view, visit https://review.coreboot.org/c/coreboot/+/45281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic48008719a9cf6942ae8cdaebaab6ba43e665489 Gerrit-Change-Number: 45281 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: libpayload: Add support for link time optimization
by Jacob Garber (Code Review) 03 Nov '20

03 Nov '20

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38291 ) Change subject: libpayload: Add support for link time optimization ...................................................................... libpayload: Add support for link time optimization Link time optimization is a technique for whole-program optimization. Instead of doing code generation during compilation, the compiler saves its intermediate representation to the object files. During the final linking step, it will then merge all the object files together and perform optimizations on the entire program. This can often reduce the final binary size, but also may increase the total compilation time. This patch introduces a Kconfig option for enabling link time optimization in libpayload. Since libpayload does no linking of its own, its LTO archive files will contain only IR and no generated code. Downstream projects will need to use LTO-aware tools when manipulating the archives (eg. gcc-ar and gcc-nm), but otherwise do not need to use LTO themselves -- the compiler will recognize which files are LTO and which are not, so enabling this option should mostly be "drop in". For example, when building coreinfo.elf using tinycurses libpayload: binary size compilation time default 149K 11.49s LTO 125K 10.36s In this case the total compilation time was actually shorter -- despite the final linking step taking longer, this was offset by the shorter compilation times for each individual file (since there is no code gen until the very end). Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile.inc 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38291/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index f7501e3..9312f19 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -80,6 +80,13 @@ endchoice +config LTO + bool "Use link time optimization" + default n + help + Compile with link time optimization. This can often decrease the + final binary size, but may increase compilation time. + config REMOTEGDB bool "Remote GDB stub" default n diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 1b7986c..ecf7937 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -65,6 +65,10 @@ CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS += -Wstrict-aliasing -Wshadow -Werror +ifeq ($(CONFIG_LP_LTO),y) +CFLAGS += -flto=$(CPUS) -fuse-linker-plugin -fno-fat-lto-objects +endif + $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/38291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I048f2ff6298ed0d891098942e1e8b29d35487b91 Gerrit-Change-Number: 38291 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

8 23

Change in coreboot[master]: cpu/x86/mp_init: Add support for x86_64
by Patrick Rudolph (Code Review) 03 Nov '20

03 Nov '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44675 ) Change subject: cpu/x86/mp_init: Add support for x86_64 ...................................................................... cpu/x86/mp_init: Add support for x86_64 Fix compilation on x86_64. Tested on HP Z220: * Still boots on x86_32. Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/mp_init.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44675/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 5807831..da0002f 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -113,7 +113,7 @@ /* The SIPI vector is loaded at the SMM_DEFAULT_BASE. The reason is at the * memory range is already reserved so the OS cannot use it. That region is * free to use for AP bringup before SMM is initialized. */ -static const uint32_t sipi_vector_location = SMM_DEFAULT_BASE; +static const uintptr_t sipi_vector_location = SMM_DEFAULT_BASE; static const int sipi_vector_location_size = SMM_DEFAULT_SIZE; struct mp_flight_plan { @@ -339,16 +339,16 @@ setup_default_sipi_vector_params(sp); /* Setup MSR table. */ - sp->msr_table_ptr = (uint32_t)&mod_loc[module_size]; + sp->msr_table_ptr = (uintptr_t)&mod_loc[module_size]; sp->msr_count = num_msrs; /* Provide pointer to microcode patch. */ - sp->microcode_ptr = (uint32_t)mp_params->microcode_pointer; + sp->microcode_ptr = (uintptr_t)mp_params->microcode_pointer; /* Pass on ability to load microcode in parallel. */ if (mp_params->parallel_microcode_load) sp->microcode_lock = 0; else sp->microcode_lock = ~0; - sp->c_handler = (uint32_t)&ap_init; + sp->c_handler = (uintptr_t)&ap_init; ap_count = &sp->ap_count; atomic_set(ap_count, 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/44675 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7190d24172803e40acaf1495ce20f3ea38016b0 Gerrit-Change-Number: 44675 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 5

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020