coreboot-gerrit November 2020

coreboot-gerrit@coreboot.org

1 participants
3243 discussions

Change in coreboot[master]: driver/usb/acpi: Add power resources for devices on USB ports
by Tim Wawrzynczak (Code Review) 02 Nov '20

02 Nov '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46713 ) Change subject: driver/usb/acpi: Add power resources for devices on USB ports ...................................................................... Patch Set 2: (1 comment) > Patch Set 2: > > (1 comment) > > > Patch Set 2: > > > > (1 comment) > > > > Hmm, this makes me want to attack the power resource problem again... > > With the devtree alias patches in, expressing power resource dependencies is even cleaner, e.g.,: > > > > ``` > > chip drivers/generic/power_resource/ > > register "on" = "{{GPIO_L(GPP_A1), 50}, > > {GPIO_L(GPIO_B2), 1},}" > > register "off" = "{{GPIO_L(GPP_B2), 1}, > > {GPIO(GPP_A1), 10},}" > > # or even the current interface in generic/2c with the stop_gpio, reset_gpio, etc. > > # but I kind of like this explicit sequencing you get here. > > device generic 0 alias i2c1_power_res on end > > end > > chip drivers/i2c/generic > > use i2c1_power_res as power_resource; > > device i2c 1f on end > > end > > chip drivers/spi/generic > > use i2c1_power_res as power_resource; > > device spi 0 on end > > end > > ``` > > > > Each "resource" in the 'on' and 'off' list (i.e., GPIOs) can emit enable/disable methods that use reference counting to keep track of when it's safe to actually assert/deassert the pins. > > > > WDYT? If you don't want to tackle that right now, factoring out the power resource fields into a common `struct power_resource_config` or similar would be better than copy-pasting these fields around into different drivers. > > We might want to eventually do something like you recommended i.e. having a separate power resource device especially if multiple devices have to share power resource. Last week you mentioned that this might probably be a use case for the camera device. > > One thing that we will probably have to think about some more is -- if a driver wants to expose the GPIOs in _CRS in addition to generating the power resource, then it will require both on/off as well as reset/enable GPIOs to be provided by mainboard in the devicetree entry. It might be helpful to write these thoughts in a doc/bug so that we can capture all scenarios. > > About adding a power_resource structure - I think that can be a quick way forward right now especially if Karthik is looking to unblock the mainboard CLs. However, if you plan to refactor and add a new power_resource driver, do you want to wait until then to decide what the structure should really look like? Just a strawman for the moment 😊 There are other considerations too, like ensuring that _PR0/_PR3 get emitted too. I have some thoughts, I should collect them into a doc. https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/chip.h File src/drivers/usb/acpi/chip.h: https://review.coreboot.org/c/coreboot/+/46713/2/src/drivers/usb/acpi/chip.… PS2, Line 47: /* Disable reset and enable GPIO export in _CRS */ : bool disable_gpio_export_in_crs; > I think we should skip this. […] Thanks for the background, I had been wondering what the deal was with leaving the GPIOs out of _CRS. -- To view, visit https://review.coreboot.org/c/coreboot/+/46713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc1aebfb9e3e646a7f608f0cd391079fd30dd1c0 Gerrit-Change-Number: 46713 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 01:18:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: Add UART for sdm845
by Stefan Reinauer (Code Review) 02 Nov '20

02 Nov '20

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25817 ) Change subject: libpayload: Add UART for sdm845 ...................................................................... Patch Set 68: everything else in this patch train seems merged or abandoned? Still needed? -- To view, visit https://review.coreboot.org/c/coreboot/+/25817 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb982bccd489048833a78b6f8c5a903e5d3cdf94 Gerrit-Change-Number: 25817 Gerrit-PatchSet: 68 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 01:10:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi: move S0ix UUID to the condition
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46468 ) Change subject: soc/intel/common/acpi: move S0ix UUID to the condition ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46468/1//COMMIT_MSG@11 PS1, Line 11: CB > thx, I needed to push first to get a cb number but then forgot to fill it :'D Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic62c37090ad1b747f9d7d204363cc58f96ef67ef Gerrit-Change-Number: 46468 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 01:08:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi: rename LPID to PEPD
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46470 ) Change subject: soc/intel/common/acpi: rename LPID to PEPD ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/46470/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/46470/2//COMMIT_MSG@9 PS2, Line 9: the > I wasn't sure... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d Gerrit-Change-Number: 46470 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 03 Nov 2020 01:08:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47138 ) Change subject: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/… File src/soc/intel/common/acpi/lpit.asl: https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/… PS1, Line 26: This function > function 1; I moved that, thus must be corrected Done https://review.coreboot.org/c/coreboot/+/47138/1/src/soc/intel/common/acpi/… PS1, Line 57: DEVY > Yes and it does not work. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 01:07:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi,mb/*: replace LPID with PEPD
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46471 ) Change subject: soc/intel/common/acpi,mb/*: replace LPID with PEPD ...................................................................... Patch Set 6: (4 comments) https://review.coreboot.org/c/coreboot/+/46471/4/src/soc/intel/common/block… File src/soc/intel/common/block/acpi/acpi/pep.asl: https://review.coreboot.org/c/coreboot/+/46471/4/src/soc/intel/common/block… PS4, Line 19: Name(_HID, "INT33A1") /* Intel Power Engine */ > this still crashes Windows with `INTERNAL_POWER_ERROR`, even though refcode and vendor code have it Done https://review.coreboot.org/c/coreboot/+/46471/4/src/soc/intel/common/block… PS4, Line 30: 0x60 > this means "not supported"; refcode and vendor return 0x7F Done https://review.coreboot.org/c/coreboot/+/46471/4/src/soc/intel/common/block… PS4, Line 36: Return(Package(5) {0, Ones, Ones, Ones, Ones > wrong. […] Done https://review.coreboot.org/c/coreboot/+/46471/4/src/soc/intel/common/block… PS4, Line 42: Return(Buffer(One) {0x0}) > same as function 1 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/46471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Gerrit-Change-Number: 46471 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 03 Nov 2020 01:07:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Furquan Shaikh (Code Review) 02 Nov '20

02 Nov '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… File src/mainboard/google/dedede/variants/boten/gpio.c: https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… PS10, Line 11: 1 Shouldn't this be 0 since it is being enabled by the ACPI methods? https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… PS10, Line 45: 1 Shouldn't this be 0? Since it is being deasserted by the ACPI methods? https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… File src/mainboard/google/dedede/variants/boten/variant.c: https://review.coreboot.org/c/coreboot/+/44588/10/src/mainboard/google/dede… PS10, Line 15: const struct gpio_with_delay lte_power_off_gpios[] = { : { : GPP_H17, /* WWAN_RST_L => LTE_RESET_R_ODL */ : 10, : }, : { : GPP_A10, /* WWAN_EN => LTE_PWR_OFF_ODL */ : 0 : }, : }; : : for (int i = 0; i < ARRAY_SIZE(lte_power_off_gpios); i++) { : gpio_output(lte_power_off_gpios[i].gpio, 0); : mdelay(lte_power_off_gpios[i].delay_msecs); : } This can simply be written as: ``` gpio_output(GPIO_H17, 0); mdelay(10); gpio_output(GPIO_A10, 0); ``` Do we really need to have a table? I think the sequence is straight forward enough to put here directly. -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 10 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 03 Nov 2020 01:05:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/common/acpi: add _HID to PEPD
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46469 to look at the new patch set (#4). Change subject: soc/intel/common/acpi: add _HID to PEPD ...................................................................... soc/intel/common/acpi: add _HID to PEPD Add the _HID INT33A1 to PEPD to make Linux recognize it as "Intel Power Engine" in the pmc core driver. The _ADR gets dropped, because _HID and _ADR are mutually exclusive. Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/block/acpi/acpi/pep.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/46469/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/46469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a0335681f1601f7fd8a9245a3dea72ffd100b55 Gerrit-Change-Number: 46469 Gerrit-PatchSet: 4 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/acpi,mb/*: replace LPID with PEPD
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Tim Wawrzynczak, Paul Menzel, Subrata Banik, Patrick Rudolph, Karthikeyan Ramasubramanian, Venkata Krishna Nimmagadda, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/46471 to look at the new patch set (#6). Change subject: soc/intel/common/acpi,mb/*: replace LPID with PEPD ...................................................................... soc/intel/common/acpi,mb/*: replace LPID with PEPD Replace the two duplicate LPID with the new PEPD device. The PEPD device gets included in the plaforms' `southbridge.asl`, since it is required to load the `intel_pmc_core` module in Linux, which checks for the _HID. (See CB:46469 for more info on that.) There is no harm for mainboards not supporting S0ix, because the _DSM function won't be called with the LPS0 uuid on such boards. Such boards can use the debugging functionality of `intel_pmc_core`, too. Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/mainboard/google/deltaur/dsdt.asl M src/mainboard/google/drallion/dsdt.asl M src/mainboard/google/hatch/dsdt.asl M src/mainboard/google/sarien/dsdt.asl M src/mainboard/google/volteer/dsdt.asl M src/soc/intel/alderlake/acpi/southbridge.asl M src/soc/intel/cannonlake/acpi/southbridge.asl D src/soc/intel/common/acpi/lpit.asl A src/soc/intel/common/block/acpi/acpi/pep.asl D src/soc/intel/common/block/acpi/acpi/pmc.asl M src/soc/intel/elkhartlake/acpi/southbridge.asl M src/soc/intel/jasperlake/acpi/southbridge.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 13 files changed, 135 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46471/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/46471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5 Gerrit-Change-Number: 46471 Gerrit-PatchSet: 6 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards
by Michael Niewöhner (Code Review) 02 Nov '20

02 Nov '20

Hello build bot (Jenkins), Nico Huber, Furquan Shaikh, Matt DeVillier, Paul Menzel, Tim Wawrzynczak, Angel Pons, Subrata Banik, Patrick Rudolph, Karthikeyan Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47138 to look at the new patch set (#2). Change subject: soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards ...................................................................... soc/intel/common/acpi: fix Windows crash on S0ix-enabled boards Windows does not comply with the Low Power Idle S0 specification and crashes with an `INTERNAL_POWER_ERROR` bluescreen when function 1, does not return at least one device constraint, even when function 1 is announced as being not available by the enum function. Returning an empty package does not work. To make Windows work on S0ix-enabled boards, return a dummy constraint package with a disabled dummy device. Since the device constraints are only used for debugging low power states in Linux and probably also in Windows, there shouldn't be any negative effect to S0ix. Real device constraint entries can be added at a later point. Test: no bluescreen anymore on Clevo L140CU and Windows 10 (version 2004, build 19041.508) detects S0ix in `powercfg -a` Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de> --- M src/soc/intel/common/acpi/lpit.asl 1 file changed, 22 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47138/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd08cbcb1dfcb8cbb23f4f4c902bf8c367c8e3ac Gerrit-Change-Number: 47138 Gerrit-PatchSet: 2 Gerrit-Owner: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2020