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Change in coreboot[master]: mb/samsung/stumpy: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46215 ) Change subject: mb/samsung/stumpy: Convert to ASL 2.0 syntax ...................................................................... mb/samsung/stumpy: Convert to ASL 2.0 syntax Change-Id: I0eda144f1a4f07ca82b3a799afcd8fc908419e69 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/samsung/stumpy/acpi/platform.asl M src/mainboard/samsung/stumpy/acpi/thermal.asl 2 files changed, 49 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/46215/1 diff --git a/src/mainboard/samsung/stumpy/acpi/platform.asl b/src/mainboard/samsung/stumpy/acpi/platform.asl index 39e414b..ed056db 100644 --- a/src/mainboard/samsung/stumpy/acpi/platform.asl +++ b/src/mainboard/samsung/stumpy/acpi/platform.asl @@ -6,36 +6,36 @@ Method(_PTS,1) { - Store (Zero, GP08) // Disable Bluetooth + GP08 = 0 // Disable Bluetooth - If (LEqual (Arg0, 3)) { + If (Arg0 == 3) { // NVS has a flag to determine USB policy in S3 If (S3U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S3 If (S3U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } - If (LEqual (Arg0, 5)) { + If (Arg0 == 5) { // NVS has a flag to determine USB policy in S5 If (S5U0) { - Store (One, GP47) // Enable USB0 + GP47 = 1 // Enable USB0 } Else { - Store (Zero, GP47) // Disable USB0 + GP47 = 0 // Disable USB0 } // NVS has a flag to determine USB policy in S5 If (S5U1) { - Store (One, GP56) // Enable USB1 + GP56 = 1 // Enable USB1 } Else { - Store (Zero, GP56) // Disable USB1 + GP56 = 0 // Disable USB1 } } } @@ -66,5 +66,5 @@ /* Disable USB Controller Reset in S3 (defaults to enabled) */ Method (USBR, 0, Serialized) { - Store (USB_RESET_DISABLE_MAGIC, US3B) + US3B = USB_RESET_DISABLE_MAGIC } diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl index 39df88a..cf44aba 100644 --- a/src/mainboard/samsung/stumpy/acpi/thermal.asl +++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl @@ -20,10 +20,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -49,28 +49,28 @@ Method (_TMP, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (\F2ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -78,7 +78,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -86,7 +86,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -94,7 +94,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -102,7 +102,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -118,20 +118,20 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -139,20 +139,20 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -160,20 +160,20 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -181,20 +181,20 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -202,20 +202,20 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eda144f1a4f07ca82b3a799afcd8fc908419e69 Gerrit-Change-Number: 46215 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: ec/purism/librem: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46102 ) Change subject: ec/purism/librem: Convert to ASL 2.0 syntax ...................................................................... ec/purism/librem: Convert to ASL 2.0 syntax Change-Id: I36cb7a2ebde1161f87e78eeab739b15e3cf88860 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/purism/librem/acpi/battery.asl M src/ec/purism/librem/acpi/ec.asl 2 files changed, 53 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/46102/1 diff --git a/src/ec/purism/librem/acpi/battery.asl b/src/ec/purism/librem/acpi/battery.asl index ca682a8..028a1de 100644 --- a/src/ec/purism/librem/acpi/battery.asl +++ b/src/ec/purism/librem/acpi/battery.asl @@ -65,13 +65,13 @@ /* Method to enable full battery workaround */ Method (BFWE) { - Store (One, BFWK) + BFWK = 1 } /* Method to disable full battery workaround */ Method (BFWD) { - Store (Zero, BFWK) + BFWK = 0 } Method (_STA, 0, Serialized) @@ -86,22 +86,22 @@ Method (_BIF, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BTDF, Index (PBIF, 2)) + PBIF [2] = BTDF /* Design Voltage */ - Store (BTDV, Index (PBIF, 4)) + PBIF [4] = BTDV /* Design Capacity */ - Store (BTDA, Local0) - Store (Local0, Index (PBIF, 1)) + Local0 = BTDA + PBIF [1] = Local0 /* Design Capacity of Warning */ - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (PBIF, 5)) + Local2 = (Local0 * DWRN) / 100 + PBIF [5] = Local2 /* Design Capacity of Low */ - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (PBIF, 6)) + Local2 = (Local0 * DLOW) / 100 + PBIF [6] = Local2 Return (PBIF) } @@ -109,22 +109,22 @@ Method (_BIX, 0, Serialized) { /* Last Full Charge Capacity */ - Store (BTDF, Index (PBIX, 3)) + PBIX [3] = BTDF /* Design Voltage */ - Store (BTDV, Index (PBIX, 5)) + PBIX [5] = BTDV /* Design Capacity */ - Store (BTDA, Local0) - Store (Local0, Index (PBIX, 2)) + Local0 = BTDA + PBIX [2] = Local0 /* Design Capacity of Warning */ - Divide (Multiply (Local0, DWRN), 100, , Local2) - Store (Local2, Index (PBIX, 6)) + Local2 = (Local0 * DWRN) / 100 + PBIX [6] = Local2 /* Design Capacity of Low */ - Divide (Multiply (Local0, DLOW), 100, , Local2) - Store (Local2, Index (PBIX, 7)) + Local2 = (Local0 * DLOW) / 100 + PBIX [7] = Local2 Return (PBIX) } @@ -142,61 +142,60 @@ /* Check if AC is present */ If (ACEX) { /* Read battery status from EC */ - Store (BSTS, Local0) + Local0 = BSTS } Else { /* Always discharging when on battery power */ - Store (0x01, Local0) + Local0 = 0x01 } /* Check for critical battery level */ If (BFCR) { - Or (Local0, 0x04, Local0) + Local0 |= 0x04 } - Store (Local0, Index (PBST, 0)) + PBST [0] = Local0 /* Notify if battery state has changed since last time */ - If (LNotEqual (Local0, BSTP)) { - Store (Local0, BSTP) + If (Local0 != BSTP) { + BSTP = Local0 Notify (BAT, 0x80) } /* * 1: BATTERY PRESENT RATE */ - Store (BTPR, Local1) - If (And (Local1, 0x8000)) { - And (Not (Local1), 0x7FFF, Local0) - Increment (Local0) + Local1 = BTPR + If (Local1 & 0x8000) { + Local0 = ~Local1 & 0x7FFF + Local0++ } Else { - And (Local1, 0x7FFF, Local0) + Local0 = Local1 & 0x7FFF } - If(LLess(Local0, 0x0352)) + If(Local0 < 0x0352) { - Store(0x0352, Local0) + Local0 = 0x0352 } - Store (Local0, Index (PBST, 1)) + PBST [1] = Local0 /* * 2: BATTERY REMAINING CAPACITY */ - Store (BTRA, Local0) - If (LAnd (BFWK, LAnd (ACEX, LNot (BSTS)))) { - Store (BTDF, Local1) + Local0 = BTRA + If (BFWK && ACEX && !BSTS)) { + Local1 = BTDF /* See if within ~6% of full */ - ShiftRight (Local1, 4, Local2) - If (LAnd (LGreater (Local0, Subtract (Local1, Local2)), - LLess (Local0, Add (Local1, Local2)))) + Local2 = Local1 >> 4 + If (Local0 > (Local1 - Local2)) && (Local0 < (Local1 + Local2)) { - Store (Local1, Local0) + Local0 = Local1 } } - Store (Local0, Index (PBST, 2)) + PBST [2] = Local0 /* * 3: BATTERY PRESENT VOLTAGE */ - Store (BTVO, Index (PBST, 3)) + PBST [3] = BTVO Return (PBST) } diff --git a/src/ec/purism/librem/acpi/ec.asl b/src/ec/purism/librem/acpi/ec.asl index 668b7d1..bf855af 100644 --- a/src/ec/purism/librem/acpi/ec.asl +++ b/src/ec/purism/librem/acpi/ec.asl @@ -15,12 +15,12 @@ Method (FNCX, 1, NotSerialized) { - If (LEqual (Arg0, 0x86)) { + If (Arg0 == 0x86) { /* Enable topstar-laptop kernel driver handling */ - Store (One, ^^EC.TPSE) - } ElseIf (LEqual (Arg0, 0x87)) { + ^^EC.TPSE = 1 + } ElseIf (Arg0 == 0x87) { /* Disable topstar-laptop kernel driver handling */ - Store (Zero, ^^EC.TPSE) + ^^EC.TPSE = 0 } } } @@ -80,10 +80,10 @@ Method (_REG, 2, NotSerialized) { /* Initialize AC power state */ - Store (ACEX, \PWRS) + \PWRS = ACEX /* Initialize LID switch state */ - Store (LIDS, \LIDS) + \LIDS = LIDS } /* Notify topstar-laptop kernel driver */ @@ -115,7 +115,7 @@ /* AC Status Changed */ Method (_Q20) { - Store (ACEX, \PWRS) + \PWRS = ACEX Notify (AC, 0x80) Notify (BAT, 0x80) PNOT () @@ -124,7 +124,7 @@ /* Lid Event */ Method (_Q21) { - Store (LIDS, \LIDS) + \LIDS = LIDS Notify (LID0, 0x80) } @@ -193,7 +193,7 @@ /* KEY_BLUETOOTH */ Method (_Q37) { - XOr (^BTLE, One, ^BTLE) + ^BTLE ^= 1 } /* Turbo Enable/Disable */ @@ -208,13 +208,13 @@ * when the system is charging. */ If (TURB) { - Store (PPCM_TURBO, PPCM) + PPCM = PPCM_TURBO PPCN () - Store (One, EDTB) + EDTB = 1 } Else { - Store (PPCM_NOTURBO, PPCM) + PPCM = PPCM_NOTURBO PPCN () - Store (Zero, EDTB) + EDTB = 0 } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36cb7a2ebde1161f87e78eeab739b15e3cf88860 Gerrit-Change-Number: 46102 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: soc/intel/xeon_sp: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46243 ) Change subject: soc/intel/xeon_sp: Convert to ASL 2.0 syntax ...................................................................... soc/intel/xeon_sp: Convert to ASL 2.0 syntax Change-Id: I43e36f2e736192603be61519d3e185605e81f0e8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/xeon_sp/acpi/southcluster.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/46243/1 diff --git a/src/soc/intel/xeon_sp/acpi/southcluster.asl b/src/soc/intel/xeon_sp/acpi/southcluster.asl index effed43..d1fd98f 100644 --- a/src/soc/intel/xeon_sp/acpi/southcluster.asl +++ b/src/soc/intel/xeon_sp/acpi/southcluster.asl @@ -138,7 +138,7 @@ Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -147,7 +147,7 @@ { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46243 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43e36f2e736192603be61519d3e185605e81f0e8 Gerrit-Change-Number: 46243 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/roda/rk886ex: Convert *.asl to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46012 ) Change subject: mb/roda/rk886ex: Convert *.asl to ASL 2.0 syntax ...................................................................... mb/roda/rk886ex: Convert *.asl to ASL 2.0 syntax Change-Id: I2eea24db6cfd260e0f36243e90a5e01b360f23fb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/roda/rk886ex/acpi/battery.asl M src/mainboard/roda/rk886ex/acpi/ec.asl M src/mainboard/roda/rk886ex/acpi/platform.asl M src/mainboard/roda/rk886ex/acpi/superio.asl M src/mainboard/roda/rk886ex/acpi/thermal.asl 5 files changed, 206 insertions(+), 206 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46012/1 diff --git a/src/mainboard/roda/rk886ex/acpi/battery.asl b/src/mainboard/roda/rk886ex/acpi/battery.asl index de13049..c415c03 100644 --- a/src/mainboard/roda/rk886ex/acpi/battery.asl +++ b/src/mainboard/roda/rk886ex/acpi/battery.asl @@ -69,76 +69,76 @@ /* Update Battery Info */ Method(UPBI, 0) { - Store (0x78, Index(PBIF, 1)) - Store (0x64, Index(PBIF, 2)) - Store (0x2b5c, Index(PBIF, 4)) - Store ("Bat1", Index(PBIF, 9)) - Store ("001", Index(PBIF, 10)) - Store ("LION", Index(PBIF, 11)) - Store ("Panasonic", Index(PBIF, 12)) + PBIF [1] = 0x78 + PBIF [2] = 0x64 + PBIF [4] = 0x2b5c + PBIF [9] = "Bat1" + PBIF [10] = "001" + PBIF [11] = "LION" + SPBIF [12] = "Panasonic" } Method(UPBS, 0) { - Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0) - If (Not(Local0)) { - Store(0, GP38) + Local0 = \_SB.PCI0.LPCB.EC0.QEVT + If (!Local0) { + GP38 = 0 Sleep(0x64) - Store(GP38, Local0) - If (Not(Local0)) { - Store (RDW(0x0d), Local0) - If (LNotEqual(Local0, 0xeeee)) { - If (LLessEqual(Local0, 0x64)) { - Store(Local0, CBA1) + Local0 = GP38 + If (!Local0) { + Local0 = RDW (0x0d) + If (Local0 != 0xeeee) { + If (Local0 <= 0x64) { + CBA1 = Local0 } } } } - Store (CBA1, Local0) - Store (Local0, Index(PBST, 2)) - Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) - Store (0, Local1) + Local0 = CBA1 + PBST [2] = Local0 + PBST [3] = DerefOf (PBIF [4]) + Local1 = 0 If (PWRS) { - If (LLess(Local0, 0x64)) { - Store (2, Local1) + If (Local0 < 0x64) { + Local1 = 2 } } Else { - If (LLessEqual(Local0, 0x5)) { - Store (4, Local1) + If (Local0 <<= 0x5) { + Local1 = 4 } Else { - Store (1, Local1) + Local1 = 1 } } - Store (Local1, Index(PBST, 0)) + PBST [0] = Local1 If (\_SB.PCI0.LPCB.EC0.P63S) { - Store (0x16, Index(PBST, 1)) + PBST [1] = 0x16 } Else { - Store (0x0b, Index(PBST, 1)) + PBST [1] = 0x0b } } // Invalidate Battery Info Method(IVBI, 0) { - Store (0xffffffff, Index(PBIF, 1)) - Store (0xffffffff, Index(PBIF, 2)) - Store (0xffffffff, Index(PBIF, 4)) - Store ("Bad", Index(PBIF, 9)) - Store ("Bad", Index(PBIF, 10)) - Store ("Bad", Index(PBIF, 11)) - Store ("Bad", Index(PBIF, 12)) - Store (1, Index(PBIF, 0)) + PBIF [1] = 0xffffffff + PBIF [2] = 0xffffffff + PBIF [4] = 0xffffffff + PBIF [9] = "Bad" + PBIF [10] = "Bad" + PBIF [11] = "Bad" + PBIF [12] = "Bad" + PBIF [0] = 1 } Method(IVBS, 0) { - Store (0x0, Index(PBST, 0)) - Store (0xffffffff, Index(PBST, 1)) - Store (0xffffffff, Index(PBST, 2)) - Store (0xffffffff, Index(PBST, 3)) + PBST [0] = 0 + PBST [1] = 0xffffffff + PBST [2] = 0xffffffff + PBST [3] = 0xffffffff } } @@ -209,85 +209,85 @@ /* Update Battery Info */ Method(UPBI, 0) { - Store (0x78, Index(PBIF, 1)) - Store (0x64, Index(PBIF, 2)) - Store (0x2b5c, Index(PBIF, 4)) - Store ("Bat2", Index(PBIF, 9)) - Store ("002", Index(PBIF, 10)) - Store ("LION", Index(PBIF, 11)) - Store ("Panasonic", Index(PBIF, 12)) + PBIF [1] = 0x78 + PBIF [2] = 0x64 + PBIF [4] = 0x2b5c + PBIF [9] = "Bat2" + PBIF [10] = "002" + PBIF [11] = "LION" + SPBIF [12] = "Panasonic" } Method(UPBS, 0) { - Store(\_SB.PCI0.LPCB.EC0.QEVT, Local0) - If (Not(Local0)) { - Store(0, GP38) + Local0 = \_SB.PCI0.LPCB.EC0.QEVT + If (!Local0) { + GP38 = 0 Sleep(0x64) - Store(GP38, Local0) - If (Not(Local0)) { - Store (RDW(0x0d), Local0) - If (LNotEqual(Local0, 0xeeee)) { - If (LLessEqual(Local0, 0x64)) { - Store(Local0, CBA2) + Local0 = GP38 + If (!Local0) { + Local0 = RDW (0x0d) + If (Local0 != 0xeeee) { + If (Local0 <= 0x64) { + CBA2 = Local0 } } } } - Store (CBA2, Local0) - Store (Local0, Index(PBST, 2)) - Store (DerefOf(Index(PBIF, 4)), Index(PBST, 3)) - Store (0, Local1) + Local0 = CBA2 + PBST [2] = Local0 + PBST [3] = DerefOf (PBIF [4]) + Local1 = 0 If (PWRS) { - If (LLess(Local0, 0x64)) { - Store (2, Local1) + If (Local0 < 0x64) { + Local1 = 2 } } Else { - If (LLessEqual(Local0, 0x5)) { - Store (4, Local1) + If (Local0 <<= 0x5) { + Local1 = 4 } Else { - Store (1, Local1) + Local1 = 1 } } - Store (Local1, Index(PBST, 0)) + PBST [0] = Local1 If (\_SB.PCI0.LPCB.EC0.P62S) { - Store (0x16, Index(PBST, 1)) + PBST [1] = 0x16 } Else { - Store (0x0b, Index(PBST, 1)) + PBST [1] = 0x0b } } // Invalidate Battery Info Method(IVBI, 0) { - Store (0xffffffff, Index(PBIF, 1)) - Store (0xffffffff, Index(PBIF, 2)) - Store (0xffffffff, Index(PBIF, 4)) - Store ("Bad", Index(PBIF, 9)) - Store ("Bad", Index(PBIF, 10)) - Store ("Bad", Index(PBIF, 11)) - Store ("Bad", Index(PBIF, 12)) - Store (1, Index(PBIF, 0)) + PBIF [1] = 0xffffffff + PBIF [2] = 0xffffffff + PBIF [4] = 0xffffffff + PBIF [9] = "Bad" + PBIF [10] = "Bad" + PBIF [11] = "Bad" + PBIF [12] = "Bad" + PBIF [0] = 1 } Method(IVBS, 0) { - Store (0x0, Index(PBST, 0)) - Store (0xffffffff, Index(PBST, 1)) - Store (0xffffffff, Index(PBST, 2)) - Store (0xffffffff, Index(PBST, 3)) + PBST [0] = 0 + PBST [1] = 0xffffffff + PBST [2] = 0xffffffff + PBST [3] = 0xffffffff } } Method (RDW, 1) { - Store (0x16, \_SB.PCI0.LPCB.EC0.SMAD) - Store (Arg0, \_SB.PCI0.LPCB.EC0.SMCM) - Store (0x09, \_SB.PCI0.LPCB.EC0.SMPR) - While (LNotEqual(\_SB.PCI0.LPCB.EC0.SMPR, 0x00)) { + \_SB.PCI0.LPCB.EC0.SMAD = 0x16 + \_SB.PCI0.LPCB.EC0.SMCM = Arg0 + \_SB.PCI0.LPCB.EC0.SMPR = 0x09 + While (\_SB.PCI0.LPCB.EC0.SMPR != 0x00) { Stall (1) } @@ -300,11 +300,11 @@ Method (_PSR, 0) { If (\_SB.PCI0.LPCB.EC0.ECON) { - Store (\_SB.PCI0.LPCB.EC0.P60S, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.P60S If (Local0) { - Store (0, PWRS) + PWRS = 0 } Else { - Store (1, PWRS) + PWRS = 1 } } diff --git a/src/mainboard/roda/rk886ex/acpi/ec.asl b/src/mainboard/roda/rk886ex/acpi/ec.asl index 9ec0c36..ace6ab2 100644 --- a/src/mainboard/roda/rk886ex/acpi/ec.asl +++ b/src/mainboard/roda/rk886ex/acpi/ec.asl @@ -63,8 +63,8 @@ // This method is needed by Windows XP/2000 for // EC initialization before a driver is loaded - If (LEqual(Arg0, 0x03)) { - Store (Arg1, ECON) + If (Arg0 == 0x03) { + ECON = Arg1 } } @@ -72,20 +72,20 @@ Method (_Q11, 0) { - Store("_Q11: Fn-F8 (Sleep Button) pressed", Debug) + Debug = "_Q11: Fn-F8 (Sleep Button) pressed" Notify(SLPB, 0x80) } Method (_Q12, 0) { - Store("_Q12: Fn-F9 (Display Switch) pressed", Debug) + Debug = "_Q12: Fn-F9 (Display Switch) pressed" Notify (\_SB.PCI0.GFX0, 0x82) - // Store(1, TLST) + // TLST = 1 } Method (_Q30, 0) { - Store("_Q30: AC In/Out", Debug) + Debug = "_Q30: AC In/Out" Notify(ADP1, 0x80) // Tell the Power Adapter PNOT() // and the CPU and Battery // Notify the Batteries @@ -95,16 +95,16 @@ Method (_Q31, 0) { - Store("_Q31: LID Open/Close", Debug) + Debug = "_Q31: LID Open/Close" Notify(LID0, 0x80) } Method (_Q32, 0) { - Store("_Q32: Battery 1 In/Out", Debug) + Debug = "_Q32: Battery 1 In/Out" If (ECON) { - Store (P62S, Local0) - If (Not(Local0)) { + Local0 = P62S + If (!Local0) { Notify(BAT1, 0x80) } } @@ -112,10 +112,10 @@ Method (_Q33, 0) { - Store("_Q33: Battery 2 In/Out", Debug) + Debug = "_Q33: Battery 2 In/Out" If (ECON) { - Store (P63S, Local0) - If (Not(Local0)) { + Local0 = P63S + If (!Local0) { Notify(BAT2, 0x80) } } @@ -123,33 +123,33 @@ Method (_Q34, 0) { - Store("_Q34: LPT/FDD", Debug) + Debug = "_Q34: LPT/FDD" // PHSS(0x70) } Method (_Q35, 0) { - Store("_Q35: Processor is hot", Debug) + Debug = "_Q35: Processor is hot" } Method (_Q36, 0) { - Store("_Q36: Thermal Warning", Debug) + Debug = "_Q36: Thermal Warning" } Method (_Q37, 0) { - Store("_Q37: PME", Debug) + Debug = "_Q37: PME" } Method (_Q38, 0) { - Store("_Q38: Thermal", Debug) + Debug = "_Q38: Thermal" } Method (_Q39, 0) { - Store("_Q39: Thermal", Debug) + Debug = "_Q39: Thermal" } // TODO Scope _SB devices for AC power, LID, Power button diff --git a/src/mainboard/roda/rk886ex/acpi/platform.asl b/src/mainboard/roda/rk886ex/acpi/platform.asl index fb272dd..d62e051 100644 --- a/src/mainboard/roda/rk886ex/acpi/platform.asl +++ b/src/mainboard/roda/rk886ex/acpi/platform.asl @@ -20,12 +20,12 @@ // was inserted while a sleep state was active. // Are we going to S3? - If (LEqual(Arg0, 3)) { + If (Arg0 == 3) { // .. } // Are we going to S4? - If (LEqual(Arg0, 4)) { + If (Arg0 == 4) { // .. } @@ -56,7 +56,7 @@ * running: Windows XP SP1 needs to have C-State coordination * enabled in SMM. */ - If (LAnd(LEqual(OSYS, 2001), MPEN)) { + If ((OSYS == 2001) && MPEN) { // TRAP(61) // TODO } diff --git a/src/mainboard/roda/rk886ex/acpi/superio.asl b/src/mainboard/roda/rk886ex/acpi/superio.asl index 6f356e9..d1c670c 100644 --- a/src/mainboard/roda/rk886ex/acpi/superio.asl +++ b/src/mainboard/roda/rk886ex/acpi/superio.asl @@ -19,13 +19,13 @@ Method (READ, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (DATA, Local1) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + Local1 = DATA + INDX = 0xaa } - And (Local1, Arg2, Local1) + Local1 &= Arg2 Release(SIOM) Return(Local1) } @@ -33,11 +33,11 @@ Method (WRIT, 3) { Acquire (SIOM, 0xffff) - If (LEqual(Arg0, 0)) { - Store (0x55, INDX) - Store (Arg1, INDX) - Store (Arg2, DATA) - Store (0xaa, INDX) + If (Arg0 == 0) { + INDX = 0x55 + INDX = Arg1 + DATA = Arg2 + INDX = 0xaa } Release(SIOM) } @@ -52,18 +52,18 @@ Method (_STA, 0) { // Device disabled by coreboot? - If (LEqual(CMAP, 0)) { + If (CMAP == 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x24, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x24, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x08), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x08) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -76,12 +76,12 @@ { WRIT(0, 0x24, 0x00) - Store(READ(0, 0x28, 0x0f), Local0) + Local0 = READ (0, 0x28, 0x0f) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -106,8 +106,8 @@ IRQNoFlags(_IRA) { 4 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA() & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -119,15 +119,15 @@ \_SB.PCI0.LPCB.SIO1.COMA._CRS._IRA._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x24, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x24, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0xf0), Local0) - ShiftRight(Local0, 4, Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0xf0) + Local0 >>= 4 + IRQ = 1 << Local0 Return(RSRC) } @@ -140,29 +140,29 @@ WRIT(0, 0x24, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) - ShiftLeft(Local0, 4, Local0) + Local0-- + Local0 <<= 4 - Store(READ(0, 0x28, 0x0f), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0x0f) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x24, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } @@ -170,22 +170,22 @@ /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x08, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x08 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x40, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x40 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x08, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x08 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } @@ -200,24 +200,24 @@ Method (_STA, 0) { // Device disabled by coreboot? - If (LEqual(CMBP, 0)) { + If (CMBP == 0) { Return (0) } /* IRDA? */ - Store(READ(0, 0x0c, 0x38), Local0) - If (LNotEqual(Local0, Zero)) { + Local0 = READ (0, 0x0c, 0x38) + If (Local0 != 0) { Return (0) } // Is the hardware enabled? - Store (READ(0, 0x25, 0xff), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x25, 0xff) + If (Local0 == 0) { Return (0xd) } Else { // Power Enabled? - Store (READ(0, 0x02, 0x80), Local0) - If (LEqual(Local0, 0)) { + Local0 = READ (0, 0x02, 0x80) + If (Local0 == 0) { Return (0x0d) } Else { Return (0x0f) @@ -230,12 +230,12 @@ { WRIT(0, 0x25, 0x00) - Store(READ(0, 0x28, 0xf0), Local0) + Local0 = READ (0, 0x28, 0xf0) WRIT(0, 0x28, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } @@ -260,8 +260,8 @@ IRQNoFlags(_IRB) { 3 } }) - And (_STA(), 0x02, Local0) - If (LEqual(Local0, 0)) { + Local0 = _STA() & 0x02 + If (Local0 == 0) { Return(NONE) } @@ -273,14 +273,14 @@ \_SB.PCI0.LPCB.SIO1.COMB._CRS._IRB._INT, IRQ) /* I/O Base */ - Store (READ(0, 0x25, 0xfe), Local0) - ShiftLeft(Local0, 0x02, Local0) - Store(Local0, IOMN) - Store(Local0, IOMX) + Local0 = READ (0, 0x25, 0xfe) + Local0 <<= 2 + IOMN = Local0 + IOMX = Local0 /* Interrupt */ - Store(READ(0, 0x28, 0x0f), Local0) - ShiftLeft(1, Local0, IRQ) + Local0 = READ (0, 0x28, 0x0f) + IRQ = 1 << Local0 Return(RSRC) } @@ -293,55 +293,55 @@ WRIT(0, 0x25, 0) FindSetRightBit(IRQL, Local0) - Decrement(Local0) + Local0-- - Store(READ(0, 0x28, 0xf0), Local1) - Or(Local0, Local1, Local0) + Local1 = READ (0, 0x28, 0xf0) + Local0 |= Local1 WRIT(0, 0x28, Local0) - Store(IOLO, Local0) - ShiftRight(Local0, 2, Local0) - And(Local0, 0xfe, Local0) + Local0 = IOLO + Local0 >>= 2 + Local0 &= 0xfe - Store(IOHI, Local1) - ShiftLeft(Local1, 6, Local1) - Or (Local0, Local1, Local0) + Local1 = IOHI + Local1 <<= 6 + Local0 |= Local1 WRIT(0, 0x25, Local0) - Store(READ(0, 0x0c, 0xff), Local0) - Not(0x38, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x0c, 0xff) + Local1 = ~0x38 + Local0 &= Local1 WRIT(0, 0x0c, Local0) - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store(READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And (Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D0 state - Line drivers are on */ Method (_PS0, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Or(Local0, 0x80, Local0) + Local0 = READ (0, 0x02, 0xff) + Local0 |= 0x80 WRIT(0, 0x02, Local0) - Store (READ(0, 0x07, 0xff), Local0) - Not(0x20, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x07, 0xff) + Local1 = ~0x20 + Local0 &= Local1 WRIT(0, 0x07, Local0) } /* D3 State - Line drivers are off */ Method(_PS3, 0) { - Store(READ(0, 0x02, 0xff), Local0) - Not(0x80, Local1) - And(Local0, Local1, Local0) + Local0 = READ (0, 0x02, 0xff) + Local1 = ~0x80 + Local0 &= Local1 WRIT(0, 0x02, Local0) } } diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl index ff7639f..29d501f 100644 --- a/src/mainboard/roda/rk886ex/acpi/thermal.asl +++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl @@ -29,7 +29,7 @@ // Critical shutdown temperature Method (_CRT, 0, Serialized) { - Return (Add (0x0aac, 0x50)) // FIXME + Return (0x0aac + 0x50) // FIXME } // CPU throttling start temperature -- To view, visit https://review.coreboot.org/c/coreboot/+/46012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2eea24db6cfd260e0f36243e90a5e01b360f23fb Gerrit-Change-Number: 46012 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/link: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46176 ) Change subject: mb/google/link: Convert to ASL 2.0 syntax ...................................................................... mb/google/link: Convert to ASL 2.0 syntax Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/link/acpi/platform.asl M src/mainboard/google/link/acpi/thermal.asl 2 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/46176/1 diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl index 35893ee..12b1453 100644 --- a/src/mainboard/google/link/acpi/platform.asl +++ b/src/mainboard/google/link/acpi/platform.asl @@ -7,7 +7,7 @@ Method(_PTS,1) { /* Disable WWAN */ - Store (Zero, GP36) + GP36 = 0 } /* The _WAK method is called on system wakeup */ @@ -15,16 +15,16 @@ Method(_WAK,1) { /* Update AC status */ - Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0) - if (LNotEqual (Local0, \PWRS)) { - Store (Local0, \PWRS) + Local0 = \_SB.PCI0.LPCB.EC0.ACEX + if (Local0 != \PWRS) { + \PWRS = Local0 Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80) } /* Update LID status */ - Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0) - if (LNotEqual (Local0, \LIDS)) { - Store (Local0, \LIDS) + Local0 = \_SB.PCI0.LPCB.EC0.LIDS + if (Local0 != \LIDS) { + \LIDS = Local0 Notify (\_SB.PCI0.LPCB.EC0.LID0, 0x80) } diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl index 28fa490..7ea38ae 100644 --- a/src/mainboard/google/link/acpi/thermal.asl +++ b/src/mainboard/google/link/acpi/thermal.asl @@ -15,10 +15,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -32,33 +32,33 @@ Method (_TMP, 0, Serialized) { // Get CPU Temperature from TIN9/PECI via EC - Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TIN9 // Check for sensor not calibrated - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNCA) { Return (CTOK(0)) } // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } } @@ -77,10 +77,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -106,34 +106,34 @@ Method (_TMP, 0, Serialized) { // Get Temperature from TIN# set in NVS - Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0) + Local0 = \_SB.PCI0.LPCB.EC0.TINS (TMPS) // Check for sensor not present - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNPR) { Return (CTOK(0)) } // Check for sensor not powered - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TNOP) { Return (CTOK(0)) } // Check for sensor bad reading - If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + If (Local0 == \_SB.PCI0.LPCB.EC0.TBAD) { Return (CTOK(0)) } // Adjust by offset to get Kelvin - Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + Local0 += \_SB.PCI0.LPCB.EC0.TOFS // Convert to 1/10 Kelvin - Multiply (Local0, 10, Local0) + Local0 *= 10 Return (Local0) } /* CTDP Down */ Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -142,7 +142,7 @@ /* CTDP Nominal */ Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -155,19 +155,19 @@ PowerResource (TNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) + \FLVL = 0 \_SB.PCI0.MCHC.STND () Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 \_SB.PCI0.MCHC.STDN () Notify (\_TZ.THRM, 0x81) } @@ -176,18 +176,18 @@ PowerResource (TNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) + \FLVL = 1 Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4fc3acd82023b007d80638bcb71476330ef320 Gerrit-Change-Number: 46176 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/beltino: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46170 ) Change subject: mb/google/beltino: Convert to ASL 2.0 syntax ...................................................................... mb/google/beltino: Convert to ASL 2.0 syntax Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/google/beltino/acpi/mainboard.asl M src/mainboard/google/beltino/acpi/thermal.asl 2 files changed, 57 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/46170/1 diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 3049dbe..10696ff 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -14,9 +14,9 @@ Method (_DSW, 3, NotSerialized) { - Store (NIC_WAKE_GPIO, Local0) + Local0 = NIC_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } @@ -36,9 +36,9 @@ Method (_DSW, 3, NotSerialized) { - Store (WLAN_WAKE_GPIO, Local0) + Local0 = WLAN_WAKE_GPIO - If (LEqual (Arg0, 1)) { + If (Arg0 == 1) { // Enable GPIO as wake source \_SB.PCI0.LPCB.GWAK (Local0) } diff --git a/src/mainboard/google/beltino/acpi/thermal.asl b/src/mainboard/google/beltino/acpi/thermal.asl index 1292af4..96acaeb 100644 --- a/src/mainboard/google/beltino/acpi/thermal.asl +++ b/src/mainboard/google/beltino/acpi/thermal.asl @@ -23,10 +23,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,66 +52,66 @@ // Start fan at state 4 = lowest temp state Method (_INI) { - Store (4, \FLVL) - Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } Method (TCHK, 0, Serialized) { // Get CPU Temperature from PECI via SuperIO TMPIN3 - Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3 // Check for "no reading available" - If (LEqual (Local0, 0x80)) { + If (Local0 == 0x80) { Return (CTOK (FAN0_THRESHOLD_ON)) } // Check for invalid readings - If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + If ((Local0 == 255) || (Local0 == 0)) { Return (CTOK (FAN0_THRESHOLD_ON)) } // PECI raw value is an offset from Tj_max - Subtract (255, Local0, Local1) + Local1 = 255 - Local0 // Handle values greater than Tj_max - If (LGreaterEqual (Local1, \TMAX)) { + If (Local1 >= \TMAX) { Return (CTOK (\TMAX)) } // Subtract from Tj_max to get temperature - Subtract (\TMAX, Local1, Local0) + Local0 = \TMAX - Local1 Return (CTOK (Local0)) } Method (_TMP, 0, Serialized) { // Get temperature from SuperIO in deci-kelvin - Store (TCHK (), Local0) + Local0 = TCHK () // Critical temperature in deci-kelvin - Store (CTOK (\TMAX), Local1) + Local1 = CTOK (\TMAX) - If (LGreaterEqual (Local0, Local1)) { - Store ("CRITICAL TEMPERATURE", Debug) - Store (Local0, Debug) + If (Local0 >= Local1) { + Debug = "CRITICAL TEMPERATURE" + Debug = Local0 // Wait 1 second for SuperIO to re-poll Sleep (1000) // Re-read temperature from SuperIO - Store (TCHK (), Local0) + Local0 = TCHK () - Store ("RE-READ TEMPERATURE", Debug) - Store (Local0, Debug) + Debug = "RE-READ TEMPERATURE" + Debug = Local0 } Return (Local0) } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { Return (CTOK (FAN0_THRESHOLD_ON)) @@ -119,7 +119,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { Return (CTOK (FAN1_THRESHOLD_ON)) @@ -127,7 +127,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { Return (CTOK (FAN2_THRESHOLD_ON)) @@ -135,7 +135,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { Return (CTOK (FAN3_THRESHOLD_ON)) @@ -143,7 +143,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (FAN4_THRESHOLD_OFF)) } Else { Return (CTOK (FAN4_THRESHOLD_ON)) @@ -159,25 +159,23 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (0, \FLVL) - Store (FAN0_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN0_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } @@ -186,25 +184,23 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (1, \FLVL) - Store (FAN1_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN1_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } @@ -213,25 +209,23 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (2, \FLVL) - Store (FAN2_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN2_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } @@ -240,25 +234,23 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (3, \FLVL) - Store (FAN3_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN3_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } @@ -267,25 +259,23 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - If (LNot (_STA ())) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + If (!_STA ()) { + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } Method (_OFF) { If (_STA ()) { - Store (4, \FLVL) - Store (FAN4_PWM, - \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F2PS = FAN4_PWM Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12b6a8264e53ece30ae79da2d79c6f1d302fb357 Gerrit-Change-Number: 46170 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/baskingridge: Convert to ASL 2.0 syntax
by HAOUAS Elyes (Code Review) 04 Nov '20

04 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46182 ) Change subject: mb/intel/baskingridge: Convert to ASL 2.0 syntax ...................................................................... mb/intel/baskingridge: Convert to ASL 2.0 syntax Change-Id: I5897397bdadf86214ceaf90d8cd706e10969d8c1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/intel/baskingridge/acpi/thermal.asl 1 file changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/46182/1 diff --git a/src/mainboard/intel/baskingridge/acpi/thermal.asl b/src/mainboard/intel/baskingridge/acpi/thermal.asl index 487b741..c1bb116 100644 --- a/src/mainboard/intel/baskingridge/acpi/thermal.asl +++ b/src/mainboard/intel/baskingridge/acpi/thermal.asl @@ -20,10 +20,10 @@ // Convert from Degrees C to 1/10 Kelvin for ACPI Method (CTOK, 1) { // 10th of Degrees C - Multiply (Arg0, 10, Local0) + Local0 = Arg0 * 10 // Convert to Kelvin - Add (Local0, 2732, Local0) + Local0 += 2732 Return (Local0) } @@ -52,7 +52,7 @@ } Method (_AC0) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (CTOK (\F0OF)) } Else { Return (CTOK (\F0ON)) @@ -60,7 +60,7 @@ } Method (_AC1) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (CTOK (\F1OF)) } Else { Return (CTOK (\F1ON)) @@ -68,7 +68,7 @@ } Method (_AC2) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (CTOK (\F2OF)) } Else { Return (CTOK (\F2ON)) @@ -76,7 +76,7 @@ } Method (_AC3) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (CTOK (\F3OF)) } Else { Return (CTOK (\F3ON)) @@ -84,7 +84,7 @@ } Method (_AC4) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (CTOK (\F4OF)) } Else { Return (CTOK (\F4ON)) @@ -100,20 +100,20 @@ PowerResource (FNP0, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 0)) { + If (\FLVL <= 0) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (0, \FLVL) - Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 0 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } } @@ -121,20 +121,20 @@ PowerResource (FNP1, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 1)) { + If (\FLVL <= 1) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (1, \FLVL) - Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 1 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } } @@ -142,20 +142,20 @@ PowerResource (FNP2, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 2)) { + If (\FLVL <= 2) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (2, \FLVL) - Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 2 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } } @@ -163,20 +163,20 @@ PowerResource (FNP3, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 3)) { + If (\FLVL <= 3) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (3, \FLVL) - Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 3 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } @@ -184,20 +184,20 @@ PowerResource (FNP4, 0, 0) { Method (_STA) { - If (LLessEqual (\FLVL, 4)) { + If (\FLVL <= 4) { Return (One) } Else { Return (Zero) } } Method (_ON) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } Method (_OFF) { - Store (4, \FLVL) - Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS) + \FLVL = 4 + \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW Notify (\_TZ.THRM, 0x81) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/46182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5897397bdadf86214ceaf90d8cd706e10969d8c1 Gerrit-Change-Number: 46182 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voema: Update dq/dqs mappings
by David Wu (Code Review) 04 Nov '20

04 Nov '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47093 ) Change subject: mb/google/volteer/var/voema: Update dq/dqs mappings ...................................................................... mb/google/volteer/var/voema: Update dq/dqs mappings Update dq/dqs mappings based on voema schematics. BUG=b:169356808 BRANCH=volteer TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I1aae4286278e712bf29ebb15738477828d3f74d6 --- A src/mainboard/google/volteer/variants/voema/Makefile.inc A src/mainboard/google/volteer/variants/voema/memory.c 2 files changed, 68 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/47093/1 diff --git a/src/mainboard/google/volteer/variants/voema/Makefile.inc b/src/mainboard/google/volteer/variants/voema/Makefile.inc new file mode 100644 index 0000000..9064208 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +romstage-y += memory.c diff --git a/src/mainboard/google/volteer/variants/voema/memory.c b/src/mainboard/google/volteer/variants/voema/memory.c new file mode 100644 index 0000000..7d95658 --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg terrador_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 7, 3, 1, 4, 0, 5, 2, 6, }, /* DDR0_DQ0[7:0] */ + { 13, 14, 8, 10, 9, 15, 11, 12 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 1, 2, 7, 6, 3, 5, 4, 0, }, /* DDR1_DQ0[7:0] */ + { 14, 15, 13, 10, 8, 11, 12, 9 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 11, 15, 10, 9, 8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */ + { 5, 6, 4, 0, 7, 2, 3, 1 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 11, 15, 10, 9, 13, 12, 14, 8, }, /* DDR3_DQ0[7:0] */ + { 0, 5, 6, 4, 1, 2, 7, 3 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 7, 2, 3, 1, 4, 0, 5, 6, }, /* DDR4_DQ0[7:0] */ + { 13, 14, 8, 12, 10, 9, 15, 11 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 7, 3, 2, 1, 6, 4, 0, 5, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 12, 8, 11, 13, 9, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 11, 10, 15, 12, 8, 9, 14, 13, }, /* DDR6_DQ0[7:0] */ + { 6, 0, 5, 4, 3, 2, 7, 1 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 9, 10, 11, 8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */ + { 0, 5, 4, 7, 1, 6, 3, 2 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 0, 1 }, /* DDR0_DQS[1:0] */ + [1] = { 0, 1 }, /* DDR1_DQS[1:0] */ + [2] = { 1, 0 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 0, 1 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 1, 0 }, /* DDR6_DQS[1:0] */ + [7] = { 1, 0 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &terrador_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/47093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1aae4286278e712bf29ebb15738477828d3f74d6 Gerrit-Change-Number: 47093 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: AMD/SOC: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION
by Bao Zheng (Code Review) 04 Nov '20

04 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/46062 to review the following change. Change subject: AMD/SOC: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION ...................................................................... AMD/SOC: Change FIRMWARE_LOCATE to FIRMWARE_LOCATION Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/mainboard/google/zork/spd/Makefile.inc M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/fw.cfg M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/fw_cz.cfg M src/soc/amd/stoneyridge/fw_st.cfg M src/southbridge/amd/pi/hudson/Makefile.inc M src/southbridge/amd/pi/hudson/fw_avl.cfg M util/amdfwtool/data_parse.c 9 files changed, 33 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46062/1 diff --git a/src/mainboard/google/zork/spd/Makefile.inc b/src/mainboard/google/zork/spd/Makefile.inc index 1042d91..d6ae475 100644 --- a/src/mainboard/google/zork/spd/Makefile.inc +++ b/src/mainboard/google/zork/spd/Makefile.inc @@ -6,7 +6,7 @@ APCB_SOURCES=$(foreach f, $(basename $(SPD_SOURCES)), $(obj)/APCB_$(f).gen) # APCB binary with magic numbers to be replaced by apcb_edit tool -APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATE)/APCB_magic.bin +APCB_MAGIC_BLOB:=$(FIRMWARE_LOCATION)/APCB_magic.bin $(obj)/APCB_%.gen: $(SPD_SOURCES_DIR)/%.hex \ $(APCB_EDIT_TOOL) \ diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 44145b2..5779072 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -122,7 +122,7 @@ # Design Guide for AMD Family 17h Processors" (PID #55758, NDA only). # -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # Enable secure debug unlock @@ -172,9 +172,9 @@ APOB_NV_BASE=$(shell grep "FMAP_SECTION_RW_MRC_CACHE_START" $(obj)/fmap_config.h | awk '{print $$(NF)}') # type = 0x66 -PSP_UCODE_FILE1=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B1.bin -PSP_UCODE_FILE2=$(FIRMWARE_LOCATE)/UcodePatch_PCO_B0.bin -PSP_UCODE_FILE3=$(FIRMWARE_LOCATE)/UcodePatch_RV2_A0.bin +PSP_UCODE_FILE1=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B1.bin +PSP_UCODE_FILE2=$(FIRMWARE_LOCATION)/UcodePatch_PCO_B0.bin +PSP_UCODE_FILE3=$(FIRMWARE_LOCATION)/UcodePatch_RV2_A0.bin ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location diff --git a/src/soc/amd/picasso/fw.cfg b/src/soc/amd/picasso/fw.cfg index e746d1e..516af7b 100644 --- a/src/soc/amd/picasso/fw.cfg +++ b/src/soc/amd/picasso/fw.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/picasso/PSP +FIRMWARE_LOCATION 3rdparty/amd_blobs/picasso/PSP # type file AMD_PUBKEY_FILE AmdPubKeyRV.bin diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 16b8326..096b1b8 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -102,9 +102,9 @@ ### 0 -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') -ifneq ($(FIRMWARE_LOCATE),) +ifneq ($(FIRMWARE_LOCATION),) ifeq ($(CONFIG_AMD_APU_STONEYRIDGE),y) FIRMWARE_TYPE=ST @@ -126,11 +126,11 @@ OPT_STONEYRIDGE_XHCI_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_XHCI_FWM_FILE), --xhci) OPT_STONEYRIDGE_GEC_FWM_FILE=$(call add_opt_prefix, $(CONFIG_STONEYRIDGE_GEC_FWM_FILE), --gec) -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE).csbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware_$(FIRMWARE_TYPE).csbin +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware_$(FIRMWARE_TYPE)_FN.csbin ifeq ("$(wildcard $(SMUFWM_FILE))","") -SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin +SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE).sbin +SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin endif ifeq ($(FIRMWARE_TYPE),ST) @@ -203,7 +203,7 @@ endif # ifeq ($(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW),y) -else # ifneq ($(FIRMWARE_LOCATE),) +else # ifneq ($(FIRMWARE_LOCATION),) warn_no_amdfw: printf "\n\t** WARNING **\n" @@ -214,6 +214,6 @@ files_added:: warn_no_amdfw -endif # ifneq ($(FIRMWARE_LOCATE),) +endif # ifneq ($(FIRMWARE_LOCATION),) endif # ($(CONFIG_SOC_AMD_STONEYRIDGE),y) diff --git a/src/soc/amd/stoneyridge/fw_cz.cfg b/src/soc/amd/stoneyridge/fw_cz.cfg index acbf136..a6a22f7 100644 --- a/src/soc/amd/stoneyridge/fw_cz.cfg +++ b/src/soc/amd/stoneyridge/fw_cz.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/CZ +FIRMWARE_LOCATION 3rdparty/amd_blobs/stoneyridge/PSP/CZ #PSP AMD_PUBKEY_FILE AmdPubKeyCZ.bin PSPBTLDR_FILE PspBootLoader_prod_CZ.sbin diff --git a/src/soc/amd/stoneyridge/fw_st.cfg b/src/soc/amd/stoneyridge/fw_st.cfg index aa02668..01db8b9 100644 --- a/src/soc/amd/stoneyridge/fw_st.cfg +++ b/src/soc/amd/stoneyridge/fw_st.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/amd_blobs/stoneyridge/PSP/ST +FIRMWARE_LOCATION 3rdparty/amd_blobs/stoneyridge/PSP/ST #XHCI_FWM_FILE xhci.bin #PSP diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 0c06ee2..9792bec 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -78,29 +78,29 @@ ifeq ($(CONFIG_HUDSON_PSP), y) ifeq ($(CONFIG_CPU_AMD_PI_00730F01), y) -FIRMWARE_LOCATE=$(shell grep -e FIRMWARE_LOCATE $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') +FIRMWARE_LOCATION=$(shell grep -e FIRMWARE_LOCATION $(CONFIG_AMDFW_CONFIG_FILE) | awk '{print $$2}') FIRMWARE_TYPE= endif ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) +FIRMWARE_LOCATION=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader_prod_CZ.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecoveryBootLoader_prod_CZ.sbin -PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs_prod_CZ.csbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspTrustlets_prod_CZ.cbin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/TrustletKey_prod_CZ.sbin -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin +PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspBootLoader_prod_CZ.sbin +PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspRecoveryBootLoader_prod_CZ.sbin +PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureOs_prod_CZ.csbin +PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspTrustlets_prod_CZ.cbin +TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/TrustletKey_prod_CZ.sbin +SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware2_prod_CZ.sbin endif -#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin -#SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin -#SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin -#SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin +#SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE).sbin +#SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin +#SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuScs$(FIRMWARE_TYPE).bin +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key endif diff --git a/src/southbridge/amd/pi/hudson/fw_avl.cfg b/src/southbridge/amd/pi/hudson/fw_avl.cfg index 510d6ae..eb3fac3 100644 --- a/src/southbridge/amd/pi/hudson/fw_avl.cfg +++ b/src/southbridge/amd/pi/hudson/fw_avl.cfg @@ -1,6 +1,6 @@ # PSP fw config file -FIRMWARE_LOCATE 3rdparty/blobs/southbridge/amd/avalon/PSP +FIRMWARE_LOCATION 3rdparty/blobs/southbridge/amd/avalon/PSP #PSP AMD_PUBKEY_FILE AmdPubKey.bin PSPBTLDR_FILE PspBootLoader.Bypass.sbin diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index d55b0cc..d1af9e1 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -312,7 +312,7 @@ entries_line_regex, &entries_line_expr); /* Get a line */ - /* Get FIRMWARE_LOCATE in the first loop */ + /* Get FIRMWARE_LOCATION in the first loop */ while (get_input_file_line(config, oneline, MAX_LINE_SIZE) == OK) { /* get line */ /* blank comment */ @@ -328,7 +328,7 @@ /* no match */ continue; } - if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATE") == 0) { + if (strcmp(&(oneline[match[1].rm_so]), "FIRMWARE_LOCATION") == 0) { strcpy(dir, &(oneline[match[2].rm_so])); break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/46062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a3d187fc24ab752dfe61893c15561a92d009fe2 Gerrit-Change-Number: 46062 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: amdfwtool: Change all error output to fprintf stderr
by Bao Zheng (Code Review) 04 Nov '20

04 Nov '20

Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45895 to review the following change. Change subject: amdfwtool: Change all error output to fprintf stderr ...................................................................... amdfwtool: Change all error output to fprintf stderr Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/data_parse.c 2 files changed, 32 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/45895/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 03afc46..c87f1b4 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -523,19 +523,19 @@ fd = open(src_file, O_RDONLY); if (fd < 0) { - printf("Error opening file: %s: %s\n", + fprintf(stderr, "Error opening file: %s: %s\n", src_file, strerror(errno)); return -1; } if (fstat(fd, &fd_stat)) { - printf("fstat error: %s\n", strerror(errno)); + fprintf(stderr, "fstat error: %s\n", strerror(errno)); close(fd); return -2; } if ((size_t)fd_stat.st_size > room) { - printf("Error: %s will not fit. Exiting.\n", src_file); + fprintf(stderr, "Error: %s will not fit. Exiting.\n", src_file); close(fd); return -3; } @@ -543,7 +543,7 @@ bytes = read(fd, dest, (size_t)fd_stat.st_size); close(fd); if (bytes != (ssize_t)fd_stat.st_size) { - printf("Error while reading %s\n", src_file); + fprintf(stderr, "Error while reading %s\n", src_file); return -4; } @@ -746,7 +746,7 @@ } if (count > MAX_PSP_ENTRIES) { - printf("Error: PSP entries exceed max allowed items\n"); + fprintf(stderr, "Error: PSP entries exceed max allowed items\n"); free(ctx->rom); exit(1); } @@ -862,7 +862,7 @@ if (!fw_table[i].size && !fw_table[i].src) continue; /* APOB_NV not used */ if (fw_table[i].src && !fw_table[i].size) { - printf("Error: APOB NV address provided, but no size\n"); + fprintf(stderr, "Error: APOB NV address provided, but no size\n"); free(ctx->rom); exit(1); } @@ -874,7 +874,7 @@ /* APOB_DATA needs destination */ if (fw_table[i].type == AMD_BIOS_APOB && !fw_table[i].dest) { - printf("Error: APOB destination not provided\n"); + fprintf(stderr, "Error: APOB destination not provided\n"); free(ctx->rom); exit(1); } @@ -884,12 +884,12 @@ */ if (fw_table[i].type == AMD_BIOS_BIN) { if (!fw_table[i].dest || !fw_table[i].size) { - printf("Error: BIOS binary destination and uncompressed size are required\n"); + fprintf(stderr, "Error: BIOS binary destination and uncompressed size are required\n"); free(ctx->rom); exit(1); } if (!fw_table[i].filename && !fw_table[i].src) { - printf("Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); + fprintf(stderr, "Error: BIOS binary assumed outside amdfw.rom but no source address given\n"); free(ctx->rom); exit(1); } @@ -1006,7 +1006,7 @@ } if (count > MAX_BIOS_ENTRIES) { - printf("Error: BIOS entries (%d) exceeds max allowed items " + fprintf(stderr, "Error: BIOS entries (%d) exceeds max allowed items " "(%d)\n", count, MAX_BIOS_ENTRIES); free(ctx->rom); exit(1); @@ -1166,7 +1166,7 @@ uint8_t efs_spi_micron_flag) { if ((efs_spi_readmode == 0xFF) || (efs_spi_speed == 0xFF)) { - printf("Error: EFS read mode and SPI speed must be set\n"); + fprintf(stderr, "Error: EFS read mode and SPI speed must be set\n"); return 1; } switch (soc_id) { @@ -1188,7 +1188,7 @@ amd_romsig->qpr_dummy_cycle_f17_mod_00_2f = 0xa; break; default: - printf("Error: EFS Micron flag must be correctly set.\n\n"); + fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); return 1; } break; @@ -1208,13 +1208,13 @@ amd_romsig->micron_detect_f17_mod_30_3f = 0x55; break; default: - printf("Error: EFS Micron flag must be correctly set.\n\n"); + fprintf(stderr, "Error: EFS Micron flag must be correctly set.\n\n"); return 1; } break; case PLATFORM_UNKNOWN: default: - printf("Error: Invalid SOC name.\n\n"); + fprintf(stderr, "Error: Invalid SOC name.\n\n"); return 1; } return 0; @@ -1384,7 +1384,7 @@ case 'C': soc_id = identify_platform(optarg); if (soc_id == PLATFORM_UNKNOWN) { - printf("Error: Invalid SOC name specified\n\n"); + fprintf(stderr, "Error: Invalid SOC name specified\n\n"); retval = 1; } sub = instance = 0; @@ -1407,7 +1407,7 @@ case 'f': ctx.rom_size = (uint32_t)strtoul(optarg, &tmp, 16); if (*tmp != '\0') { - printf("Error: ROM size specified" + fprintf(stderr, "Error: ROM size specified" " incorrectly (%s)\n\n", optarg); retval = 1; } @@ -1415,7 +1415,7 @@ case 'l': dir_location = (uint32_t)strtoul(optarg, &tmp, 16); if (*tmp != '\0') { - printf("Error: Directory Location specified" + fprintf(stderr, "Error: Directory Location specified" " incorrectly (%s)\n\n", optarg); retval = 1; } @@ -1468,18 +1468,18 @@ register_fw_fuse(DEFAULT_SOFT_FUSE_CHAIN); if (!output) { - printf("Error: Output value is not specified.\n\n"); + fprintf(stderr, "Error: Output value is not specified.\n\n"); retval = 1; } if (ctx.rom_size % 1024 != 0) { - printf("Error: ROM Size (%d bytes) should be a multiple of" + fprintf(stderr, "Error: ROM Size (%d bytes) should be a multiple of" " 1024 bytes.\n\n", ctx.rom_size); retval = 1; } if (ctx.rom_size < MIN_ROM_KB * 1024) { - printf("Error: ROM Size (%dKB) must be at least %dKB.\n\n", + fprintf(stderr, "Error: ROM Size (%dKB) must be at least %dKB.\n\n", ctx.rom_size / 1024, MIN_ROM_KB); retval = 1; } @@ -1493,14 +1493,14 @@ rom_base_address = 0xFFFFFFFF - ctx.rom_size + 1; if (dir_location && (dir_location < rom_base_address)) { - printf("Error: Directory location outside of ROM.\n\n"); + fprintf(stderr, "Error: Directory location outside of ROM.\n\n"); return 1; } if (any_location) { if (dir_location & 0x3f) { - printf("Error: Invalid Directory location.\n"); - printf(" Valid locations are 64-byte aligned\n"); + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, " Valid locations are 64-byte aligned\n"); return 1; } } else { @@ -1514,16 +1514,16 @@ case 0xFF020000: /* Fall through */ break; default: - printf("Error: Invalid Directory location.\n"); - printf(" Valid locations are 0xFFFA0000, 0xFFF20000,\n"); - printf(" 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); + fprintf(stderr, "Error: Invalid Directory location.\n"); + fprintf(stderr, " Valid locations are 0xFFFA0000, 0xFFF20000,\n"); + fprintf(stderr, " 0xFFE20000, 0xFFC20000, 0xFF820000, 0xFF020000\n"); return 1; } } ctx.rom = malloc(ctx.rom_size); if (!ctx.rom) { - printf("Error: Failed to allocate memory\n"); + fprintf(stderr, "Error: Failed to allocate memory\n"); return 1; } memset(ctx.rom, 0xFF, ctx.rom_size); @@ -1545,11 +1545,11 @@ retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, efs_spi_speed, efs_spi_micron_flag); if (retval) { - printf("ERROR: Failed to initialize EFS table!\n"); + fprintf(stderr, "ERROR: Failed to initialize EFS table!\n"); return retval; } } else { - printf("WARNING: No SOC name specified.\n"); + fprintf(stderr, "WARNING: No SOC name specified.\n"); } integrate_firmwares(&ctx, amd_romsig, amd_fw_table); @@ -1623,7 +1623,7 @@ retval = 1; close(targetfd); } else { - printf("Error: could not open file: %s\n", output); + fprintf(stderr, "Error: could not open file: %s\n", output); retval = 1; } diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 7d27e52..98453ac 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -38,7 +38,7 @@ result = regcomp(reg, expr, cflags); if (result != 0) { regerror(result, reg, error_msg, ERROR_BUF_SIZE); - printf("%s\n", error_msg); + fprintf(stderr, "%s\n", error_msg); } } @@ -291,7 +291,7 @@ line[strlen(line) - 1] = '\0'; if (strlen(line) == ((size_t) (line_buf_size - 1))) { - printf("The line size in config file should be lower than %d bytes.\n", + fprintf(stderr, "The line size in config file should be lower than %d bytes.\n", MAX_LINE_SIZE); exit(1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45895 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie4ce0f1fb3aea8f12dfae9e5d16589262e7d6ab0 Gerrit-Change-Number: 45895 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-MessageType: newchange

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coreboot-gerrit November 2020