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Change in coreboot[master]: mb/purism/librem_mini: Drop community comments in GPIO config
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47190 ) Change subject: mb/purism/librem_mini: Drop community comments in GPIO config ...................................................................... mb/purism/librem_mini: Drop community comments in GPIO config These add nothing useful to the GPIO config Change-Id: Ieecc9bd67d020e141c3a1f1d387034df5e563068 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47190/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 254510e..04c8614 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -5,8 +5,6 @@ /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { - /* ------- GPIO Community 0 ------- */ - /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ @@ -237,8 +235,6 @@ /* DW0: 0x44000300, DW1: 0x00001000 */ PAD_NC(GPP_G7, DN_20K), - /* ------- GPIO Community 1 ------- */ - /* ------- GPIO Group GPP_D ------- */ /* GPP_D0 - GPIO */ @@ -533,8 +529,6 @@ /* DW0: 0x44000200, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H23, 0, DEEP), - /* ------- GPIO Community 2 ------- */ - /* ------- GPIO Group GPD ------- */ /* GPD0 - BATLOW# */ @@ -585,8 +579,6 @@ /* DW0: 0x04000600, DW1: 0x00000000 */ PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), - /* ------- GPIO Community 4 ------- */ - /* ------- GPIO Group GPP_C ------- */ /* GPP_C0 - SMBCLK */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47190 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieecc9bd67d020e141c3a1f1d387034df5e563068 Gerrit-Change-Number: 47190 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: mb/purism/librem_mini: Update GPIO config
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47206 ) Change subject: mb/purism/librem_mini: Update GPIO config ...................................................................... mb/purism/librem_mini: Update GPIO config Update GPIO config using a fresh dump of inteltool from the vendor (AMI) firmware on a Librem Mini v2, run through intelp2m with parameters '-p cnl -n -ii' Change-Id: I747415fb9ab7b21943d256d248729cb9e2b4b945 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c 1 file changed, 60 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/47206/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 254510e..3a48dc5 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -38,8 +38,8 @@ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* GPP_A7 - GPIO */ - /* DW0: 0x44000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_A7, 0, DEEP), + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), /* GPP_A8 - CLKRUN# */ /* DW0: 0x44000700, DW1: 0x00000000 */ @@ -54,7 +54,7 @@ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* GPP_A11 - GPIO */ - /* DW0: 0x80880201, DW1: 0x00000000 */ + /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_A11, 1, PLTRST), /* GPP_A12 - GPIO */ @@ -74,8 +74,8 @@ PAD_CFG_GPO(GPP_A15, 1, PLTRST), /* GPP_A16 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST), + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_A16, 1, UP_20K, PLTRST), /* GPP_A17 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -115,9 +115,9 @@ /* DW0: 0x44000700, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), - /* GPP_B2 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* GPP_B2 - VRALERT# */ + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* GPP_B3 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -167,17 +167,17 @@ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), - /* GPP_B15 - GSPI0_CS0# */ - /* DW0: 0x00000701, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1), + /* GPP_B15 - GPIO */ + /* DW0: 0x80000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_B15, 1, UP_20K, PLTRST), /* GPP_B16 - GSPI0_CLK */ /* DW0: 0x84000601, DW1: 0x00000000 */ PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1), /* GPP_B17 - GSPI0_MISO */ - /* DW0: 0x44000502, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* DW0: 0x84000502, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_B17, NONE, PLTRST, NF1), /* GPP_B18 - GSPI0_MOSI */ /* DW0: 0x84000601, DW1: 0x00000000 */ @@ -274,8 +274,8 @@ PAD_CFG_GPO(GPP_D7, 1, PLTRST), /* GPP_D8 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D8, 0, PLTRST), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D8, 1, PLTRST), /* GPP_D9 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ @@ -294,16 +294,16 @@ PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE), /* GPP_D13 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D13, 1, RSMRST), + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_D13, NONE), /* GPP_D14 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_D14, 1, PLTRST), /* GPP_D15 - GPIO */ - /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* GPP_D16 - GPIO */ /* DW0: 0x04000200, DW1: 0x00000000 */ @@ -352,8 +352,8 @@ PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST), /* GPP_F3 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00003000 */ - PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST), + /* DW0: 0x84000300, DW1: 0x00003000 */ + PAD_NC(GPP_F3, UP_20K), /* GPP_F4 - CNV_BRI_DT */ /* DW0: 0x44000700, DW1: 0x00003000 */ @@ -494,20 +494,20 @@ PAD_CFG_GPO(GPP_H13, 1, PLTRST), /* GPP_H14 - GPIO */ - /* DW0: 0x84000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H14, 0, PLTRST), + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H14, 1, PLTRST), /* GPP_H15 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ PAD_CFG_GPO(GPP_H15, 1, PLTRST), /* GPP_H16 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H16, 1, RSMRST), + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H16, NONE), /* GPP_H17 - GPIO */ - /* DW0: 0x04000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_H17, 1, RSMRST), + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), /* GPP_H18 - CPU_C10_GATE# */ /* DW0: 0x44000700, DW1: 0x00000000 */ @@ -518,7 +518,7 @@ PAD_CFG_GPO(GPP_H19, 1, PLTRST), /* GPP_H20 - GPIO */ - /* DW0: 0x44000300, DW1: 0x00000000 */ + /* DW0: 0x84000300, DW1: 0x00000000 */ PAD_NC(GPP_H20, NONE), /* GPP_H21 - GPIO */ @@ -538,52 +538,52 @@ /* ------- GPIO Group GPD ------- */ /* GPD0 - BATLOW# */ - /* DW0: 0x04000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00000000 */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1 - ACPRESENT */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* GPD2 - LAN_WAKE# */ - /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003c00 */ + PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), /* GPD3 - PRWBTN# */ - /* DW0: 0x04000702, DW1: 0x00003000 */ - PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + /* DW0: 0x44000702, DW1: 0x00003000 */ + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4 - SLP_S3# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5 - SLP_S4# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6 - SLP_A# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* GPD7 - GPIO */ - /* DW0: 0x04000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPD7, 0, RSMRST), + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD7, 0, DEEP), /* GPD8 - SUSCLK */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 - SLP_WLAN# */ - /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + /* DW0: 0x44000700, DW1: 0x00000000 */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* GPD10 - SLP_S5# */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* GPD11 - LANPHYPC */ - /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + /* DW0: 0x44000600, DW1: 0x00000000 */ + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* ------- GPIO Community 4 ------- */ @@ -634,8 +634,8 @@ PAD_CFG_GPO(GPP_C10, 0, PLTRST), /* GPP_C11 - GPIO */ - /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C11, 1, PLTRST), + /* DW0: 0x40100103, DW1: 0x00000000 */ + PAD_CFG_GPI_APIC(GPP_C11, NONE, DEEP, LEVEL, NONE), /* GPP_C12 - UART1_RXD */ /* DW0: 0x84000603, DW1: 0x00000000 */ @@ -650,8 +650,8 @@ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* GPP_C15 - UART1_CTS# */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), /* GPP_C16 - I2C0_SDA */ /* DW0: 0x84000402, DW1: 0x00000000 */ @@ -776,12 +776,12 @@ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* GPP_E22 - DPPD_CTRLCLK */ - /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E22, NONE, PLTRST, NF1), /* GPP_E23 - DPPD_CTRLDATA */ - /* DW0: 0x44000602, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* DW0: 0x84000603, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_E23, NONE, PLTRST, NF1), }; const struct pad_config *variant_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/47206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I747415fb9ab7b21943d256d248729cb9e2b4b945 Gerrit-Change-Number: 47206 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/purism/librem_mini: Reorganize devicetree
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47188 ) Change subject: mb/purism/librem_mini: Reorganize devicetree ...................................................................... mb/purism/librem_mini: Reorganize devicetree Move registers under devices to which they belong. Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 27 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47188/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index ae19b04..c69f3f6 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -18,30 +18,6 @@ register "SaGv" = "SaGv_Enabled" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # SATA - register "SataMode" = "Sata_AHCI" - register "SataPortsEnable[0]" = "1" # 2.5" - register "SataPortsEnable[2]" = "1" # m.2 - - # Audio - register "PchHdaAudioLinkHda" = "1" - - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower - register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower - register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper - register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear - register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth - register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower - - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper # All SRCCLKREQ pins mapped directly register "PcieClkSrcClkReq[0]" = "0" @@ -59,20 +35,8 @@ register "PcieClkSrcUsage[4]" = "0x80" register "PcieClkSrcUsage[5]" = "0x80" - # PCI Express Root Port #8 x1, Clock 2 (WLAN) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - - # PCI Express Root Port #10 x1, Clock 3 (LAN) - register "PcieRpEnable[9]" = "1" - - # PCI Express Root port #13 x4, Clock 1 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - # Misc register "AcousticNoiseMitigation" = "1" - register "satapwroptimize" = "1" # Power register "PchPmSlpS3MinAssert" = "3" # 50ms @@ -198,6 +162,19 @@ end end end + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper end device pci 14.1 off end # USB xDCI (OTG) device pci 15.0 off end # I2C #0 @@ -210,7 +187,12 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on end # SATA + device pci 17.0 on # SATA + register "SataMode" = "Sata_AHCI" + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "satapwroptimize" = "1" + end device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 off end # UART #2 @@ -224,15 +206,20 @@ device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 (WLAN) register "PcieRpSlotImplemented[7]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" end device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 on # PCI Express Port 10 (LAN) register "PcieRpSlotImplemented[9]" = "1" + register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1d.4 on # PCI Express Port 13 (NVMe) register "PcieRpSlotImplemented[12]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 @@ -244,7 +231,9 @@ device pci 1f.0 on end # LPC Bridge device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller - device pci 1f.3 on end # Intel HDA + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkHda" = "1" + end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI device pci 1f.6 off end # GbE -- To view, visit https://review.coreboot.org/c/coreboot/+/47188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61ca7c1db02646252d7421f8b79dfc8a40b2bdb5 Gerrit-Change-Number: 47188 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: util/intelp2m: Update macros
by Stefan Reinauer (Code Review) 04 Nov '20

04 Nov '20

Stefan Reinauer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45008 ) Change subject: util/intelp2m: Update macros ...................................................................... util/intelp2m: Update macros Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45008 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- M util/intelp2m/platforms/snr/macro.go 1 file changed, 17 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve Maxim Polyakov: Looks good to me, but someone else must approve diff --git a/util/intelp2m/platforms/snr/macro.go b/util/intelp2m/platforms/snr/macro.go index 86cc7b7..43d373e 100644 --- a/util/intelp2m/platforms/snr/macro.go +++ b/util/intelp2m/platforms/snr/macro.go @@ -59,13 +59,13 @@ dw1 := macro.Register(PAD_CFG_DW1) var pull = map[uint8]string{ 0x0: "NONE", - 0x2: "5K_PD", - 0x4: "20K_PD", - 0x9: "1K_PU", - 0xa: "5K_PU", - 0xb: "2K_PU", - 0xc: "20K_PU", - 0xd: "667_PU", + 0x2: "DN_5K", + 0x4: "DN_20K", + 0x9: "UP_1K", + 0xa: "UP_5K", + 0xb: "UP_2K", + 0xc: "UP_20K", + 0xd: "UP_667", 0xf: "NATIVE", } str, valid := pull[dw1.GetTermination()] @@ -91,7 +91,9 @@ if dw0.GetRXLevelEdgeConfiguration() == common.TRIG_LEVEL { if dw0.GetRxInvert() != 0 { // PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) - macro.Add("_INVERT") + macro.Add("_LOW") + } else { + macro.Add("_HIGH") } // PAD_CFG_GPI_APIC(pad, pull, rst) macro.Add("(").Id().Pull().Rstsrc().Add("),") @@ -121,16 +123,16 @@ if dw0.GetGPIOInputRouteSCI() == 0 { return false } + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc() + if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { + macro.Trig() + } // e.g. PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT), if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), // #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ // PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) - macro.Add("_ACPI") - } - macro.Add("_SCI").Add("(").Id().Pull().Rstsrc() - if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { - macro.Trig() + macro.Add(",").Add("EDGE_SINGLE") } macro.Invert().Add("),") return true @@ -143,11 +145,11 @@ if dw0.GetGPIOInputRouteSMI() == 0 { return false } + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc() if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) != 0 { // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), - macro.Add("_ACPI") + macro.Add(",").Add("EDGE_SINGLE") } - macro.Add("_SMI").Add("(").Id().Pull().Rstsrc() if (dw0.GetRXLevelEdgeConfiguration() & common.TRIG_EDGE_SINGLE) == 0 { // e.g. PAD_CFG_GPI_SMI(GPP_E7, NONE, DEEP, LEVEL, NONE), macro.Trig() -- To view, visit https://review.coreboot.org/c/coreboot/+/45008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed Gerrit-Change-Number: 45008 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: util/intelp2m: Update macros
by Stefan Reinauer (Code Review) 04 Nov '20

04 Nov '20

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45008 ) Change subject: util/intelp2m: Update macros ...................................................................... Patch Set 2: Code-Review+2 (3 comments) Agree, it would be nice to fix those. Please make another patch for that if you can https://review.coreboot.org/c/coreboot/+/45008/2/util/intelp2m/platforms/sn… File util/intelp2m/platforms/snr/macro.go: https://review.coreboot.org/c/coreboot/+/45008/2/util/intelp2m/platforms/sn… PS2, Line 93: // PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) > this comment contains an old macro. Please remove or update it. Ack https://review.coreboot.org/c/coreboot/+/45008/2/util/intelp2m/platforms/sn… PS2, Line 132: // e.g. PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), : // #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ : // PAD_CFG_GPI_SCI(pad, pull, rst, EDGE_SINGLE, inv) > same Ack https://review.coreboot.org/c/coreboot/+/45008/2/util/intelp2m/platforms/sn… PS2, Line 150: // e.g. PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), > same Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/45008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0a7dea89fdb69e01f0abe577488f26a5d2bd6ed Gerrit-Change-Number: 45008 Gerrit-PatchSet: 2 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 04 Nov 2020 21:14:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/purism/librem_mini: Adjust GPIO reset values
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47192 ) Change subject: mb/purism/librem_mini: Adjust GPIO reset values ...................................................................... mb/purism/librem_mini: Adjust GPIO reset values Adjust reset values of some pads, using the original vendor firmware as a reference. Change-Id: I2d6a72d2e3597234c8fde86e028b033b3c8d36ae Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/47192/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 9311ca0..ca91a13 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -299,7 +299,7 @@ /* GPP_D15 - GPIO */ /* DW0: 0x44000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + PAD_CFG_GPO(GPP_D15, 1, PLTRST), /* GPP_D16 - GPIO */ /* DW0: 0x04000200, DW1: 0x00000000 */ @@ -533,51 +533,51 @@ /* GPD0 - BATLOW# */ /* DW0: 0x04000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* GPD1 - ACPRESENT */ /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), /* GPD2 - LAN_WAKE# */ /* DW0: 0x04000702, DW1: 0x00003c00 */ - PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + PAD_CFG_NF(GPD2, NATIVE, DEEP, NF1), /* GPD3 - PRWBTN# */ /* DW0: 0x04000702, DW1: 0x00003000 */ - PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), /* GPD4 - SLP_S3# */ /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* GPD5 - SLP_S4# */ /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* GPD6 - SLP_A# */ /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD6, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* GPD7 - GPIO */ /* DW0: 0x04000200, DW1: 0x00000000 */ - PAD_CFG_GPO(GPD7, 0, RSMRST), + PAD_CFG_GPO(GPD7, 0, DEEP), /* GPD8 - SUSCLK */ /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* GPD9 - SLP_WLAN# */ /* DW0: 0x04000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPD9, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* GPD10 - SLP_S5# */ /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD10, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* GPD11 - LANPHYPC */ /* DW0: 0x04000600, DW1: 0x00000000 */ - PAD_CFG_NF(GPD11, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* ------- GPIO Group GPP_C ------- */ @@ -627,7 +627,7 @@ /* GPP_C11 - GPIO */ /* DW0: 0x84000201, DW1: 0x00000000 */ - PAD_CFG_GPO(GPP_C11, 1, PLTRST), + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* GPP_C12 - UART1_RXD */ /* DW0: 0x84000603, DW1: 0x00000000 */ @@ -635,15 +635,15 @@ /* GPP_C13 - UART1_TXD */ /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C13, NONE, PLTRST, NF1), /* GPP_C14 - UART1_RTS# */ /* DW0: 0x44000700, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C14, NONE, PLTRST, NF1), /* GPP_C15 - UART1_CTS# */ /* DW0: 0x44000702, DW1: 0x00000000 */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C15, NONE, PLTRST, NF1), /* GPP_C16 - I2C0_SDA */ /* DW0: 0x84000402, DW1: 0x00000000 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47192 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d6a72d2e3597234c8fde86e028b033b3c8d36ae Gerrit-Change-Number: 47192 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47189 ) Change subject: mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs ...................................................................... mb/purism_librem_mini: Add child device, slot descriptions to PCIe RPs Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 10 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/47189/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index c69f3f6..9fde5e9 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -204,22 +204,29 @@ device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 (WLAN) + device pci 1c.7 on # PCI Express Port 8 + chip drivers/wifi/generic + device pci 00.0 on end # x1 M.2/E 2230 (WLAN) + end register "PcieRpSlotImplemented[7]" = "1" register "PcieRpEnable[7]" = "1" register "PcieRpLtrEnable[7]" = "1" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" end device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 on # PCI Express Port 10 (LAN) + device pci 1d.1 on # PCI Express Port 10 + device pci 00.0 on end # x1 (LAN) register "PcieRpSlotImplemented[9]" = "1" register "PcieRpEnable[9]" = "1" end device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 (NVMe) + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (NVMe) register "PcieRpSlotImplemented[12]" = "1" register "PcieRpEnable[12]" = "1" register "PcieRpLtrEnable[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 -- To view, visit https://review.coreboot.org/c/coreboot/+/47189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id306100fc691dcbde48b65092d0be9d7e73c0722 Gerrit-Change-Number: 47189 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 9

Change in coreboot[master]: mb/purism/librem_mini: drop unused HeciEnabled register
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47187 ) Change subject: mb/purism/librem_mini: drop unused HeciEnabled register ...................................................................... mb/purism/librem_mini: drop unused HeciEnabled register this should have been corrected as part of: 3de90d1 [soc/intel/cnl: Set Heci1Disable depending on devicetree config] Change-Id: I6a103a1de01fc258ef359258a8a64f4c5a181139 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/47187/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 9d2b34b..ae19b04 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -204,10 +204,7 @@ device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 off # Management Engine Interface 1 - # HECI must be enabled w/HAP disable else S3 issues - register "HeciEnabled" = "1" - end + device pci 16.0 off end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection -- To view, visit https://review.coreboot.org/c/coreboot/+/47187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a103a1de01fc258ef359258a8a64f4c5a181139 Gerrit-Change-Number: 47187 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/purism/librem_mini: Increase TDP/PL2 setting
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47186 ) Change subject: mb/purism/librem_mini: Increase TDP/PL2 setting ...................................................................... mb/purism/librem_mini: Increase TDP/PL2 setting PL2 was set artificially low during development when the active cooling fan was not functional, and never corrected once the fan was fixed. Raise PL2 to a value which works with both Librem Mini variants. Change-Id: Ie377392020f73359aed80ddae727adb6f8d06344 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47186/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 308fa69..9d2b34b 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -8,7 +8,7 @@ # Power limit register "power_limits_config" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 28, + .tdp_pl2_override = 51, }" # Enable Enhanced Intel SpeedStep -- To view, visit https://review.coreboot.org/c/coreboot/+/47186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie377392020f73359aed80ddae727adb6f8d06344 Gerrit-Change-Number: 47186 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: mb/purism/librem_mini: Drop devicetree settings which default to 0
by Matt DeVillier (Code Review) 04 Nov '20

04 Nov '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47185 ) Change subject: mb/purism/librem_mini: Drop devicetree settings which default to 0 ...................................................................... mb/purism/librem_mini: Drop devicetree settings which default to 0 All chip registers default to 0, no need to explicitly set them. Change-Id: I056121170d22393484b0ee79bd0815452161a900 Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> --- M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb 1 file changed, 0 insertions(+), 47 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/47185/1 diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 40779a2..308fa69 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -4,16 +4,6 @@ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, }" -# ACPI (soc/intel/cannonlake/acpi.c) - # Disable s0ix - register "s0ix_enable" = "0" - - # PM Timer Enabled - register "PmTimerDisabled" = "0" - - # Disable DPTF - register "dptf_enable" = "0" - # CPU (soc/intel/cannonlake/cpu.c) # Power limit register "power_limits_config" = "{ @@ -28,45 +18,13 @@ register "SaGv" = "SaGv_Enabled" # FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoDisabled, - [PchSerialIoIndexI2C1] = PchSerialIoDisabled, - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoDisabled, - [PchSerialIoIndexSPI0] = PchSerialIoDisabled, - [PchSerialIoIndexSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoDisabled, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - # SATA register "SataMode" = "Sata_AHCI" - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" # 2.5" register "SataPortsEnable[2]" = "1" # m.2 - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" # Audio - register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkDmic0" = "0" - register "PchHdaAudioLinkDmic1" = "0" - register "PchHdaAudioLinkSsp0" = "0" - register "PchHdaAudioLinkSsp1" = "0" - register "PchHdaAudioLinkSsp2" = "0" - register "PchHdaAudioLinkSndw1" = "0" - register "PchHdaAudioLinkSndw2" = "0" - register "PchHdaAudioLinkSndw3" = "0" - register "PchHdaAudioLinkSndw4" = "0" - - # USB - register "SsicPortEnable" = "0" # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper @@ -107,7 +65,6 @@ # PCI Express Root Port #10 x1, Clock 3 (LAN) register "PcieRpEnable[9]" = "1" - register "PcieRpLtrEnable[9]" = "0" # PCI Express Root port #13 x4, Clock 1 (NVMe) register "PcieRpEnable[12]" = "1" @@ -129,10 +86,6 @@ # Serial IRQ Mode register "serirq_mode" = "SERIRQ_CONTINUOUS" -# PMC (soc/intel/cannonlake/pmc.c) - # Disable deep Sx states - register "deep_sx_config" = "0" - # PM Util (soc/intel/cannonlake/pmutil.c) # GPE configuration # Note that GPE events called out in ASL code rely on this -- To view, visit https://review.coreboot.org/c/coreboot/+/47185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I056121170d22393484b0ee79bd0815452161a900 Gerrit-Change-Number: 47185 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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