Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46758 )
Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ......................................................................
soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs
Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs) added these IRQs for Lynx Point and earlier southbridges. Follow suit for Broadwell, since it also supports them. Vendor firmware of the Asus X555LAB laptop also contains these IRQs, as per the disassembled DSDT.
Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/soc/intel/broadwell/pch/acpi/irqlinks.asl 1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/46758/1
diff --git a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl index 0661ff8..8a63ba5 100644 --- a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl @@ -15,7 +15,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -74,7 +74,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -133,7 +133,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -192,7 +192,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -251,7 +251,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -310,7 +310,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -369,7 +369,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -428,7 +428,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46758 )
Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ......................................................................
Patch Set 10: Code-Review+2
Why blow up the patch train with that? A note in the follow-up that using common code involves added missing IRQs would have been enough IMO
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46758 )
Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ......................................................................
Patch Set 10:
Patch Set 10: Code-Review+2
Why blow up the patch train with that? A note in the follow-up that using common code involves added missing IRQs would have been enough IMO
Ah, I see why that was done (timeless check)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46758 )
Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ......................................................................
Patch Set 10:
Patch Set 10: Code-Review+2
Why blow up the patch train with that? A note in the follow-up that using common code involves added missing IRQs would have been enough IMO
Blow up?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46758 )
Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ......................................................................
Patch Set 10:
Patch Set 10:
Patch Set 10: Code-Review+2
Why blow up the patch train with that? A note in the follow-up that using common code involves added missing IRQs would have been enough IMO
Ah, I see why that was done (timeless check)
Yes, I prefer to have a small patch that explains why adding these IRQs is fine, and then a big change that is reproducible. I do this quite often, and if reviewers know about it, then I feel it makes things easier to review. :)
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46758 )
Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ......................................................................
Patch Set 10:
Patch Set 10:
Patch Set 10:
Patch Set 10: Code-Review+2
Why blow up the patch train with that? A note in the follow-up that using common code involves added missing IRQs would have been enough IMO
Ah, I see why that was done (timeless check)
Yes, I prefer to have a small patch that explains why adding these IRQs is fine, and then a big change that is reproducible. I do this quite often, and if reviewers know about it, then I feel it makes things easier to review. :)
Yup, ack ;-) All fine
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46758 )
Change subject: soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs ......................................................................
soc/intel/broadwell/pch/acpi/irqlinks.asl: Add missing IRQs
Commit 2e1f764 (sb/intel/common/acpi/irqlinks.asl: Add missing IRQs) added these IRQs for Lynx Point and earlier southbridges. Follow suit for Broadwell, since it also supports them. Vendor firmware of the Asus X555LAB laptop also contains these IRQs, as per the disassembled DSDT.
Change-Id: If857352dd25ba61c1f09c1ff4358efafdc3a5c73 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46758 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/broadwell/pch/acpi/irqlinks.asl 1 file changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl index 0661ff8..8a63ba5 100644 --- a/src/soc/intel/broadwell/pch/acpi/irqlinks.asl +++ b/src/soc/intel/broadwell/pch/acpi/irqlinks.asl @@ -15,7 +15,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -74,7 +74,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -133,7 +133,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -192,7 +192,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -251,7 +251,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -310,7 +310,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -369,7 +369,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link @@ -428,7 +428,7 @@ Name (_PRS, ResourceTemplate() { IRQ (Level, ActiveLow, Shared) - { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + { 3, 4, 5, 6, 7, 10, 11, 12, 14, 15 } })
// Current Resource Settings for this link
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)