coreboot-gerrit November 2020

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Change in coreboot[master]: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47240 ) Change subject: sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled ...................................................................... sb/intel/lynxpoint/pcie.c: Ensure OBFF is disabled Setting registers 64h[19:18] = 2 and 68h[14:13] = 3 enables OBFF, and setting registers 64h[19:18] = 0 and 68h[14:13] = 0 disables OBFF. Register at offset 0x64 is DCAP2, and offset 0x68 is DCTL2. However, current code doesn't account for this. The result is that register 64h[19:18] = 2 and 68h[14:13] = 0, which means the hardware is OBFF-capable but support is disabled, which makes no sense. Given that reference code and Broadwell both disable OBFF, disable it here too. Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/47240/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 4a245b1..f7d2430 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -645,9 +645,9 @@ pci_and_config32(dev, 0x338, ~(1 << 26)); } - /* Enable LTR in Root Port. */ - pci_or_config32(dev, 0x64, 1 << 11); - pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); + /* Enable LTR in Root Port. Disable OBFF. */ + pci_update_config32(dev, 0x64, ~(3 << 18), 1 << 11); + pci_update_config32(dev, 0x68, ~(3 << 13), 1 << 10); pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); -- To view, visit https://review.coreboot.org/c/coreboot/+/47240 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c1cafdb435ee22909b077128b3ae5bde5543039 Gerrit-Change-Number: 47240 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47042 ) Change subject: sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function ...................................................................... sb/intel/lynxpoint/lpc.c: Relocate `enable_hpet` function Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/47042/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 2e4dcd0..373bafc 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -73,6 +73,25 @@ #endif } +static void enable_hpet(struct device *const dev) +{ + u32 reg32; + size_t i; + + /* Assign unique bus/dev/fn for each HPET */ + for (i = 0; i < 8; ++i) + pci_write_config16(dev, LPC_HnBDF(i), + PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); + + /* Move HPET to default address 0xfed00000 and enable it */ + reg32 = RCBA32(HPTC); + reg32 |= (1 << 7); // HPET Address Enable + reg32 &= ~(3 << 0); + RCBA32(HPTC) = reg32; + /* Read it back to stick. It's affected by posted write syndrome. */ + RCBA32(HPTC); +} + /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control * 0x00 - 0000 = Reserved * 0x01 - 0001 = Reserved @@ -359,25 +378,6 @@ RCBA32_OR(0x33c8, (1 << 15)); } -static void enable_hpet(struct device *const dev) -{ - u32 reg32; - size_t i; - - /* Assign unique bus/dev/fn for each HPET */ - for (i = 0; i < 8; ++i) - pci_write_config16(dev, LPC_HnBDF(i), - PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i); - - /* Move HPET to default address 0xfed00000 and enable it */ - reg32 = RCBA32(HPTC); - reg32 |= (1 << 7); // HPET Address Enable - reg32 &= ~(3 << 0); - RCBA32(HPTC) = reg32; - /* Read it back to stick. It's affected by posted write syndrome. */ - RCBA32(HPTC); -} - static void enable_clock_gating(struct device *dev) { /* LynxPoint Mobile */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I957556bcb3f2d793ed2d9a9c966b2081f9be090c Gerrit-Change-Number: 47042 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/lpc.c: Correct GPI routing check
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47044 ) Change subject: sb/intel/lynxpoint/lpc.c: Correct GPI routing check ...................................................................... sb/intel/lynxpoint/lpc.c: Correct GPI routing check Code does not match comment, but this time the comment is right. Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/47044/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ee0dc53..1845273 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -265,7 +265,7 @@ * Set the board's GPI routing on LynxPoint-H. * This is done as part of GPIO configuration on LynxPoint-LP. */ - if (pch_is_lp()) + if (!pch_is_lp()) pch_gpi_routing(dev, config); /* GPE setup based on device tree configuration */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e277a802c68c8a4e858b2e33e7ec69b41dd9773 Gerrit-Change-Number: 47044 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47234 ) Change subject: sb/intel/lynxpoint: Correct SATA DTLE IOBP registers ...................................................................... sb/intel/lynxpoint: Correct SATA DTLE IOBP registers Testing shows that these registers are backwards. Use the definitions from Broadwell instead. All affected boards use the same value for both. Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/47234/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 66cd05e..429dcc0 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -267,10 +267,10 @@ /* SATA IOBP Registers */ #define SATA_IOBP_SP0G3IR 0xea000151 #define SATA_IOBP_SP1G3IR 0xea000051 -#define SATA_IOBP_SP0DTLE_DATA 0xea002550 -#define SATA_IOBP_SP0DTLE_EDGE 0xea002554 -#define SATA_IOBP_SP1DTLE_DATA 0xea002750 -#define SATA_IOBP_SP1DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP0DTLE_DATA 0xea002750 +#define SATA_IOBP_SP0DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP1DTLE_DATA 0xea002550 +#define SATA_IOBP_SP1DTLE_EDGE 0xea002554 #define SATA_DTLE_MASK 0xF #define SATA_DTLE_DATA_SHIFT 24 -- To view, visit https://review.coreboot.org/c/coreboot/+/47234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie47c9fddc2e9e15ce4c64821ea3a69356ac31b1a Gerrit-Change-Number: 47234 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel: Don't set ACPI_EN twice
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47207 ) Change subject: sb/intel: Don't set ACPI_EN twice ...................................................................... sb/intel: Don't set ACPI_EN twice It is already done once when enabling PMBASE in early init. Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/ibexpeak/early_pch.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/lpc.c 7 files changed, 3 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/47207/1 diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 452adb1..767d3ad 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -222,7 +222,7 @@ pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index df5625a..2c3b10a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -44,9 +44,6 @@ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index eb59eb0..ea73322 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -35,9 +35,6 @@ */ static void i82801gx_enable_ioapic(struct device *dev) { - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02); /* diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c index ace09e2..df380c5 100644 --- a/src/southbridge/intel/ibexpeak/early_pch.c +++ b/src/southbridge/intel/ibexpeak/early_pch.c @@ -33,7 +33,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); printk(BIOS_DEBUG, " done.\n"); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 8269dd9..4f622dd 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -39,9 +39,6 @@ { u32 reg32; - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x01); /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read(VIO_APIC_VADDR, 0x01); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 465aa1e..8cc6a87 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -40,7 +40,7 @@ pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); /* Enable ACPI BAR */ - pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, ACPI_EN); pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 4286e6ca..b56ace8 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -41,9 +41,6 @@ pci_write_config16(dev, LPC_IBDF, PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3); - /* Enable ACPI I/O range decode */ - pci_write_config8(dev, ACPI_CNTL, ACPI_EN); - set_ioapic_id(VIO_APIC_VADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47207 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14289c9164ee1488c192fce721d86c89fa5cc736 Gerrit-Change-Number: 47207 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits
by Angel Pons (Code Review) 07 Nov '20

07 Nov '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47038 ) Change subject: sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits ...................................................................... sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits For all these southbridges, the lower nibble of PCICMD is read-only. Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/i82801dx/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 7 files changed, 0 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/47038/1 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index df5625a..a498f87 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -519,11 +519,6 @@ /* Print detected platform */ report_pch_info(dev); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c index dec1266..f207c11 100644 --- a/src/southbridge/intel/i82801dx/lpc.c +++ b/src/southbridge/intel/i82801dx/lpc.c @@ -252,11 +252,6 @@ static void lpc_init(struct device *dev) { - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - i82801dx_enable_acpi(dev); /* IO APIC initialization. */ i82801dx_enable_ioapic(dev); diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index eb59eb0..721735c 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -341,11 +341,6 @@ { printk(BIOS_DEBUG, "i82801gx: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ i82801gx_enable_ioapic(dev); diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index ad7141a..652da54 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -355,11 +355,6 @@ { printk(BIOS_DEBUG, "i82801ix: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ i82801ix_enable_apic(dev); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 2f7b516..1f4cf29 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -347,11 +347,6 @@ { printk(BIOS_DEBUG, "i82801jx: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ i82801jx_enable_apic(dev); diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index 8269dd9..dddecd7 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -433,11 +433,6 @@ { printk(BIOS_DEBUG, "pch: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ pch_enable_ioapic(dev); diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index a168de0..2e4dcd0 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -488,11 +488,6 @@ { printk(BIOS_DEBUG, "pch: %s\n", __func__); - /* Set the value for PCI command register. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL | - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - /* IO APIC initialization. */ pch_enable_ioapic(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/47038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c Gerrit-Change-Number: 47038 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Configure GPIOs to enable DMIC
by Subrata Banik (Code Review) 07 Nov '20

07 Nov '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47279 ) Change subject: mb/intel/adlrvp: Configure GPIOs to enable DMIC ...................................................................... mb/intel/adlrvp: Configure GPIOs to enable DMIC The patch configures GPIO pins to enable DMIC. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47279 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved V Sowmya: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index c7029fc1..f91b94f 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -224,17 +224,17 @@ /* SNDW1_DATA */ PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SNDW2_CLK */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* SNDW2_DATA */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* SNDW3_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* SNDW3_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), /* SNDW4_CLK */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/47279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2907737071f7d6b3c88c492d90edf8455d1fa50a Gerrit-Change-Number: 47279 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel: Enable ALC711 Audio codec over SNDW0 link
by Subrata Banik (Code Review) 07 Nov '20

07 Nov '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47278 ) Change subject: mb/intel: Enable ALC711 Audio codec over SNDW0 link ...................................................................... mb/intel: Enable ALC711 Audio codec over SNDW0 link The patch enables ALC711 Audio codec. Test=Verified on ADL RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47278 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb M src/soc/intel/alderlake/soundwire.c 3 files changed, 7 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved V Sowmya: Looks good to me, approved diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 97b4bf7..2a3dbb0 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -13,6 +13,7 @@ select DRIVERS_SPI_ACPI select SOC_INTEL_ALDERLAKE select HAVE_SPD_IN_CBFS + select DRIVERS_SOUNDWIRE_ALC711 config CHROMEOS bool diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index 44c324b..ce55fa3 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -258,6 +258,11 @@ device pci 1f.3 on chip drivers/intel/soundwire device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end end end end # Intel Audio SNDW diff --git a/src/soc/intel/alderlake/soundwire.c b/src/soc/intel/alderlake/soundwire.c index 38a2c37..9899df3 100644 --- a/src/soc/intel/alderlake/soundwire.c +++ b/src/soc/intel/alderlake/soundwire.c @@ -37,8 +37,7 @@ static struct intel_soundwire_controller intel_controller = { .acpi_address = 0x40000000, .sdw = { - /* TODO: Verified Audio in nocodec mode, add codec support */ - .master_list_count = 0 + .master_list_count = 1 } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/47278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f480dad1047cebd7ffc66e0104ff10cacc300b Gerrit-Change-Number: 47278 Gerrit-PatchSet: 3 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers
by V Sowmya (Code Review) 07 Nov '20

07 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47288 ) Change subject: mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers ...................................................................... mb/intel/adlrvp: Enable TCSS xDCI, TBT PCIe RP and DMA controllers This patch enables TCSS xDCI, TBT PCIe root ports and DMA controllers for ADLRVP. BUG=:b:170607415 TEST=Built and booted on ADLRVP. Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/47288/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index ea75d5d..44c324b 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -173,17 +173,17 @@ device pci 04.0 on end # DPTF device pci 05.0 on end # IPU device pci 06.0 on end # PEG60 - device pci 07.0 off end # TBT_PCIe0 - device pci 07.1 off end # TBT_PCIe1 - device pci 07.2 off end # TBT_PCIe2 - device pci 07.3 off end # TBT_PCIe3 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe1 + device pci 07.2 on end # TBT_PCIe2 + device pci 07.3 on end # TBT_PCIe3 device pci 08.0 off end # GNA device pci 09.0 off end # NPK device pci 0a.0 off end # Crash-log SRAM device pci 0d.0 on end # USB xHCI - device pci 0d.1 off end # USB xDCI (OTG) - device pci 0d.2 off end # TBT DMA0 - device pci 0d.3 off end # TBT DMA1 + device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.2 on end # TBT DMA0 + device pci 0d.3 on end # TBT DMA1 device pci 0e.0 off end # VMD device pci 10.0 off end device pci 10.1 off end -- To view, visit https://review.coreboot.org/c/coreboot/+/47288 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabd6cc7c589d1c20cde9d66c0a63e2cf16316b33 Gerrit-Change-Number: 47288 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/intel/adlrvp: Configure the HPD GPIO's
by V Sowmya (Code Review) 07 Nov '20

07 Nov '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47290 ) Change subject: mb/intel/adlrvp: Configure the HPD GPIO's ...................................................................... mb/intel/adlrvp: Configure the HPD GPIO's This patch configures the HPD1 and HPD2 GPIO's. BUG=:b:170607415 TEST=Built and booted adlrvp. Verified the hotplug functionality is working. Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/47290/1 diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c index e142e88..cda183d 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c @@ -277,6 +277,10 @@ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + /* HPD_1 (A19) and HPD_2 (A20) pins */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* IMGCLKOUT */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/47290 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied2d4c56220212a15103e9a2fbd01ce6f0811a74 Gerrit-Change-Number: 47290 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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