coreboot-gerrit November 2020

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Change in coreboot[master]: mb/google/volteer/eldrid: Describe the privacy_gpio
by Ricardo Ribalda (Code Review) 09 Nov '20

09 Nov '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46964 ) Change subject: mb/google/volteer/eldrid: Describe the privacy_gpio ...................................................................... mb/google/volteer/eldrid: Describe the privacy_gpio Add information regarding the privacy pin on the overridetree and the gpio. Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/mainboard/google/volteer/variants/eldrid/gpio.c M src/mainboard/google/volteer/variants/eldrid/overridetree.cb 2 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/46964/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index 4f6650b..3d627e3 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -63,7 +63,7 @@ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* D4 : IMGCLKOUT0# ==> CAMMERA_SWITCH */ - PAD_CFG_GPI(GPP_D4, NONE, DEEP), + PAD_CFG_GPI_INT(GPP_D4, NONE, PLTRST, EDGE_BOTH), /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 7fd6576..3efa40c 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -68,6 +68,21 @@ }" device domain 0 on + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "privacy_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH_ACTIVE_LOW(GPP_D4)" + device usb 3.2 on end + end + end + end + end + device ref dptf on # DPTF Policy for Eldrid board chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/46964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab19a863715ba5a928dd7c16402d398e5475edc Gerrit-Change-Number: 46964 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

4 13

Change in coreboot[master]: mb/google/hatch/jinlon: Describe the privacy_gpio
by Ricardo Ribalda (Code Review) 09 Nov '20

09 Nov '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46962 ) Change subject: mb/google/hatch/jinlon: Describe the privacy_gpio ...................................................................... mb/google/hatch/jinlon: Describe the privacy_gpio Add information regarding the privacy pin on the overridetree and gpio. Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/mainboard/google/hatch/variants/jinlon/gpio.c M src/mainboard/google/hatch/variants/jinlon/overridetree.cb 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/46962/1 diff --git a/src/mainboard/google/hatch/variants/jinlon/gpio.c b/src/mainboard/google/hatch/variants/jinlon/gpio.c index 88f0092..3b6a76f 100644 --- a/src/mainboard/google/hatch/variants/jinlon/gpio.c +++ b/src/mainboard/google/hatch/variants/jinlon/gpio.c @@ -18,6 +18,8 @@ * using this pin, expose this pin to driver. */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* D4 : Camera Privacy Status */ + PAD_CFG_GPI(GPP_D4, NONE, DEEP), /* E0 : View Angle Management */ PAD_CFG_GPO(GPP_E0, 0, DEEP), /* F3 : MEM_STRAP_3 */ diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index fc3bb85..22cc5d3 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -80,6 +80,16 @@ device generic 0 on end end end # Integrated Graphics Device + device pci 14.0 on + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D4)" + device usb 2.6 on end + end + end + end + end # USB xHCI device pci 15.0 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" -- To view, visit https://review.coreboot.org/c/coreboot/+/46962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa628dda03f3f65976850aeabaf516f528a921b7 Gerrit-Change-Number: 46962 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

5 21

Change in coreboot[master]: acpi: Add support for privacy_gpio
by Ricardo Ribalda (Code Review) 09 Nov '20

09 Nov '20

Ricardo Ribalda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46961 ) Change subject: acpi: Add support for privacy_gpio ...................................................................... acpi: Add support for privacy_gpio Some devices, such as cameras, can implement a physical switch to disable the input on demand. Think of it like the typical privacy sticker on the notebooks, but more elegant. In order to notify the system about the status this feature, a GPIO is typically used. The map between a GPIO and the feature is done via ACPI, the same way as the reset_gpio works. This patch implements an extra field for the described privacy gpio. This gpio does not require any extra handling from the power management. Change-Id: Idcc65c9a13eca6f076ac3c68aaa1bed3c481df3d Signed-off-by: Ricardo Ribalda <ribalda(a)chromium.org> --- M src/drivers/usb/acpi/chip.h M src/drivers/usb/acpi/usb_acpi.c 2 files changed, 18 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/46961/1 diff --git a/src/drivers/usb/acpi/chip.h b/src/drivers/usb/acpi/chip.h index 8cd9268..4a55cc6 100644 --- a/src/drivers/usb/acpi/chip.h +++ b/src/drivers/usb/acpi/chip.h @@ -45,6 +45,7 @@ struct acpi_pld custom_pld; struct acpi_gpio reset_gpio; + struct acpi_gpio privacy_gpio; }; #endif /* __USB_ACPI_CHIP_H__ */ diff --git a/src/drivers/usb/acpi/usb_acpi.c b/src/drivers/usb/acpi/usb_acpi.c index d33b7de..9b45483 100644 --- a/src/drivers/usb/acpi/usb_acpi.c +++ b/src/drivers/usb/acpi/usb_acpi.c @@ -13,10 +13,13 @@ /* * Return false if reset GPIO is not provided. */ - if (cfg->reset_gpio.pin_count == 0) - return false; + if (cfg->reset_gpio.pin_count) + return true; - return true; + if (cfg->privacy_gpio.pin_count) + return true; + + return false; } static void usb_acpi_fill_ssdt_generator(const struct device *dev) @@ -49,15 +52,23 @@ /* Resources */ if (usb_acpi_add_gpios_to_crs(config) == true) { struct acpi_dp *dsd; + int idx = 0; acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); - acpi_device_write_gpio(&config->reset_gpio); + if (config->reset_gpio.pin_count) + acpi_device_write_gpio(&config->reset_gpio); + if (config->privacy_gpio.pin_count) + acpi_device_write_gpio(&config->privacy_gpio); acpigen_write_resourcetemplate_footer(); dsd = acpi_dp_new_table("_DSD"); - acpi_dp_add_gpio(dsd, "reset-gpio", path, 0, 0, - config->reset_gpio.active_low); + if (config->reset_gpio.pin_count) + acpi_dp_add_gpio(dsd, "reset-gpio", path, idx++, 0, + config->reset_gpio.active_low); + if (config->privacy_gpio.pin_count) + acpi_dp_add_gpio(dsd, "privacy-gpio", path, idx++, 0, + config->privacy_gpio.active_low); acpi_dp_write(dsd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/46961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcc65c9a13eca6f076ac3c68aaa1bed3c481df3d Gerrit-Change-Number: 46961 Gerrit-PatchSet: 1 Gerrit-Owner: Ricardo Ribalda <ribalda(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Create drobit variant
by Frank Chu (Code Review) 09 Nov '20

09 Nov '20

Hello Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/47358 to look at the new patch set (#2). Change subject: mb/google/volteer: Create drobit variant ...................................................................... mb/google/volteer: Create drobit variant Create the drobit variant of the volteer. BUG=b: BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Ib3dca73dea26c0d267d8e0e725d712f750810b06 --- A src/mainboard/google/volteer/variants/drobit/Makefile.inc A src/mainboard/google/volteer/variants/drobit/gpio.c A src/mainboard/google/volteer/variants/drobit/include/variant/ec.h A src/mainboard/google/volteer/variants/drobit/include/variant/gpio.h A src/mainboard/google/volteer/variants/drobit/memory.c A src/mainboard/google/volteer/variants/drobit/memory/Makefile.inc A src/mainboard/google/volteer/variants/drobit/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/drobit/memory/mem_list_variant.txt A src/mainboard/google/volteer/variants/drobit/overridetree.cb 9 files changed, 532 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47358/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/47358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3dca73dea26c0d267d8e0e725d712f750810b06 Gerrit-Change-Number: 47358 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/google/dedede/variants/magolor: Update Power Limit2 minimum value
by Sumeet R Pawnikar (Code Review) 09 Nov '20

09 Nov '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47285 ) Change subject: mb/google/dedede/variants/magolor: Update Power Limit2 minimum value ...................................................................... mb/google/dedede/variants/magolor: Update Power Limit2 minimum value Update Power Limit2 (PL2) minimum value to the same as maximum value for magolor board. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=b:168353037 BRANCH=None TEST=Build and test on magolor board Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/47285/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 625546e..33b89d6 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -92,7 +92,7 @@ .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ - .min_power = 7000, + .min_power = 12000, .max_power = 12000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, -- To view, visit https://review.coreboot.org/c/coreboot/+/47285 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74e960de506d366cba2c8aefb23f9e69337fd163 Gerrit-Change-Number: 47285 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log
by Tim Wawrzynczak (Code Review) 09 Nov '20

09 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47183 ) Change subject: soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log ...................................................................... soc/intel/jasperlake: Add PCH PCIe RPs wake up events to event log All wakes by a PCH PCIe root port were lumped under one event source; this commit splits them up so each root port gets its own ID in the event log. BUG=b:172279061 BRANCH=volteer Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/jasperlake/elog.c 1 file changed, 41 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47183/1 diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 235dc6e..d383924 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -2,11 +2,14 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> +#include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> + +#define PCIE_ROOT_PORT_STATUS 0x60 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +23,41 @@ } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; + }; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + const uint32_t pme_status = pci_s_read_config32( + pme_map[i].devfn, + PCIE_ROOT_PORT_STATUS); + + if (pme_status == 0xFFFFFFFF || !(pme_status & BIT(16))) + continue; + + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -30,9 +68,9 @@ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - /* PCI Express (TODO: determine wake device) */ + /* PCI Express */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47183 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icdb10043700c20ddb6ae93747a731005fd233a70 Gerrit-Change-Number: 47183 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log
by Tim Wawrzynczak (Code Review) 09 Nov '20

09 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47182 ) Change subject: soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log ...................................................................... soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log All wakes by a PCH PCIe root port were lumped under one event source; this commit splits them up so each root port gets its own ID in the event log. BUG=b:172279061 BRANCH=volteer Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0 --- M src/soc/intel/tigerlake/elog.c 1 file changed, 42 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/47182/1 diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index 84f0a7e..256675d 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -2,11 +2,15 @@ #include <bootstate.h> #include <console/console.h> -#include <stdint.h> +#include <device/pci_ops.h> #include <elog.h> #include <intelblocks/pmclib.h> #include <soc/pci_devs.h> #include <soc/pm.h> +#include <stdint.h> +#include <types.h> + +#define PCIE_ROOT_PORT_STATUS 0x60 static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { @@ -20,6 +24,41 @@ } } +static void pch_log_rp_wake_source(void) +{ + size_t i; + struct pme_map { + pci_devfn_t devfn; + unsigned int wake_source; + }; + + const struct pme_map pme_map[] = { + { PCH_DEVFN_PCIE1, ELOG_WAKE_SOURCE_PME_PCIE1 }, + { PCH_DEVFN_PCIE2, ELOG_WAKE_SOURCE_PME_PCIE2 }, + { PCH_DEVFN_PCIE3, ELOG_WAKE_SOURCE_PME_PCIE3 }, + { PCH_DEVFN_PCIE4, ELOG_WAKE_SOURCE_PME_PCIE4 }, + { PCH_DEVFN_PCIE5, ELOG_WAKE_SOURCE_PME_PCIE5 }, + { PCH_DEVFN_PCIE6, ELOG_WAKE_SOURCE_PME_PCIE6 }, + { PCH_DEVFN_PCIE7, ELOG_WAKE_SOURCE_PME_PCIE7 }, + { PCH_DEVFN_PCIE8, ELOG_WAKE_SOURCE_PME_PCIE8 }, + { PCH_DEVFN_PCIE9, ELOG_WAKE_SOURCE_PME_PCIE9 }, + { PCH_DEVFN_PCIE10, ELOG_WAKE_SOURCE_PME_PCIE10 }, + { PCH_DEVFN_PCIE11, ELOG_WAKE_SOURCE_PME_PCIE11 }, + { PCH_DEVFN_PCIE12, ELOG_WAKE_SOURCE_PME_PCIE12 }, + }; + + for (i = 0; i < MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_map)); ++i) { + uint32_t pme_status = pci_s_read_config32( + pme_map[i].devfn, + PCIE_ROOT_PORT_STATUS); + + if (pme_status == 0xFFFFFFFF || !(pme_status & BIT(16))) + continue; + + elog_add_event_wake(pme_map[i].wake_source, 0); + } +} + static void pch_log_wake_source(struct chipset_power_state *ps) { /* Power Button */ @@ -30,9 +69,9 @@ if (ps->pm1_sts & RTC_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); - /* PCI Express (TODO: determine wake device) */ + /* PCI Express */ if (ps->pm1_sts & PCIEXPWAK_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + pch_log_rp_wake_source(); /* PME (TODO: determine wake device) */ if (ps->gpe0_sts[GPE_STD] & PME_STS) -- To view, visit https://review.coreboot.org/c/coreboot/+/47182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icebcac3b69c605ecf6df37733b641397ea3c3ad0 Gerrit-Change-Number: 47182 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: device: Add pci_s_dev_is_wake_source function
by Tim Wawrzynczak (Code Review) 09 Nov '20

09 Nov '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47260 ) Change subject: device: Add pci_s_dev_is_wake_source function ...................................................................... device: Add pci_s_dev_is_wake_source function This function is the SIMPLE_DEVICE equivalent of `pci_dev_is_wake_source`, which is required so that elog can use this function, which since it runs in SMM as well, it uses the simple device model. Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie5583c04366c9a16bc1b00a6892d39eeafe5da49 --- M src/device/pci_ops.c M src/include/device/pci_ops.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/47260/1 diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 90f45bf..cb833f8 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -78,3 +78,18 @@ { die("PCI: dev is NULL!\n"); } + +bool pci_s_dev_is_wake_source(pci_devfn_t dev) +{ + unsigned int pm_cap; + uint16_t pmcs; + + pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM); + if (!pm_cap) + return false; + + pmcs = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL); + + /* PCI Device is a wake source if PME_ENABLE and PME_STATUS are set in PMCS register. */ + return (pmcs & PCI_PM_CTRL_PME_ENABLE) && (pmcs & PCI_PM_CTRL_PME_STATUS); +} diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index cdf02d6..1738cd1 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -209,4 +209,12 @@ return pci_s_find_capability(PCI_BDF(dev), cap); } +/* + * Determine if the given PCI device is the source of wake from sleep by checking PME_STATUS and + * PME_ENABLE bits in PM control and status register. + * + * Returns true if PCI device is wake source, false otherwise. + */ +bool pci_s_dev_is_wake_source(pci_devfn_t dev); + #endif /* PCI_OPS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie5583c04366c9a16bc1b00a6892d39eeafe5da49 Gerrit-Change-Number: 47260 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: mb/google/dedede/var/boten: Add LTE power on/off sequence
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44588 ) Change subject: mb/google/dedede/var/boten: Add LTE power on/off sequence ...................................................................... mb/google/dedede/var/boten: Add LTE power on/off sequence LTE module used in boten has a specific power on/off sequence. GPIOs related to power sequnce are: * GPP_A10 - LTE_PWR_OFF_R_ODL * GPP_H17 - LTE_RESET_R_ODL 1. Power on: GPP_A10 -> 20ms -> GPP_H17 2. Power off: GPP_H17 -> 10ms -> GPP_A10 3. Warm reset: Power off -> 500ms -> Power on Configure the GPIOs based on these requirements. BUG=b:163100335 TEST=Build and boot Boten to OS. Ensure that the LTE module power sequence requirements are met. Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44588 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/variants/boten/Makefile.inc M src/mainboard/google/dedede/variants/boten/gpio.c M src/mainboard/google/dedede/variants/boten/overridetree.cb A src/mainboard/google/dedede/variants/boten/variant.c 4 files changed, 35 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marco Chen: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/boten/Makefile.inc b/src/mainboard/google/dedede/variants/boten/Makefile.inc index a352709..67a7ab2 100644 --- a/src/mainboard/google/dedede/variants/boten/Makefile.inc +++ b/src/mainboard/google/dedede/variants/boten/Makefile.inc @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0-only ramstage-y += gpio.c + +smm-y += variant.c diff --git a/src/mainboard/google/dedede/variants/boten/gpio.c b/src/mainboard/google/dedede/variants/boten/gpio.c index f889c7f..c27daa4 100644 --- a/src/mainboard/google/dedede/variants/boten/gpio.c +++ b/src/mainboard/google/dedede/variants/boten/gpio.c @@ -7,6 +7,9 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { + /* A10 : WWAN_EN => LTE_PWR_OFF_ODL */ + PAD_CFG_GPO(GPP_A10, 0, PLTRST), + /* C12 : AP_PEN_DET_ODL */ PAD_CFG_GPI_SCI(GPP_C12, NONE, DEEP, EDGE_SINGLE, NONE), /* C18 : AP_I2C_EMR_SDA */ @@ -38,6 +41,8 @@ PAD_NC(GPP_H6, NONE), /* H7 : AP_I2C_CAM_SCL */ PAD_NC(GPP_H7, NONE), + /* H17 : WWAN_RST_L => LTE_RESET_R_ODL */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), }; const struct pad_config *variant_override_gpio_table(size_t *num) diff --git a/src/mainboard/google/dedede/variants/boten/overridetree.cb b/src/mainboard/google/dedede/variants/boten/overridetree.cb index 4ec6457..4966aac 100644 --- a/src/mainboard/google/dedede/variants/boten/overridetree.cb +++ b/src/mainboard/google/dedede/variants/boten/overridetree.cb @@ -65,6 +65,11 @@ chip drivers/usb/acpi register "desc" = ""LTE"" register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)" + register "reset_off_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "enable_delay_ms" = "20" device usb 2.3 on end end chip drivers/usb/acpi diff --git a/src/mainboard/google/dedede/variants/boten/variant.c b/src/mainboard/google/dedede/variants/boten/variant.c new file mode 100644 index 0000000..2540fc7 --- /dev/null +++ b/src/mainboard/google/dedede/variants/boten/variant.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi.h> +#include <baseboard/variants.h> +#include <delay.h> +#include <gpio.h> + +static void power_off_lte_module(void) +{ + gpio_output(GPP_H17, 0); + mdelay(10); + gpio_output(GPP_A10, 0); +} + +void variant_smi_sleep(u8 slp_typ) +{ + /* + * Once the FW_CONFIG is provisioned, power off LTE module only under + * the situation where it is stuffed. + */ + if (slp_typ == ACPI_S5) + power_off_lte_module(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44588 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d5d21ce5267f147b332a4c9b01a29b3b8ccfb8 Gerrit-Change-Number: 44588 Gerrit-PatchSet: 12 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Alec Wang <alec.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede: Add support for variant specific SMI sleep flow
by Patrick Georgi (Code Review) 09 Nov '20

09 Nov '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44587 ) Change subject: mb/google/dedede: Add support for variant specific SMI sleep flow ...................................................................... mb/google/dedede: Add support for variant specific SMI sleep flow This support is required to power off certain components that exist only in certain variants. BUG=None TEST=Build and boot Boten to OS. Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44587 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/dedede/smihandler.c M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Marco Chen: Looks good to me, approved Peichao Wang: Looks good to me, approved diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 20f0207..c50578d 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -21,6 +21,8 @@ pads = variant_sleep_gpio_table(&num); gpio_configure_pads(pads, num); + variant_smi_sleep(slp_typ); + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS); } @@ -41,3 +43,7 @@ { chromeec_smi_process_events(); } + +void __weak variant_smi_sleep(u8 slp_typ) +{ +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index bb41e45..e7bfd86 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -36,4 +36,7 @@ */ bool variant_mem_is_half_populated(void); +/* Allow each variants to customize SMI sleep flow. */ +void variant_smi_sleep(u8 slp_typ); + #endif /*__BASEBOARD_VARIANTS_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44587 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib43ada784666919a4d26246a683dad7f3546fabb Gerrit-Change-Number: 44587 Gerrit-PatchSet: 8 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Marco Chen <marcochen(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: merged

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coreboot-gerrit November 2020