coreboot-gerrit November 2020

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Sugnan Prabhu S (Code Review) 09 Nov '20

09 Nov '20

Sugnan Prabhu S has uploaded a new patch set (#64) to the change originally created by Rizwan Qureshi. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks, field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset, vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This will be used in the recovery scenario and also when booting with top-swap disabled i.e, RTC reset. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config INTEL_TOP_SWAP_MULTI_FIT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. Update config name and Makefile.inc TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sure that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md M Makefile.inc A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 8 files changed, 685 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/64 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 64 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Introduce HP Sure Start and the method to bypass it
by Iru Cai (vimacs) (Code Review) 09 Nov '20

09 Nov '20

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/45577 to review the following change. Change subject: Documentation: Introduce HP Sure Start and the method to bypass it ...................................................................... Documentation: Introduce HP Sure Start and the method to bypass it Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- A Documentation/mainboard/hp/hp_sure_start.md M Documentation/mainboard/index.md 2 files changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/45577/1 diff --git a/Documentation/mainboard/hp/hp_sure_start.md b/Documentation/mainboard/hp/hp_sure_start.md new file mode 100644 index 0000000..d1f3f67 --- /dev/null +++ b/Documentation/mainboard/hp/hp_sure_start.md @@ -0,0 +1,57 @@ +# HP Sure Start + +According to the [HP Sure Start Technical Whitepaper], HP Sure Start is a chipset +and processor independent firmware intrusion detection and automatic repair system. +It is implemented in HP notebooks since 2013, and desktops since 2015. + +This document talks about some mechanism of HP Sure Start on some machines, and +the method to bypass it. + +## Laptops with SMSC MEC1322 embedded controller + +Haswell EliteBook, ZBook and ProBook 600 series use SMSC MEC1322 embedded controller. +The EC firmware implements HP Sure Start. A Haswell EliteBook has two flash chips. +According to the strings in the EC firmware, the 16MB flash chip that stores the +BIOS firmware is called the *system flash*, and the 2MB flash chip that stores part +of the system flash content is called the *private flash*. + +The private flash is connected to the EC, and is not accessible by the OS. +It contains the following: + +- HP Sure Start policy header (starting with the string "POLI") +- A copy of the Intel Flash Descriptor +- A copy of the GbE firmware +- Machine Unique Data (MUD) +- Hashes of the IFD, GbE firmware and MUD, the hash algorithm is unknown +- A copy of the bootblock, UEFI PEI stage, and microcode + +If the IFD of the system flash does not match the hash in the private flash, for example, +modifying the IFD with ``ifdtool -u`` or ``me_cleaner -S``, the EC will recover the IFD. + +If the content of the private flash is lost. The EC firmware will still copy the IFD, +bootblock and PEI to the private flash. However, the IFD is not protected after that. + +HP Sure Start also verifies bootblock, PEI, and microcode without using the private flash. +EC firmware reads them from an absolute address of the system flash chip, which is +hardcoded in the EC firmware. It looks like this verification is done with a digital +signature. If the PEI volume is modified, EC firmware will recover it using the copy +in the private flash. If the private flash has no valid copies of the PEI volume, and +the PEI volume is modified, the machine will refuse to boot with the CapsLock LED blinking. + +## Bypassing HP Sure Start + +First search the mainboard for the flash chips. If there are two flash chips, +the smaller one may be the private flash. + +For Intel boards, try to modify the IFD with ``ifdtool -u``, power on and shut down +the machine, then read the flash again. If the IFD is not modified, it is likely to +be recovered from the private flash. Find the private flash and erase it, then the IFD +can be modified. + +To bypass the bootblock and PEI verification, we can modify the IFD to make the +BIOS region not overlap with the protected region. Since the EC firmware is usually +located at the high address of the flash chip (and in the protected region), +we can leave it untouched, and do not need to extract the EC firmware to put it in +the coreboot image. + +[HP Sure Start Technical Whitepaper]: http://h10032.www1.hp.com/ctg/Manual/c05163901 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 0eefee8..335eae2 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -61,6 +61,7 @@ ### EliteBook series - [HP Laptops with KBC1126 EC](hp/hp_kbc1126_laptops.md) +- [HP Sure Start](hp/hp_sure_start.md) - [EliteBook 2560p](hp/2560p.md) - [EliteBook 8760w](hp/8760w.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/45577 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id198afdaa13b4c361e1b77a56d5a2436ed1c4c86 Gerrit-Change-Number: 45577 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab
by HAOUAS Elyes (Code Review) 09 Nov '20

09 Nov '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46328 ) Change subject: soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab ...................................................................... soc/nvidia/tegra124/include/soc/clk_rst.h: Remove extra tab Change-Id: I0c606fd129c200446744f7a67ae63fec6d8e1684 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/nvidia/tegra124/include/soc/clk_rst.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/46328/1 diff --git a/src/soc/nvidia/tegra124/include/soc/clk_rst.h b/src/soc/nvidia/tegra124/include/soc/clk_rst.h index 0b0e025..cfddd10 100644 --- a/src/soc/nvidia/tegra124/include/soc/clk_rst.h +++ b/src/soc/nvidia/tegra124/include/soc/clk_rst.h @@ -257,7 +257,7 @@ u32 spare_reg0; /* _SPARE_REG0, 0x55c */ u32 _rsv32[4]; /* 0x560-0x56c */ u32 plld2_ss_cfg; /* _PLLD2_SS_CFG 0x570 */ - u32 _rsv32_1[7]; /* 0x574-58c */ + u32 _rsv32_1[7]; /* 0x574-58c */ u32 plldp_base; /* _PLLDP_BASE, 0x590 */ u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/46328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c606fd129c200446744f7a67ae63fec6d8e1684 Gerrit-Change-Number: 46328 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4
by Michał Żygowski (Code Review) 09 Nov '20

09 Nov '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47058 ) Change subject: cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4 ...................................................................... cpu/intel/model_206ax: Get CPU frequencies for SMBIOS type 4 Calculate the frequencies based on the appropriate MSRs adn pass them to SMBIOS tables generator. Ivybridge microarchitecture does not yet implement CPUID 16H leaf to obtain the required frequencies. TEST=Intel Core i7-3770, TianoCore UEFI payload displays the CPU frequency correctly equal 3.4GHz in Boot Manager Menu, dmidecode shows correct frequencies according to Intel ARK, 3.4Ghz base and 3.9GHz turbo Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb --- M src/cpu/intel/model_206ax/model_206ax_init.c 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/47058/1 diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 7fb412c..2afbfee 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -18,6 +18,7 @@ #include "chip.h" #include <cpu/intel/smm_reloc.h> #include <cpu/intel/common/common.h> +#include <smbios.h> /* * List of supported C-states in this processor @@ -360,6 +361,25 @@ ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK); } +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + return (msr.lo & 0xff) * SANDYBRIDGE_BCLK; +} + +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK; +} + +unsigned int smbios_processor_external_clock(void) +{ + return SANDYBRIDGE_BCLK; +} + static void configure_mca(void) { msr_t msr; -- To view, visit https://review.coreboot.org/c/coreboot/+/47058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefbae6111d39107eacac7e61654311646c6981eb Gerrit-Change-Number: 47058 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Enable Intel FIVR RFI settings
by Maulik V Vaghela (Code Review) 09 Nov '20

09 Nov '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47286 ) Change subject: soc/intel/jasperlake: Enable Intel FIVR RFI settings ...................................................................... soc/intel/jasperlake: Enable Intel FIVR RFI settings We already have RFI settings UPD to mitigate RFI noise issues in platform. These UPDs were not getting filled via devicetree but needed to be filled from fsp_params.c Exporting these UPDs to chip.h will allow OEM/ODMs to fill it directly from devicetree and also allow us to control it based on boards instead of keeping it common across SoCs. BUG=b:171683785 BRANCH=None TEST=Compilation works and we're able to fill UPD from devicetree.Value gets reflected in FSP UPDs. Change-Id: I495cd2294368e6b3035c48b9556a83418d5632de Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/47286/1 diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 5e90530..16712c7 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -342,6 +342,25 @@ * - PM_CFG.SLP_LAN_MIN_ASST_WDTH */ uint8_t PchPmPwrCycDur; + + /* + * FIVR RFI Frequency + * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. + * 0: Auto. + * Range varies based on XTAL clock: + * 0-1918 (Up to 191.8HMz) for 24MHz clock; + * 0-1535 (Up to 153.5MHz) for 19MHz clock. + */ + uint16_t FivrRfiFrequency; + + /* + * FIVR RFI Spread Spectrum + * Set the Spread Spectrum Range. <b>1.5%</b>; + * Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%,6%. + * Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1% + * = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44. + */ + uint8_t FivrSpreadSpectrum; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index db27234..92c35c6 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -216,6 +216,10 @@ /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* Configure FIVR RFI related settings */ + params->FivrRfiFrequency = config->FivrRfiFrequency; + params->FivrSpreadSpectrum = config->FivrSpreadSpectrum; + /* Apply minimum assertion width settings if non-zero */ if (config->PchPmSlpS3MinAssert) params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; -- To view, visit https://review.coreboot.org/c/coreboot/+/47286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I495cd2294368e6b3035c48b9556a83418d5632de Gerrit-Change-Number: 47286 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/q35: Define pm_acpi_smi_cmd_port
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45814 ) Change subject: mb/emulation/q35: Define pm_acpi_smi_cmd_port ...................................................................... mb/emulation/q35: Define pm_acpi_smi_cmd_port The X86 Qemu targets use the AMD64 SMM save state, but unlike most AMD CPU's the PM ACPI SMI port is not configurable and uses the Intel default APM_CNT, 0xb2 port. This will be used by the common save state handler. Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/emulation/qemu-q35/Makefile.inc A src/mainboard/emulation/qemu-q35/smi.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/45814/1 diff --git a/src/mainboard/emulation/qemu-q35/Makefile.inc b/src/mainboard/emulation/qemu-q35/Makefile.inc index e142d4d..59c61c4 100644 --- a/src/mainboard/emulation/qemu-q35/Makefile.inc +++ b/src/mainboard/emulation/qemu-q35/Makefile.inc @@ -14,3 +14,5 @@ verstage-$(CONFIG_CHROMEOS) += chromeos.c verstage-$(CONFIG_CHROMEOS) += ../qemu-i440fx/fw_cfg.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi.c \ No newline at end of file diff --git a/src/mainboard/emulation/qemu-q35/smi.c b/src/mainboard/emulation/qemu-q35/smi.c new file mode 100644 index 0000000..5d8d482 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/smi.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> + +/* The X86 qemu target uses AMD64 save states but the APM port is not configurable. */ +uint16_t pm_acpi_smi_cmd_port(void) +{ + return APM_CNT; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/45814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifee9476f628a2df710fb4340ce6a19b008df1033 Gerrit-Change-Number: 45814 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45813 ) Change subject: soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration ...................................................................... soc/amd/*/smi.h: Move the pm_acpi_smi_cmd_port function declaration This prototype will be used outside of soc/amd. Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/include/cpu/x86/smm.h M src/soc/amd/picasso/include/soc/smi.h M src/soc/amd/picasso/smi_util.c M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/smi_util.c 5 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/45813/1 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index 1073d03..6cf6f82 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -197,5 +197,8 @@ /* Return the SMM save state revision. The revision can be fetched from the smm savestate which is always at the same offset downward from the top of the save state. */ uint32_t smm_revision(void); +/* Returns the PM ACPI SMI port. On Intel systems this typically not configurable (APM_CNT, 0xb2). + On AMD systems it is sometimes configurable. */ +uint16_t pm_acpi_smi_cmd_port(void); #endif /* CPU_X86_SMM_H */ diff --git a/src/soc/amd/picasso/include/soc/smi.h b/src/soc/amd/picasso/include/soc/smi.h index a629fc5..ee47676 100644 --- a/src/soc/amd/picasso/include/soc/smi.h +++ b/src/soc/amd/picasso/include/soc/smi.h @@ -213,7 +213,6 @@ uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/picasso/smi_util.c b/src/soc/amd/picasso/smi_util.c index 2c5085b..2fbc8e2 100644 --- a/src/soc/amd/picasso/smi_util.c +++ b/src/soc/amd/picasso/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h index f7cacea..15bba0f 100644 --- a/src/soc/amd/stoneyridge/include/soc/smi.h +++ b/src/soc/amd/stoneyridge/include/soc/smi.h @@ -211,7 +211,6 @@ uint8_t level; /* Edge or Level, smi_sci_dir */ }; -uint16_t pm_acpi_smi_cmd_port(void); void configure_smi(uint8_t smi_num, uint8_t mode); void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); void configure_scimap(const struct sci_source *sci); diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c index 2c5085b..2fbc8e2 100644 --- a/src/soc/amd/stoneyridge/smi_util.c +++ b/src/soc/amd/stoneyridge/smi_util.c @@ -5,6 +5,7 @@ */ #include <console/console.h> +#include <cpu/x86/smm.h> #include <soc/southbridge.h> #include <soc/smi.h> #include <amdblocks/acpimmio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/45813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121 Gerrit-Change-Number: 45813 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: [WIP] SMM save states
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44323 ) Change subject: [WIP] SMM save states ...................................................................... [WIP] SMM save states Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/smm/Makefile.inc A src/cpu/intel/smm/em64t101_save_state.c M src/cpu/x86/smm/Makefile.inc A src/cpu/x86/smm/save_state.c M src/cpu/x86/smm/smm.ld A src/include/cpu/x86/save_state.h M src/lib/program.ld M src/southbridge/intel/i82801ix/smihandler.c 8 files changed, 210 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44323/1 diff --git a/src/cpu/intel/smm/Makefile.inc b/src/cpu/intel/smm/Makefile.inc index a49b796..df73ae7 100644 --- a/src/cpu/intel/smm/Makefile.inc +++ b/src/cpu/intel/smm/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm_reloc.c +smm-y += em64t101_save_state.c diff --git a/src/cpu/intel/smm/em64t101_save_state.c b/src/cpu/intel/smm/em64t101_save_state.c new file mode 100644 index 0000000..404906b --- /dev/null +++ b/src/cpu/intel/smm/em64t101_save_state.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <string.h> +#include <cpu/x86/save_state.h> +#include <cpu/intel/em64t101_save_state.h> + +static void *em64t101_get_reg_base(const enum cpu_reg reg, const int node) +{ + const em64t101_smm_state_save_area_t *save_state = (const em64t101_smm_state_save_area_t *)smm_get_save_state(node); + + switch (reg) { + case RAX: + return (void *)&save_state->rax; + case RBX: + return (void *)&save_state->rbx; + case RCX: + return (void *)&save_state->rcx; + case RDX: + return (void *)&save_state->rdx; + } + + return NULL; +} + +enum get_set { + GET, + SET +}; + +static int em64t101_get_set(const enum get_set op_type, const enum cpu_reg reg, + const int node, void *in_out, const uint8_t length) +{ + + void *reg_base = em64t101_get_reg_base(reg, node); + + if (!reg_base) + return -1; + + switch (length) { + case 1: + case 2: + case 4: + case 8: + switch (op_type) { + case GET: + memcpy(in_out, reg_base, length); + return 0; + case SET: + memcpy(reg_base, in_out, length); + } + } + + return -1; +} + +static int em64t101_get_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + return em64t101_get_set(GET, reg, node, out, length); +} + +static int em64t101_set_reg(const enum cpu_reg reg, const int node, void *in, const uint8_t length) +{ + return em64t101_get_set(SET, reg, node, in, length); +} + +static int em64t101_apmc_node(u8 cmd) +{ + em64t101_smm_state_save_area_t *state; + int node; + + for (node = 0; node < CONFIG_MAX_CPUS; node++) { + state = smm_get_save_state(node); + + /* Check for Synchronous IO (bit0 == 1) */ + if (!(state->io_misc_info & (1 << 0))) + continue; + + /* Make sure it was a write (bit4 == 0) */ + if (state->io_misc_info & (1 << 4)) + continue; + + /* Check for APMC IO port */ + if (((state->io_misc_info >> 16) & 0xff) != APM_CNT) + continue; + + /* Check AX against the requested command */ + if ((state->rax & 0xff) != cmd) + continue; + + return node; + } + + return -1; +} + +static const uint32_t revisions[] = { + 0x00030101, + SMM_REV_INVALID, +}; + +static const struct smm_save_state_ops ops __smm_save_state_ops = { + .revision_table = revisions, + .get_reg = em64t101_get_reg, + .set_reg = em64t101_set_reg, + .apmc_node = em64t101_apmc_node, +}; diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index bbd96c6..2b3e073 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -28,6 +28,8 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual endif +smm-y += save_state.c + ifeq ($(CONFIG_SMM_TSEG),y) ramstage-y += tseg_region.c diff --git a/src/cpu/x86/smm/save_state.c b/src/cpu/x86/smm/save_state.c new file mode 100644 index 0000000..7c757e3 --- /dev/null +++ b/src/cpu/x86/smm/save_state.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cpu/x86/smm.h> +#include <cpu/x86/save_state.h> + +static struct smm_save_state_ops *save_state; + +/* Returns -1 on failure, 0 on success */ +static int init_save_state(void) +{ + const uint32_t revision = smm_revision(); + struct smm_save_state_ops *ops; + static bool initialized = false; + + if (initialized) + return 0; + + for (ops = _smm_save_state_ops; ops < _esmm_save_state_ops; ops++) { + const uint32_t *rev; + for (rev = ops->revision_table; *rev != SMM_REV_INVALID; rev++) + if (*rev == revision) { + save_state = ops; + initialized = true; + return 0; + } + } + + return -1; +} + +int get_apmc_node(u8 cmd) +{ + if (init_save_state()) + return -1; + + return save_state->apmc_node(cmd); +} + +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length) +{ + if (init_save_state()) + return -1; + + return save_state->get_reg(reg, node, out, length); +} diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index 2f46975..39afee4 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -25,6 +25,11 @@ /* C read-only data of the SMM handler */ . = ALIGN(16); + + _smm_save_state_ops = .; + KEEP(*(.rodata.smm_ops)); + _esmm_save_state_ops = .; + *(.rodata) *(.rodata.*) diff --git a/src/include/cpu/x86/save_state.h b/src/include/cpu/x86/save_state.h new file mode 100644 index 0000000..b97890b --- /dev/null +++ b/src/include/cpu/x86/save_state.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __CPU_X86_SAVE_STATE_H__ +#define __CPU_X86_SAVE_STATE_H__ + +#include <stdint.h> + +#if ENV_SMM +#define __smm_save_state_ops __attribute__((used, __section__(".rodata.smm_ops"))) +#else +#define __smm_save_state_ops __attribute__((unused)) +#endif + +enum cpu_reg { + RAX, + RBX, + RCX, + RDX +}; + +#define SMM_REV_INVALID 0xffffffff + +struct smm_save_state_ops { + const uint32_t *revision_table; + /* Accessors for CPU registers in the SMM save state + Returns -1 on failure, 0 on success */ + int (*get_reg)(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + int(*set_reg)(const enum cpu_reg reg, const int node, void *in, const uint8_t length); + /* Returns -1 on failure, the node on which the 'cmd' was send on success */ + int(*apmc_node)(u8 cmd); +}; + +/** start of compile time generated pci driver array */ +extern struct smm_save_state_ops _smm_save_state_ops[]; +/** end of compile time generated pci driver array */ +extern struct smm_save_state_ops _esmm_save_state_ops[]; + +int get_apmc_node(u8 cmd); +int get_save_state_reg(const enum cpu_reg reg, const int node, void *out, const uint8_t length); + +#endif /* __CPU_X86_SAVE_STATE_H__ */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 88a3126..1894ae0 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -44,6 +44,13 @@ _ecpu_drivers = .; #endif +#if ENV_SMM || ENV_RMODULE + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); + _smm_save_state_ops = .; + KEEP(*(.rodata.smm_ops)); + _esmm_save_state_ops = .; +#endif + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); *(.rodata); *(.rodata.*); diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 699f51f..9b37f05 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -3,6 +3,7 @@ #include <types.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <cpu/x86/save_state.h> #include <device/pci_def.h> #include <southbridge/intel/common/pmutil.h> #include "i82801ix.h" @@ -31,6 +32,8 @@ return 1; /* IO trap handled */ } + get_apmc_node(5); + /* Not handled */ return 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a31d05c09065543424a9010ac434dde0dfb5836 Gerrit-Change-Number: 44323 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44322 ) Change subject: cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4 ...................................................................... cpu/x86/smm/smm.ld: Assert that CONFIG_MAX_CPUS <= 4 The SMM_ASEG code only supports up to 4 CPUs, so assert this at buildtime. Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smm.ld 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44322/1 diff --git a/src/cpu/x86/smm/smm.ld b/src/cpu/x86/smm/smm.ld index af5968d..2f46975 100644 --- a/src/cpu/x86/smm/smm.ld +++ b/src/cpu/x86/smm/smm.ld @@ -2,6 +2,9 @@ /* Maximum number of CPUs/cores */ CPUS = 4; + +_ = ASSERT(CPUS > CONFIG_MAX_CPUS, "The ASEG SMM code only supports up to 4 CPUS"); + ENTRY(smm_handler_start); SECTIONS -- To view, visit https://review.coreboot.org/c/coreboot/+/44322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec803cd1b76f17f4dccd5c573179d542d54c277 Gerrit-Change-Number: 44322 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: cpu/x86/smm/smihandler.c: Simplify smm revision handling
by Arthur Heymans (Code Review) 09 Nov '20

09 Nov '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45471 ) Change subject: cpu/x86/smm/smihandler.c: Simplify smm revision handling ...................................................................... cpu/x86/smm/smihandler.c: Simplify smm revision handling The ASEG smihandler bails out if an unsupported SMM save state revision is detected. Now we have code to find the SMM save state depending on the SMM save state revision so reuse this to do the same. This also increases the loglevel when bailing out of SMM due to unsupported SMM save state revision from BIOS_DEBUG to BIOS_WARNING, given that the system likely still boots but won't have a functioning smihandler. Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/x86/smm/smihandler.c 1 file changed, 3 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/45471/1 diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index 077fa8d..dea4cf3 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -14,23 +14,6 @@ #include <spi-generic.h> #endif -typedef enum { - AMD64, - EM64T100, - EM64T101, - LEGACY -} save_state_type_t; - -typedef struct { - save_state_type_t type; - union { - amd64_smm_state_save_area_t *amd64_state_save; - em64t100_smm_state_save_area_t *em64t100_state_save; - em64t101_smm_state_save_area_t *em64t101_state_save; - legacy_smm_state_save_area_t *legacy_state_save; - }; -} smm_state_save_area_t; - static int do_driver_init = 1; typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -162,9 +145,6 @@ void smi_handler(void) { unsigned int node; - const uint32_t smm_rev = smm_revision(); - smm_state_save_area_t state_save; - u32 smm_base = SMM_BASE; /* ASEG */ /* Are we ok to execute the handler? */ if (!smi_obtain_lock()) { @@ -190,36 +170,9 @@ printk(BIOS_SPEW, "\nSMI# #%d\n", node); - switch (smm_rev) { - case 0x00030002: - case 0x00030007: - state_save.type = LEGACY; - state_save.legacy_state_save = - smm_save_state(smm_base, - SMM_LEGACY_ARCH_OFFSET, node); - break; - case 0x00030100: - state_save.type = EM64T100; - state_save.em64t100_state_save = - smm_save_state(smm_base, - SMM_EM64T100_ARCH_OFFSET, node); - break; - case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ - state_save.type = EM64T101; - state_save.em64t101_state_save = - smm_save_state(smm_base, - SMM_EM64T101_ARCH_OFFSET, node); - break; - case 0x00020064: - case 0x00030064: - state_save.type = AMD64; - state_save.amd64_state_save = - smm_save_state(smm_base, - SMM_AMD64_ARCH_OFFSET, node); - break; - default: - printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_rev); - printk(BIOS_DEBUG, "SMI# not supported on your CPU\n"); + if (smm_get_save_state(node) == NULL) { + printk(BIOS_WARNING, "smm_revision: 0x%08x\n", smm_revision()); + printk(BIOS_WARNING, "SMI# not supported on your CPU\n"); /* Don't release lock, so no further SMI will happen, * if we don't handle it anyways. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/45471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57198f0c85c0f7a1fa363d3bd236c3d41b68d2f0 Gerrit-Change-Number: 45471 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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