Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34517 )
Change subject: soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
......................................................................
soc/intel/{cnl,icl}: Enable support to configure interrupt overrides
This implementation selects SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE
config. It would enable support from SOC to dynamically populate the
PCI IRQ routing table based on the devices enabled from the mainboard.
And pass the same to FSP to configure the IRQ entries in ITSS PIRx
register. The same table can be used to generate the ACPI PIRQ mapping
table.
Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/icelake/Kconfig
2 files changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/34517/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f859cd5..0283f2c 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -97,6 +97,7 @@
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 5dca44b..79a19ee 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -51,6 +51,7 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
select SSE2
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I8464d5797cb4ff85406c06e1ecb92c7207380acd
Gerrit-Change-Number: 34517
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-MessageType: newchange
Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34348 )
Change subject: src/soc/intel/*/include: Get list of devices that needs IRQ programming
......................................................................
src/soc/intel/*/include: Get list of devices that needs IRQ programming
This implementation adds SOC function that returns list of PCI devices
that needs IRQ programming. This list can be further used to program
IRQ for these devices.
Change-Id: I3482172f6cb549dece23e2b8b09b8b79578b83b7
Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com>
---
M src/soc/intel/cannonlake/Makefile.inc
A src/soc/intel/cannonlake/irq.c
M src/soc/intel/icelake/Makefile.inc
A src/soc/intel/icelake/irq.c
4 files changed, 150 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34348/1
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 8a4a8b7..ed0d09c 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -41,6 +41,7 @@
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += i2c.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c
ramstage-y += lockdown.c
ramstage-y += lpc.c
ramstage-y += me.c
diff --git a/src/soc/intel/cannonlake/irq.c b/src/soc/intel/cannonlake/irq.c
new file mode 100644
index 0000000..ce0e539
--- /dev/null
+++ b/src/soc/intel/cannonlake/irq.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/irq.h>
+#include <soc/pci_devs.h>
+#include <stdint.h>
+
+static const int irq_devices[] = {
+ PCH_DEVFN_HDA,
+ PCH_DEVFN_SMBUS,
+ PCH_DEVFN_GBE,
+ PCH_DEVFN_TRACEHUB,
+ PCH_DEVFN_PCIE9,
+ PCH_DEVFN_PCIE10,
+ PCH_DEVFN_PCIE11,
+ PCH_DEVFN_PCIE12,
+ PCH_DEVFN_PCIE13,
+ PCH_DEVFN_PCIE14,
+ PCH_DEVFN_PCIE15,
+ PCH_DEVFN_PCIE16,
+ PCH_DEVFN_PCIE1,
+ PCH_DEVFN_PCIE2,
+ PCH_DEVFN_PCIE3,
+ PCH_DEVFN_PCIE4,
+ PCH_DEVFN_PCIE5,
+ PCH_DEVFN_PCIE6,
+ PCH_DEVFN_PCIE7,
+ PCH_DEVFN_PCIE8,
+ PCH_DEVFN_EMMC,
+ PCH_DEVFN_SATA,
+ PCH_DEVFN_CSE,
+ PCH_DEVFN_CSE_2,
+ PCH_DEVFN_CSE_IDER,
+ PCH_DEVFN_CSE_KT,
+ PCH_DEVFN_CSE_3,
+ PCH_DEVFN_CSE_4,
+ PCH_DEVFN_XHCI,
+ PCH_DEVFN_USBOTG,
+ PCH_DEVFN_CNViWIFI,
+ PCH_DEVFN_SDCARD,
+ PCH_DEVFN_ISH,
+ PCH_DEVFN_THERMAL,
+ PCH_DEVFN_UFS,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_UART2,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_GSPI2,
+};
+
+const int *get_soc_irq_devices(size_t *size)
+{
+ *size = ARRAY_SIZE(irq_devices);
+ return irq_devices;
+}
diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc
index cd02934..2973e15 100644
--- a/src/soc/intel/icelake/Makefile.inc
+++ b/src/soc/intel/icelake/Makefile.inc
@@ -43,6 +43,7 @@
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += i2c.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_ITSS_INTERRUPT_OVERRIDE) += irq.c
ramstage-y += lockdown.c
ramstage-y += memmap.c
ramstage-y += p2sb.c
diff --git a/src/soc/intel/icelake/irq.c b/src/soc/intel/icelake/irq.c
new file mode 100644
index 0000000..ce0e539
--- /dev/null
+++ b/src/soc/intel/icelake/irq.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <intelblocks/irq.h>
+#include <soc/pci_devs.h>
+#include <stdint.h>
+
+static const int irq_devices[] = {
+ PCH_DEVFN_HDA,
+ PCH_DEVFN_SMBUS,
+ PCH_DEVFN_GBE,
+ PCH_DEVFN_TRACEHUB,
+ PCH_DEVFN_PCIE9,
+ PCH_DEVFN_PCIE10,
+ PCH_DEVFN_PCIE11,
+ PCH_DEVFN_PCIE12,
+ PCH_DEVFN_PCIE13,
+ PCH_DEVFN_PCIE14,
+ PCH_DEVFN_PCIE15,
+ PCH_DEVFN_PCIE16,
+ PCH_DEVFN_PCIE1,
+ PCH_DEVFN_PCIE2,
+ PCH_DEVFN_PCIE3,
+ PCH_DEVFN_PCIE4,
+ PCH_DEVFN_PCIE5,
+ PCH_DEVFN_PCIE6,
+ PCH_DEVFN_PCIE7,
+ PCH_DEVFN_PCIE8,
+ PCH_DEVFN_EMMC,
+ PCH_DEVFN_SATA,
+ PCH_DEVFN_CSE,
+ PCH_DEVFN_CSE_2,
+ PCH_DEVFN_CSE_IDER,
+ PCH_DEVFN_CSE_KT,
+ PCH_DEVFN_CSE_3,
+ PCH_DEVFN_CSE_4,
+ PCH_DEVFN_XHCI,
+ PCH_DEVFN_USBOTG,
+ PCH_DEVFN_CNViWIFI,
+ PCH_DEVFN_SDCARD,
+ PCH_DEVFN_ISH,
+ PCH_DEVFN_THERMAL,
+ PCH_DEVFN_UFS,
+ PCH_DEVFN_UART0,
+ PCH_DEVFN_UART1,
+ PCH_DEVFN_GSPI0,
+ PCH_DEVFN_GSPI1,
+ PCH_DEVFN_UART2,
+ PCH_DEVFN_I2C5,
+ PCH_DEVFN_I2C4,
+ PCH_DEVFN_I2C0,
+ PCH_DEVFN_I2C1,
+ PCH_DEVFN_I2C2,
+ PCH_DEVFN_I2C3,
+ PCH_DEVFN_GSPI2,
+};
+
+const int *get_soc_irq_devices(size_t *size)
+{
+ *size = ARRAY_SIZE(irq_devices);
+ return irq_devices;
+}
--
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Gerrit-Change-Number: 34348
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Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34089 )
Change subject: src/soc/intel/common/itss: Add support to get IRQ configuration for PCI devices
......................................................................
Patch Set 21:
This change is ready for review.
--
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